diff --git a/SheepShaver/src/Unix/main_unix.cpp b/SheepShaver/src/Unix/main_unix.cpp
index ff56e9d0..a3d7bc11 100644
--- a/SheepShaver/src/Unix/main_unix.cpp
+++ b/SheepShaver/src/Unix/main_unix.cpp
@@ -632,6 +632,8 @@ int main(int argc, char **argv)
 					PVR = 0x000a0000;
 				else if (strcmp(value, "750") == 0)
 					PVR = 0x00080000;
+				else if (strcmp(value, "750FX") == 0)
+					PVR = 0x70000000;
 				else if (strcmp(value, "821") == 0)
 					PVR = 0x00320000;
 				else if (strcmp(value, "860") == 0)
@@ -640,6 +642,12 @@ int main(int argc, char **argv)
 					PVR = 0x000c0000;
 				else if (strcmp(value, "7410") == 0)
 					PVR = 0x800c0000;
+				else if (strcmp(value, "7450") == 0)
+					PVR = 0x80000000;
+				else if (strcmp(value, "7455") == 0)
+					PVR = 0x80010000;
+				else if (strcmp(value, "7457") == 0)
+					PVR = 0x80020000;
 				else
 					printf("WARNING: Unknown CPU type '%s', assuming 604\n", value);
 			}
diff --git a/SheepShaver/src/name_registry.cpp b/SheepShaver/src/name_registry.cpp
index 8fad055b..85b9abb0 100644
--- a/SheepShaver/src/name_registry.cpp
+++ b/SheepShaver/src/name_registry.cpp
@@ -217,7 +217,8 @@ void DoPatchNameRegistry(void)
 					u32.set_value(64);
 					RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
 					break;
-				case 8:		// 750
+				case 8:		// 750, 750FX
+				case 0x7000:
 					u32.set_value(32);
 					RegistryPropertyCreate(power_pc.ptr(), "d-cache-block-size", u32.ptr(), 4);
 					u32.set_value(256);
@@ -254,8 +255,11 @@ void DoPatchNameRegistry(void)
 					u32.set_value(128);
 					RegistryPropertyCreate(power_pc.ptr(), "tlb-size", u32.ptr(), 4);
 					break;
-				case 12:	// 7400, 7410
+				case 12:	// 7400, 7410, 7450, 7455, 7457
 				case 0x800c:
+				case 0x8000:
+				case 0x8001:
+				case 0x8002:
 					u32.set_value(32);
 					RegistryPropertyCreate(power_pc.ptr(), "d-cache-block-size", u32.ptr(), 4);
 					u32.set_value(128);
diff --git a/SheepShaver/src/rom_patches.cpp b/SheepShaver/src/rom_patches.cpp
index eb13d459..11ea232d 100644
--- a/SheepShaver/src/rom_patches.cpp
+++ b/SheepShaver/src/rom_patches.cpp
@@ -847,7 +847,8 @@ static bool patch_nanokernel_boot(void)
 			lp[7] = htonl(0x00040004);	// Inst cache assoc/Data cache assoc
 			lp[8] = htonl(0x00400002);	// TLB total size/TLB assoc
 			break;
-		case 8:		// 750
+		case 8:		// 750, 750FX
+		case 0x7000:
 			lp[0] = htonl(0x1000);		// Page size
 			lp[1] = htonl(0x8000);		// Data cache size
 			lp[2] = htonl(0x8000);		// Inst cache size
@@ -871,8 +872,11 @@ static bool patch_nanokernel_boot(void)
 			lp[8] = htonl(0x00800002);	// TLB total size/TLB assoc
 			break;
 //		case 11:	// X704?
-		case 12:	// 7400, 7410
+		case 12:	// 7400, 7410, 7450, 7455, 7457
 		case 0x800c:
+		case 0x8000:
+		case 0x8001:
+		case 0x8002:
 			lp[0] = htonl(0x1000);		// Page size
 			lp[1] = htonl(0x8000);		// Data cache size
 			lp[2] = htonl(0x8000);		// Inst cache size