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1,378 Commits 6 Branches 17 Tags
Commit Graph

143 Commits

Author SHA1 Message Date
gbeauche
d91e8b2a8f fix "banks" addressing mode for 64-bit platforms 2005-05-13 11:05:56 +00:00
gbeauche
380a9ed970 ensure allocated code fits under 32-bit boundaries 2005-04-24 23:02:48 +00:00
gbeauche
165b32da39 Fix build with gcc4 on x86-64: ignore errors when casting pointers to int 
from regs & fpu members + code cache. This is possible because data is
allocated in 32-bit space and we force allocation of translation cache to
those bounds too.
 2005-04-24 23:00:08 +00:00
gbeauche
57169c7923 Recognize lahf_lm from Dual Core Opterons. This enables use of LAHF/SETO 
instructions in long mode (64-bit). However, there seems to be another bug
in the JIT preventing it from being fully supported. m68k.h & codegen_x86.h
are easily fixed bug another patch is still needed.
 2005-04-21 09:08:57 +00:00
gbeauche
5c001ba645 Allocate executable space to detect cpu features (cpuid). aka don't crash 
on non-executable .data sections on x86-64 with NX support enabled.
 2005-03-22 16:12:18 +00:00
gbeauche
608c1f65bd close opened files and make sure to flush stdout on exit, this used to 
cause weird results on windows otherwise
 2005-03-17 00:21:36 +00:00
gbeauche
30632aed4f Happy New Year! 2005-01-30 21:42:16 +00:00
gbeauche
a6bf2d0928 add some code to gather stats on m68k registers used in translated blocks 2004-11-20 23:35:16 +00:00
gbeauche
6774a0821d fix tester for BSF flags handling 2004-11-11 07:07:55 +00:00
gbeauche
20f5f531ca fix inline dispatcher to really generate a cmove on x86-64 (silly bug!) 2004-11-08 23:24:54 +00:00
gbeauche
0c255e1fbd Merge BSF simulation on P4 from Amithlon. Use 33-bit memory addressing model. 2004-11-08 21:10:46 +00:00
gbeauche
0ba075050c Enable RIP-relative addressing, optimize REX conditions processing in 
! X86_FLAT_REGISTERS mode, fix __REX_mem encodings (e.g. POPLm)
 2004-11-08 20:48:19 +00:00
gbeauche
c21650b7a8 fix protection changes on translation cache + cosmetic fixlet 2004-11-02 23:52:00 +00:00
gbeauche
3fcceb052c fix JIT FPU for x86_64 2004-11-02 23:28:19 +00:00
gbeauche
129f80faf6 preserve r11 as the register used to resolve pointers to functions 2004-11-01 18:40:30 +00:00
gbeauche
b3bd00f159 - affine need_to_preserve[] to get close to linux/x86_64 ABI 
- optimize NOP fillers on x86-64 (based on GNU as implementation)
 2004-11-01 17:12:55 +00:00
gbeauche
e58fbc745b revive and fix almost two-year old port to x86_64 2004-11-01 16:01:51 +00:00
gbeauche
730364ac1e - optimize absolute addresses into RIP relative, if possible 
- fix MOVQir as the operand is 64-bit
- fix IMULWrr, IMULLrr, IMULQrr, MOVSBWrr, MOVZBWrr
 2004-11-01 15:37:40 +00:00
gbeauche
c12d2fa0ea add dumb but handy brute-force runtime assembler verifier, someone will 
probably want to rewrite it to use BFD/opcodes internals for checks
 2004-11-01 15:30:46 +00:00
gbeauche
33be2e8ace Reorder SPL, BPL, SIL, DIL IDs so that 8-bit register allocation is simpler 
Fix MOVZBL and MOVSBL encodings with those extended 8-bit registers
 2004-10-31 16:02:04 +00:00
gbeauche
87b79bdc20 fix SIB encoding with base=r13 
fix PUSH/POP with x86_64 extended registers
fix CALL/JMP REX prefixes
 2004-10-24 22:22:49 +00:00
cebix
9e7932abf0 Happy New Year! :) 2004-01-12 15:29:31 +00:00
gbeauche
45df157a5e Implement lazy icache range invalidation. Disable for now until it shows 
a real benefit over only 2%
 2003-11-21 14:20:01 +00:00
gbeauche
3630404307 fix fp_do_sgn1() for "double"-targets 2003-11-21 13:27:47 +00:00
gbeauche
309c2f0bd5 Add "jitblacklist" prefs item so that opcodes ranges could be excluded for 
translation. This should help debugging of (badly) translated code.

Usage: jitblacklist xxxx(-yyyy)?(;xxxx(-yyyy)?)*
where xxxx/yyyy are hexadecimal numbers
 2003-10-14 10:29:19 +00:00
gbeauche
b66f5972f9 Make sure a 32-bit B2/JIT works reasonnably well on AMD64 too. This implies 
to force RAMBaseHost < 0x80000000. This is empirically determined to work on
Linux/x86 and Linux/amd64.
 2003-10-03 18:18:15 +00:00
gbeauche
87e4d48b3e flags are live after a call to fflags_into_flags_internal() 2003-10-02 09:51:14 +00:00
gbeauche
c464b19f06 get a chance to see some illegal instruction variants if we ever come to 
encounter them.
 2003-10-02 09:48:10 +00:00
gbeauche
f3ad33ed58 Call correct PUSHF/POPF macro 2003-06-03 09:01:03 +00:00
gbeauche
04167990a6 workaround a compiler bug on SPARC (Milan) 2003-05-28 10:17:43 +00:00
gbeauche
ccdec0782b really make long double values (Milan) 2003-05-28 10:14:14 +00:00
gbeauche
3863961d26 - Fix "extended register" predicate to exclude X86_NOREG and X86_RIP 
- Really handle requested 32-bit absolute address in AMD64 target
- Fix REX prefixes in 16-bit ALU instructions
- Fix POPF, remove useless? POPFD and PUSHFD
 2003-05-19 17:15:17 +00:00
nigel
21c4e9da5b Building on GCC 2 causes errors: 
../uae_cpu/gencpu.c: In function `void gen_opcode(long unsigned int)':
../uae_cpu/gencpu.c:874: conversion from `unsigned int' to `enum wordsizes'
../uae_cpu/gencpu.c:875: conversion from `unsigned int' to `enum amodes'
due to mismatching of types in struct instr and types in function prototypes.
However, this only started happening recently and I don't know why :-(
 2003-04-01 05:26:07 +00:00
gbeauche
9ed554b3a9 Remove some dead code. Start implementation of optimized calls to interpretive 
fallbacks for untranslatable instruction handlers. Disabled for now since
call_m_01() is not correctly imeplemented yet.
 2003-03-21 19:12:44 +00:00
gbeauche
b48a5a3253 Detect x86-64 2003-03-20 13:49:49 +00:00
gbeauche
96ae75cd7e Optimize TEST[BWLQ]ir case where dest register is %rax 
Add JCCSii and JCCii which directly takes the displacement value to encode
 2003-03-19 17:06:22 +00:00
gbeauche
ecab19aa4e Emulate CMOV in the new code generator for processors that don't support 
this intruction
 2003-03-19 17:05:02 +00:00
gbeauche
06af072a40 Add missing wrappers of the new runtime-assembler primitives 2003-03-19 16:32:51 +00:00
gbeauche
a3b815366a Add facility to filter out some opcodes from the compfunctbl[] et al. 2003-03-19 16:28:23 +00:00
gbeauche
547bd6ab2c Fix MOVBrr 2003-03-19 16:25:12 +00:00
gbeauche
c4bf8e0695 Fix 0(%rbp,<reg>,1) operand encoding 2003-03-19 11:34:10 +00:00
gbeauche
da8d81509e Add new backend, disabled for until it's proofread and fully functional 
Remove obsolete string-related instructions
 2003-03-18 17:26:32 +00:00
gbeauche
5fb74e3592 Add sign/zero-extend instructions 2003-03-18 17:01:44 +00:00
gbeauche
29f636c2eb Fix _REXBmr(). Add CPUID. Some C++ compiler fixes. Make x86_emit_failure() 
be void, and let x86_emit_failure0() be an int expression instead.
 2003-03-18 16:28:23 +00:00
gbeauche
8271c0503e Add CMOV and BSF/BSR instructions 2003-03-18 13:12:56 +00:00
gbeauche
e07bfdbc8b Handle absolute and RIP addressing modes in x86-64 2003-03-18 10:08:16 +00:00
gbeauche
ce3d90ff5e clobber "cc" for flags, not "flags". Thanks Milan for noticing it. 2003-03-17 22:37:55 +00:00
gbeauche
08e9f936eb Add some SSE/SSE2 instructions 2003-03-17 17:18:24 +00:00
gbeauche
c2566295af Implement a generic setzflg_l() for P4, thus permitting to re-enable 
translation of ADDX/SUBX/BCLR/BTST/BSET/BCHG instructions. i.e. make
it faster. ;-)
 2003-03-13 20:34:34 +00:00
gbeauche
0cfa3126b3 Workaround change in flags handling for BSF instruction on Pentium 4. 
i.e. currently disable translation of ADDX/SUBX/B<CHG,CLR,SET,TST> instructions
in that case. That is to say, better (much?) slower than inaccurate. :-(
 2003-03-13 15:57:01 +00:00