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dbc467e316
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159 Commits

Author SHA1 Message Date
gbeauche
dbc467e316 prefer lower indexes in register allocation, this avoids REX prefixes on 
x86_64 when %r8 - %r15 are used (very light speedup expected)
 2006-02-26 18:58:18 +00:00
gbeauche
91babf4bb5 fix FETOX & FTWOTOX translations for x86_64 2006-02-26 18:49:55 +00:00
gbeauche
294664b726 Fix SAHF_SETO_PROFITABLE code for x86-64 platforms. 
This was only an experiment. Improvement was marginal: only +3% on AMD64
(an Athlon 64 3200+). However, it may be interesting to test it on EM64T
(e.g. newer P4s) since an older P3/800, hence in 32-bit mode, got a +15%
improvement in Speedometer 4 benchmarks.

Rationale: lahf/seto sequences avoid load/stores to the stack (push/pop)
and it was thus hoped to be faster.

Anyhow, SAHF_SETO_PROFITABLE can only be enabled manually at this time.
Edit your generated Makefile for testing, but first make sure your CPU
supports lahf in 64-bit mode (lahf_lm flag in /proc/cpuinfo).
 2006-02-06 23:06:54 +00:00
gbeauche
3b94dfb1a9 Cosmetics, fix %rh cases in !X86_FLAT_REGISTERS mode, lahf/sahf are now 
valid instructions in long mode (recent enough CPU revisions: lahf_lm).
 2006-02-06 22:57:18 +00:00
gbeauche
9ccf62f7b0 Manually emit LAHF instructions so that 64-bit assemblers can grok it 2006-02-06 22:55:44 +00:00
gbeauche
e534b07a70 more precise callee-saved register set 2006-01-16 21:31:41 +00:00
gbeauche
12f103a83a JIT generated code is not guaranteed to be leaf, e.g. there could be a call 
to a generic instruction handler (untranslated code). This caused problems
on MacOS X for Intel where the unaligned stack conditions turned out to be
more visible. Performance loss is really neglectable and this is the right
fix now anyway.
 2006-01-16 21:31:08 +00:00
gbeauche
1b99c9501f fix stack alignment (theoritically but it was OK in practise) in generated 
functions, move m68k_compile_execute() to compiler/ dir since it's JIT
generic and it now depends on USE_PUSH_POP (as it should)
 2006-01-15 22:42:51 +00:00
gbeauche
ba5ef9cd31 Stop abort()'ing when we fail to recognize the underlying processor, assume 
an obsolete i386 instead. Keep report on stderr though.
 2005-07-24 14:57:11 +00:00
gbeauche
ef5a50e2af recognize more P4 cores 2005-07-24 14:48:27 +00:00
gbeauche
12eb8b670f Avoid C99-isms in C code for old compilers (e.g. gcc "2.96" on MDK 8.1) 2005-06-22 08:51:04 +00:00
gbeauche
0f0b06b099 Much improved responsiveness on NetBSD systems. 
On those systems, it's really hard to get high resolution timings and the
system oftens fails to honour a timeout in less than 20 ms. The idea here
is to have an average m68k instruction count (countdown quantum) that
triggers real interrupt checks. The quantum is calibrated every 10 ticks
and has a 1000 Hz resolution on average.
 2005-06-11 06:43:24 +00:00
gbeauche
c0cc43a87b Really make translation through constant jumps functional. This can be 
disabled with the new prefs item "jitinline". Some rapid Speedometer 4
benchmarks showed only a 4% improvement.
 2005-06-06 19:22:56 +00:00
gbeauche
83b228cf30 Add support for hardware locks on x86_64 too 2005-06-06 18:49:51 +00:00
gbeauche
6c65ae370e Fix build with NO_INLINE_MEMORY_ACCESS set 2005-06-05 07:32:23 +00:00
gbeauche
08c4acd21f Enable FLIGHT_RECORDER for generated code but don't record registers in 
that case (yet).
 2005-06-04 16:47:14 +00:00
gbeauche
d91e8b2a8f fix "banks" addressing mode for 64-bit platforms 2005-05-13 11:05:56 +00:00
gbeauche
380a9ed970 ensure allocated code fits under 32-bit boundaries 2005-04-24 23:02:48 +00:00
gbeauche
165b32da39 Fix build with gcc4 on x86-64: ignore errors when casting pointers to int 
from regs & fpu members + code cache. This is possible because data is
allocated in 32-bit space and we force allocation of translation cache to
those bounds too.
 2005-04-24 23:00:08 +00:00
gbeauche
57169c7923 Recognize lahf_lm from Dual Core Opterons. This enables use of LAHF/SETO 
instructions in long mode (64-bit). However, there seems to be another bug
in the JIT preventing it from being fully supported. m68k.h & codegen_x86.h
are easily fixed bug another patch is still needed.
 2005-04-21 09:08:57 +00:00
gbeauche
5c001ba645 Allocate executable space to detect cpu features (cpuid). aka don't crash 
on non-executable .data sections on x86-64 with NX support enabled.
 2005-03-22 16:12:18 +00:00
gbeauche
608c1f65bd close opened files and make sure to flush stdout on exit, this used to 
cause weird results on windows otherwise
 2005-03-17 00:21:36 +00:00
gbeauche
30632aed4f Happy New Year! 2005-01-30 21:42:16 +00:00
gbeauche
a6bf2d0928 add some code to gather stats on m68k registers used in translated blocks 2004-11-20 23:35:16 +00:00
gbeauche
6774a0821d fix tester for BSF flags handling 2004-11-11 07:07:55 +00:00
gbeauche
20f5f531ca fix inline dispatcher to really generate a cmove on x86-64 (silly bug!) 2004-11-08 23:24:54 +00:00
gbeauche
0c255e1fbd Merge BSF simulation on P4 from Amithlon. Use 33-bit memory addressing model. 2004-11-08 21:10:46 +00:00
gbeauche
0ba075050c Enable RIP-relative addressing, optimize REX conditions processing in 
! X86_FLAT_REGISTERS mode, fix __REX_mem encodings (e.g. POPLm)
 2004-11-08 20:48:19 +00:00
gbeauche
c21650b7a8 fix protection changes on translation cache + cosmetic fixlet 2004-11-02 23:52:00 +00:00
gbeauche
3fcceb052c fix JIT FPU for x86_64 2004-11-02 23:28:19 +00:00
gbeauche
129f80faf6 preserve r11 as the register used to resolve pointers to functions 2004-11-01 18:40:30 +00:00
gbeauche
b3bd00f159 - affine need_to_preserve[] to get close to linux/x86_64 ABI 
- optimize NOP fillers on x86-64 (based on GNU as implementation)
 2004-11-01 17:12:55 +00:00
gbeauche
e58fbc745b revive and fix almost two-year old port to x86_64 2004-11-01 16:01:51 +00:00
gbeauche
730364ac1e - optimize absolute addresses into RIP relative, if possible 
- fix MOVQir as the operand is 64-bit
- fix IMULWrr, IMULLrr, IMULQrr, MOVSBWrr, MOVZBWrr
 2004-11-01 15:37:40 +00:00
gbeauche
c12d2fa0ea add dumb but handy brute-force runtime assembler verifier, someone will 
probably want to rewrite it to use BFD/opcodes internals for checks
 2004-11-01 15:30:46 +00:00
gbeauche
33be2e8ace Reorder SPL, BPL, SIL, DIL IDs so that 8-bit register allocation is simpler 
Fix MOVZBL and MOVSBL encodings with those extended 8-bit registers
 2004-10-31 16:02:04 +00:00
gbeauche
87b79bdc20 fix SIB encoding with base=r13 
fix PUSH/POP with x86_64 extended registers
fix CALL/JMP REX prefixes
 2004-10-24 22:22:49 +00:00
cebix
9e7932abf0 Happy New Year! :) 2004-01-12 15:29:31 +00:00
gbeauche
45df157a5e Implement lazy icache range invalidation. Disable for now until it shows 
a real benefit over only 2%
 2003-11-21 14:20:01 +00:00
gbeauche
3630404307 fix fp_do_sgn1() for "double"-targets 2003-11-21 13:27:47 +00:00
gbeauche
309c2f0bd5 Add "jitblacklist" prefs item so that opcodes ranges could be excluded for 
translation. This should help debugging of (badly) translated code.

Usage: jitblacklist xxxx(-yyyy)?(;xxxx(-yyyy)?)*
where xxxx/yyyy are hexadecimal numbers
 2003-10-14 10:29:19 +00:00
gbeauche
b66f5972f9 Make sure a 32-bit B2/JIT works reasonnably well on AMD64 too. This implies 
to force RAMBaseHost < 0x80000000. This is empirically determined to work on
Linux/x86 and Linux/amd64.
 2003-10-03 18:18:15 +00:00
gbeauche
87e4d48b3e flags are live after a call to fflags_into_flags_internal() 2003-10-02 09:51:14 +00:00
gbeauche
c464b19f06 get a chance to see some illegal instruction variants if we ever come to 
encounter them.
 2003-10-02 09:48:10 +00:00
gbeauche
f3ad33ed58 Call correct PUSHF/POPF macro 2003-06-03 09:01:03 +00:00
gbeauche
04167990a6 workaround a compiler bug on SPARC (Milan) 2003-05-28 10:17:43 +00:00
gbeauche
ccdec0782b really make long double values (Milan) 2003-05-28 10:14:14 +00:00
gbeauche
3863961d26 - Fix "extended register" predicate to exclude X86_NOREG and X86_RIP 
- Really handle requested 32-bit absolute address in AMD64 target
- Fix REX prefixes in 16-bit ALU instructions
- Fix POPF, remove useless? POPFD and PUSHFD
 2003-05-19 17:15:17 +00:00
nigel
21c4e9da5b Building on GCC 2 causes errors: 
../uae_cpu/gencpu.c: In function `void gen_opcode(long unsigned int)':
../uae_cpu/gencpu.c:874: conversion from `unsigned int' to `enum wordsizes'
../uae_cpu/gencpu.c:875: conversion from `unsigned int' to `enum amodes'
due to mismatching of types in struct instr and types in function prototypes.
However, this only started happening recently and I don't know why :-(
 2003-04-01 05:26:07 +00:00
gbeauche
9ed554b3a9 Remove some dead code. Start implementation of optimized calls to interpretive 
fallbacks for untranslatable instruction handlers. Disabled for now since
call_m_01() is not correctly imeplemented yet.
 2003-03-21 19:12:44 +00:00