2021-11-02 05:06:40 +00:00
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use crate::error::Error;
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use crate::devices::{Address, Addressable};
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2021-11-03 03:58:03 +00:00
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use super::state::{Z80, Z80Type, Register};
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#[derive(Copy, Clone, Debug)]
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pub enum Size {
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Byte,
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Word,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum Condition {
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NotZero,
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Zero,
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NotCarry,
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Carry,
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ParityOdd,
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ParityEven,
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Positive,
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Negative,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum RegisterPair {
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BC,
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DE,
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HL,
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AF,
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SP,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum SpecialRegister {
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I,
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R,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum Target {
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DirectReg(Register),
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IndirectReg(RegisterPair),
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Immediate(u8),
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}
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#[derive(Copy, Clone, Debug)]
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pub enum LoadTarget {
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DirectRegByte(Register),
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DirectRegWord(RegisterPair),
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IndirectRegByte(RegisterPair),
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IndirectRegWord(RegisterPair),
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DirectAltRegByte(Register),
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DirectSpecialRegByte(SpecialRegister),
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IndirectByte(u16),
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IndirectWord(u16),
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ImmediateByte(u8),
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ImmediateWord(u16),
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}
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#[derive(Clone, Debug)]
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pub enum Instruction {
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ADCa(Target),
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ADChl(RegisterPair),
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ADDa(Target),
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ADDhl(RegisterPair),
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AND(Target),
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CP(Target),
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CPL,
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NEG,
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OR(Target),
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SBCa(Target),
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SBChl(RegisterPair),
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SUB(Target),
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XOR(Target),
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BIT(u8, Target),
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RES(u8, Target),
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RL(Target),
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RLC(Target),
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RR(Target),
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RRC(Target),
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SET(u8, Target),
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SLA(Target),
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SLL(Target),
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SRA(Target),
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SRL(Target),
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DEC8(Target),
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DEC16(RegisterPair),
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INC8(Target),
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INC16(RegisterPair),
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EXX,
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EXafaf,
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EXhlsp,
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EXhlde,
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LD(LoadTarget, LoadTarget),
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POP(RegisterPair),
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PUSH(RegisterPair),
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INx(u8),
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INic(Register),
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OUTx(u8),
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OUTic(Register),
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CALL(u16),
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CALLcc(Condition, u16),
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DJNZ(i8),
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JP(u16),
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JPIndirectHL,
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JPcc(Condition, u16),
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JR(i8),
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JRcc(Condition, i8),
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RET,
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RETI,
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RETN,
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RETcc(Condition),
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DI,
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EI,
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IM(u8),
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NOP,
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HALT,
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RST(u8),
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CCF,
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DAA,
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RLA,
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RLCA,
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RRA,
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RRCA,
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RRD,
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RLD,
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SCF,
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CPD,
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CPDR,
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CPI,
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CPIR,
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IND,
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INDR,
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INI,
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INIR,
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LDD,
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LDDR,
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LDI,
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LDIR,
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OTDR,
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OTIR,
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OUTD,
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OUTI,
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}
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pub struct Z80Decoder {
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pub start: u16,
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pub end: u16,
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pub instruction: Instruction,
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}
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impl Z80Decoder {
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pub fn new() -> Self {
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Self {
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start: 0,
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end: 0,
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instruction: Instruction::NOP,
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}
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}
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}
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impl Z80Decoder {
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pub fn decode_at(&mut self, memory: &mut dyn Addressable, start: u16) -> Result<(), Error> {
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self.start = start;
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self.end = start;
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self.instruction = self.decode_one(memory)?;
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Ok(())
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}
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pub fn decode_one(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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let ins = self.read_instruction_byte(memory)?;
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match get_ins_x(ins) {
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0 => {
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match get_ins_z(ins) {
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0 => {
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match get_ins_y(ins) {
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0 => Ok(Instruction::NOP),
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1 => Ok(Instruction::EXafaf),
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2 => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::DJNZ(offset))
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},
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3 => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::JR(offset))
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},
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y => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::JRcc(get_condition(y - 4), offset))
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},
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}
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},
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1 => {
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if get_ins_q(ins) == 0 {
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let data = self.read_instruction_word(memory)?;
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Ok(Instruction::LD(LoadTarget::DirectRegWord(get_register_pair(get_ins_p(ins))), LoadTarget::ImmediateWord(data)))
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} else {
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Ok(Instruction::ADDhl(get_register_pair(get_ins_p(ins))))
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}
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},
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2 => {
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if (ins & 0x20) == 0 {
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let target = match (ins & 0x10) != 0 {
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false => LoadTarget::IndirectRegByte(RegisterPair::BC),
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true => LoadTarget::IndirectRegByte(RegisterPair::DE),
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};
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match (ins & 0x08) != 0 {
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false => Ok(Instruction::LD(target, LoadTarget::DirectRegByte(Register::A))),
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true => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), target)),
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}
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} else {
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let addr = self.read_instruction_word(memory)?;
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match (ins >> 3) & 0x03 {
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0 => Ok(Instruction::LD(LoadTarget::IndirectWord(addr), LoadTarget::DirectRegWord(RegisterPair::HL))),
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1 => Ok(Instruction::LD(LoadTarget::IndirectByte(addr), LoadTarget::DirectRegByte(Register::A))),
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2 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::HL), LoadTarget::IndirectWord(addr))),
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3 => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), LoadTarget::IndirectByte(addr))),
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_ => panic!("InternalError: impossible value"),
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}
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}
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},
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3 => {
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if get_ins_q(ins) == 0 {
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Ok(Instruction::INC16(get_register_pair(get_ins_p(ins))))
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} else {
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Ok(Instruction::DEC16(get_register_pair(get_ins_p(ins))))
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}
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},
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4 => {
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Ok(Instruction::INC8(get_register(get_ins_y(ins))))
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},
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5 => {
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Ok(Instruction::DEC8(get_register(get_ins_y(ins))))
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},
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6 => {
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let data = self.read_instruction_byte(memory)?;
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Ok(Instruction::LD(to_load_target(get_register(get_ins_y(ins))), LoadTarget::ImmediateByte(data)))
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},
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7 => {
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match get_ins_y(ins) {
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0 => Ok(Instruction::RLCA),
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1 => Ok(Instruction::RRCA),
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2 => Ok(Instruction::RLA),
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3 => Ok(Instruction::RRA),
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4 => Ok(Instruction::DAA),
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5 => Ok(Instruction::CPL),
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6 => Ok(Instruction::SCF),
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7 => Ok(Instruction::CCF),
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_ => panic!("InternalError: impossible value"),
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}
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},
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_ => panic!("InternalError: impossible value"),
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}
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},
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1 => {
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if ins == 0x76 {
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Ok(Instruction::HALT)
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} else {
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Ok(Instruction::LD(to_load_target(get_register(get_ins_y(ins))), to_load_target(get_register(get_ins_z(ins)))))
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}
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},
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2 => {
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Ok(get_alu_instruction(get_ins_y(ins), get_register(get_ins_z(ins))))
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},
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3 => {
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match get_ins_z(ins) {
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0 => {
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Ok(Instruction::RETcc(get_condition(get_ins_y(ins))))
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},
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1 => {
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if get_ins_q(ins) == 0 {
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Ok(Instruction::POP(get_register_pair_alt(get_ins_p(ins))))
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} else {
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match get_ins_p(ins) {
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0 => Ok(Instruction::RET),
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1 => Ok(Instruction::EXX),
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2 => Ok(Instruction::JPIndirectHL),
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3 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::SP), LoadTarget::DirectRegWord(RegisterPair::HL))),
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_ => panic!("InternalError: impossible value"),
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}
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}
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},
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2 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::JPcc(get_condition(get_ins_y(ins)), addr))
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},
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3 => {
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match get_ins_y(ins) {
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0 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::JP(addr))
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},
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1 => {
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self.decode_prefix_cb(memory)
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},
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2 => {
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let port = self.read_instruction_byte(memory)?;
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Ok(Instruction::OUTx(port))
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},
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3 => {
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let port = self.read_instruction_byte(memory)?;
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Ok(Instruction::INx(port))
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},
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4 => Ok(Instruction::EXhlsp),
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5 => Ok(Instruction::EXhlde),
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6 => Ok(Instruction::DI),
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7 => Ok(Instruction::EI),
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_ => panic!("InternalError: impossible value"),
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}
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},
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4 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::CALLcc(get_condition(get_ins_y(ins)), addr))
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}
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5 => {
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if get_ins_q(ins) == 0 {
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Ok(Instruction::PUSH(get_register_pair_alt(get_ins_p(ins))))
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} else {
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match get_ins_p(ins) {
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0 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::CALL(addr))
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},
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1 => self.decode_prefix_dd(memory),
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2 => self.decode_prefix_ed(memory),
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3 => self.decode_prefix_fd(memory),
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_ => panic!("Undecoded Instruction"),
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}
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}
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}
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6 => {
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let data = self.read_instruction_byte(memory)?;
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Ok(get_alu_instruction(get_ins_y(ins), Target::Immediate(data)))
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},
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7 => {
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Ok(Instruction::RST(get_ins_y(ins) * 8))
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},
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_ => panic!("InternalError: impossible value"),
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}
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},
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_ => panic!("Undecoded Instruction"),
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}
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}
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pub fn decode_prefix_cb(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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let ins = self.read_instruction_byte(memory)?;
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match get_ins_x(ins) {
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0 => Ok(get_rot_instruction(get_ins_y(ins), get_register(get_ins_z(ins)))),
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1 => Ok(Instruction::BIT(get_ins_y(ins), get_register(get_ins_z(ins)))),
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2 => Ok(Instruction::RES(get_ins_y(ins), get_register(get_ins_z(ins)))),
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3 => Ok(Instruction::SET(get_ins_y(ins), get_register(get_ins_z(ins)))),
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn decode_prefix_dd(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
|
|
|
|
panic!("DD instructions unimplemented")
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn decode_prefix_ed(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
|
|
|
|
let ins = self.read_instruction_byte(memory)?;
|
|
|
|
|
|
|
|
match get_ins_x(ins) {
|
|
|
|
0 => Ok(Instruction::NOP),
|
|
|
|
1 => {
|
|
|
|
match get_ins_z(ins) {
|
|
|
|
0 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
let target = get_register(get_ins_y(ins));
|
|
|
|
if let Target::DirectReg(reg) = target {
|
|
|
|
Ok(Instruction::INic(reg))
|
2021-11-02 05:06:40 +00:00
|
|
|
} else {
|
2021-11-03 03:58:03 +00:00
|
|
|
//Ok(Instruction::INic())
|
|
|
|
panic!("Unimplemented");
|
2021-11-02 05:06:40 +00:00
|
|
|
}
|
|
|
|
},
|
|
|
|
1 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
let target = get_register(get_ins_y(ins));
|
|
|
|
if let Target::DirectReg(reg) = target {
|
|
|
|
Ok(Instruction::OUTic(reg))
|
|
|
|
} else {
|
|
|
|
//Ok(Instruction::OUTic())
|
|
|
|
panic!("Unimplemented");
|
|
|
|
}
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
2 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
if get_ins_q(ins) == 0 {
|
|
|
|
Ok(Instruction::SBChl(get_register_pair(get_ins_p(ins))))
|
|
|
|
} else {
|
|
|
|
Ok(Instruction::ADChl(get_register_pair(get_ins_p(ins))))
|
|
|
|
}
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
3 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
let addr = self.read_instruction_word(memory)?;
|
|
|
|
if get_ins_q(ins) == 0 {
|
|
|
|
Ok(Instruction::LD(LoadTarget::IndirectWord(addr), LoadTarget::DirectRegWord(get_register_pair(get_ins_p(ins)))))
|
|
|
|
} else {
|
|
|
|
Ok(Instruction::LD(LoadTarget::DirectRegWord(get_register_pair(get_ins_p(ins))), LoadTarget::IndirectWord(addr)))
|
|
|
|
}
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
4 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
Ok(Instruction::NEG)
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
5 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
if get_ins_y(ins) == 1 {
|
|
|
|
Ok(Instruction::RETI)
|
|
|
|
} else {
|
|
|
|
Ok(Instruction::RETN)
|
|
|
|
}
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
6 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
Ok(Instruction::IM(get_ins_y(ins)))
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
7 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
match get_ins_y(ins) {
|
|
|
|
0 => Ok(Instruction::LD(LoadTarget::DirectSpecialRegByte(SpecialRegister::I), LoadTarget::DirectRegByte(Register::A))),
|
|
|
|
1 => Ok(Instruction::LD(LoadTarget::DirectSpecialRegByte(SpecialRegister::R), LoadTarget::DirectRegByte(Register::A))),
|
|
|
|
2 => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), LoadTarget::DirectSpecialRegByte(SpecialRegister::I))),
|
|
|
|
3 => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), LoadTarget::DirectSpecialRegByte(SpecialRegister::R))),
|
|
|
|
4 => Ok(Instruction::RRD),
|
|
|
|
5 => Ok(Instruction::RLD),
|
|
|
|
_ => Ok(Instruction::NOP),
|
|
|
|
}
|
2021-11-02 05:06:40 +00:00
|
|
|
},
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
},
|
|
|
|
2 => {
|
2021-11-03 03:58:03 +00:00
|
|
|
match ins {
|
|
|
|
0xA0 => Ok(Instruction::LDI),
|
|
|
|
0xA1 => Ok(Instruction::CPI),
|
|
|
|
0xA2 => Ok(Instruction::INI),
|
|
|
|
0xA3 => Ok(Instruction::OUTI),
|
|
|
|
0xA8 => Ok(Instruction::LDD),
|
|
|
|
0xA9 => Ok(Instruction::CPD),
|
|
|
|
0xAA => Ok(Instruction::IND),
|
|
|
|
0xAB => Ok(Instruction::OUTD),
|
|
|
|
0xB0 => Ok(Instruction::LDIR),
|
|
|
|
0xB1 => Ok(Instruction::CPIR),
|
|
|
|
0xB2 => Ok(Instruction::INIR),
|
|
|
|
0xB3 => Ok(Instruction::OTIR),
|
|
|
|
0xB8 => Ok(Instruction::LDDR),
|
|
|
|
0xB9 => Ok(Instruction::CPDR),
|
|
|
|
0xBA => Ok(Instruction::INDR),
|
|
|
|
0xBB => Ok(Instruction::OTDR),
|
2021-11-02 05:06:40 +00:00
|
|
|
_ => Ok(Instruction::NOP),
|
|
|
|
}
|
|
|
|
},
|
|
|
|
3 => Ok(Instruction::NOP),
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn decode_prefix_fd(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
|
|
|
|
panic!("FD instructions unimplemented")
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
fn read_instruction_byte(&mut self, device: &mut dyn Addressable) -> Result<u8, Error> {
|
|
|
|
let byte = device.read_u8(self.end as Address)?;
|
|
|
|
self.end += 1;
|
|
|
|
Ok(byte)
|
|
|
|
}
|
|
|
|
|
|
|
|
fn read_instruction_word(&mut self, device: &mut dyn Addressable) -> Result<u16, Error> {
|
2021-11-03 03:58:03 +00:00
|
|
|
let word = device.read_leu16(self.end as Address)?;
|
2021-11-02 05:06:40 +00:00
|
|
|
self.end += 2;
|
|
|
|
Ok(word)
|
|
|
|
}
|
|
|
|
|
2021-11-05 04:30:33 +00:00
|
|
|
pub fn format_instruction_bytes(&mut self, memory: &mut dyn Addressable) -> String {
|
|
|
|
let ins_data: String =
|
2021-11-03 03:58:03 +00:00
|
|
|
(0..(self.end - self.start)).map(|offset|
|
2021-11-05 04:30:33 +00:00
|
|
|
format!("{:02x} ", memory.read_u8((self.start + offset) as Address).unwrap())
|
2021-11-02 05:06:40 +00:00
|
|
|
).collect();
|
2021-11-05 04:30:33 +00:00
|
|
|
ins_data
|
|
|
|
}
|
|
|
|
|
|
|
|
pub fn dump_decoded(&mut self, memory: &mut dyn Addressable) {
|
|
|
|
let ins_data = self.format_instruction_bytes(memory);
|
|
|
|
println!("{:#06x}: {}\n\t{:?}\n", self.start, ins_data, self.instruction);
|
2021-11-02 05:06:40 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_alu_instruction(alu: u8, target: Target) -> Instruction {
|
|
|
|
match alu {
|
|
|
|
0 => Instruction::ADDa(target),
|
|
|
|
1 => Instruction::ADCa(target),
|
|
|
|
2 => Instruction::SUB(target),
|
|
|
|
3 => Instruction::SBCa(target),
|
|
|
|
4 => Instruction::AND(target),
|
|
|
|
5 => Instruction::XOR(target),
|
|
|
|
6 => Instruction::OR(target),
|
|
|
|
7 => Instruction::CP(target),
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_rot_instruction(rot: u8, target: Target) -> Instruction {
|
|
|
|
match rot {
|
|
|
|
0 => Instruction::RLC(target),
|
|
|
|
1 => Instruction::RRC(target),
|
|
|
|
2 => Instruction::RL(target),
|
|
|
|
3 => Instruction::RR(target),
|
|
|
|
4 => Instruction::SLA(target),
|
|
|
|
5 => Instruction::SRA(target),
|
|
|
|
6 => Instruction::SLL(target),
|
|
|
|
7 => Instruction::SRL(target),
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_register(reg: u8) -> Target {
|
|
|
|
match reg {
|
2021-11-03 03:58:03 +00:00
|
|
|
0 => Target::DirectReg(Register::B),
|
|
|
|
1 => Target::DirectReg(Register::C),
|
|
|
|
2 => Target::DirectReg(Register::D),
|
|
|
|
3 => Target::DirectReg(Register::E),
|
|
|
|
4 => Target::DirectReg(Register::H),
|
|
|
|
5 => Target::DirectReg(Register::L),
|
|
|
|
6 => Target::IndirectReg(RegisterPair::HL),
|
|
|
|
7 => Target::DirectReg(Register::A),
|
2021-11-02 05:06:40 +00:00
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn to_load_target(target: Target) -> LoadTarget {
|
|
|
|
match target {
|
2021-11-03 03:58:03 +00:00
|
|
|
Target::DirectReg(reg) => LoadTarget::DirectRegByte(reg),
|
|
|
|
Target::IndirectReg(reg) => LoadTarget::IndirectRegByte(reg),
|
|
|
|
Target::Immediate(data) => LoadTarget::ImmediateByte(data),
|
2021-11-02 05:06:40 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_register_pair(reg: u8) -> RegisterPair {
|
|
|
|
match reg {
|
|
|
|
0 => RegisterPair::BC,
|
|
|
|
1 => RegisterPair::DE,
|
|
|
|
2 => RegisterPair::HL,
|
|
|
|
3 => RegisterPair::SP,
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_register_pair_alt(reg: u8) -> RegisterPair {
|
|
|
|
match reg {
|
|
|
|
0 => RegisterPair::BC,
|
|
|
|
1 => RegisterPair::DE,
|
|
|
|
2 => RegisterPair::HL,
|
|
|
|
3 => RegisterPair::AF,
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_condition(cond: u8) -> Condition {
|
|
|
|
match cond {
|
|
|
|
0 => Condition::NotZero,
|
|
|
|
1 => Condition::Zero,
|
|
|
|
2 => Condition::NotCarry,
|
|
|
|
3 => Condition::Carry,
|
|
|
|
4 => Condition::ParityOdd,
|
|
|
|
5 => Condition::ParityEven,
|
|
|
|
6 => Condition::Positive,
|
|
|
|
7 => Condition::Negative,
|
|
|
|
_ => panic!("InternalError: impossible value"),
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_ins_x(ins: u8) -> u8 {
|
|
|
|
(ins >> 6) & 0x03
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_ins_y(ins: u8) -> u8 {
|
|
|
|
(ins >> 3) & 0x07
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_ins_z(ins: u8) -> u8 {
|
|
|
|
ins & 0x07
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_ins_p(ins: u8) -> u8 {
|
|
|
|
(ins >> 4) & 0x03
|
|
|
|
}
|
|
|
|
|
|
|
|
fn get_ins_q(ins: u8) -> u8 {
|
|
|
|
(ins >> 3) & 0x01
|
|
|
|
}
|
|
|
|
|