From 447b3727ed5ea95c743c81bab40e254a2c41783d Mon Sep 17 00:00:00 2001
From: transistor <trans@jabberwocky.ca>
Date: Fri, 22 Oct 2021 13:02:48 -0700
Subject: [PATCH] Fixed bug in DIVW instruction

---
 src/cpus/m68k/decode.rs |  2 +-
 src/cpus/m68k/tests.rs  | 10 ++++++++++
 2 files changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/cpus/m68k/decode.rs b/src/cpus/m68k/decode.rs
index ba341a0..993b5f9 100644
--- a/src/cpus/m68k/decode.rs
+++ b/src/cpus/m68k/decode.rs
@@ -399,7 +399,7 @@ impl M68kDecoder {
 
                 if size.is_none() {
                     let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
-                    let effective_addr = self.decode_lower_effective_address(memory, ins, size)?;
+                    let effective_addr = self.decode_lower_effective_address(memory, ins, Some(Size::Word))?;
                     Ok(Instruction::DIVW(effective_addr, get_high_reg(ins), sign))
                 } else if (ins & 0x1F0) == 0x100 {
                     let regx = get_high_reg(ins);
diff --git a/src/cpus/m68k/tests.rs b/src/cpus/m68k/tests.rs
index 9e14707..cd73ac7 100644
--- a/src/cpus/m68k/tests.rs
+++ b/src/cpus/m68k/tests.rs
@@ -373,6 +373,16 @@ mod decode_tests {
         assert_eq!(cpu.decoder.instruction, Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed));
     }
 
+    #[test]
+    fn instruction_divs() {
+        let (mut cpu, system) = init_decode_test(M68kType::MC68010);
+
+        system.get_bus().write_beu16(INIT_ADDR,     0x81FC).unwrap();
+        system.get_bus().write_beu16(INIT_ADDR + 2, 0x0003).unwrap();
+        cpu.decode_next(&system).unwrap();
+        assert_eq!(cpu.decoder.instruction, Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed));
+    }
+
     #[test]
     fn instruction_mulsl() {
         let (mut cpu, system) = init_decode_test(M68kType::MC68030);