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Fixed bug in DIVW instruction
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f9e018742b
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@ -399,7 +399,7 @@ impl M68kDecoder {
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if size.is_none() {
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let sign = if (ins & 0x0100) == 0 { Sign::Unsigned } else { Sign::Signed };
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let effective_addr = self.decode_lower_effective_address(memory, ins, size)?;
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let effective_addr = self.decode_lower_effective_address(memory, ins, Some(Size::Word))?;
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Ok(Instruction::DIVW(effective_addr, get_high_reg(ins), sign))
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} else if (ins & 0x1F0) == 0x100 {
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let regx = get_high_reg(ins);
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@ -373,6 +373,16 @@ mod decode_tests {
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assert_eq!(cpu.decoder.instruction, Instruction::MULW(Target::Immediate(0x276), 0, Sign::Signed));
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}
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#[test]
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fn instruction_divs() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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system.get_bus().write_beu16(INIT_ADDR, 0x81FC).unwrap();
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system.get_bus().write_beu16(INIT_ADDR + 2, 0x0003).unwrap();
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cpu.decode_next(&system).unwrap();
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assert_eq!(cpu.decoder.instruction, Instruction::DIVW(Target::Immediate(3), 0, Sign::Signed));
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}
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#[test]
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fn instruction_mulsl() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68030);
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