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https://github.com/transistorfet/moa.git
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Fixed warnings
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parent
e3819fe549
commit
5095aee531
@ -173,7 +173,7 @@ mod decode_tests {
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// Err(err) => { println!("{}", err.msg); errors += 1 },
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//}
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if let Err(err) = run_timing_test(case) {
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if let Err(_) = run_timing_test(case) {
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errors += 1;
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}
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}
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@ -189,7 +189,7 @@ mod decode_tests {
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#[test]
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fn target_direct_d() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let (mut cpu, _) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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@ -199,7 +199,7 @@ mod decode_tests {
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#[test]
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fn target_direct_a() {
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let (mut cpu, system) = init_decode_test(M68kType::MC68010);
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let (mut cpu, _) = init_decode_test(M68kType::MC68010);
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let size = Size::Word;
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@ -1,21 +1,7 @@
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use super::state::M68kType;
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use super::instructions::{
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Register,
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Size,
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Sign,
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Direction,
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ShiftDirection,
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XRegister,
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BaseRegister,
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IndexRegister,
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RegOrImmediate,
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ControlRegister,
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Condition,
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Target,
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Instruction,
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};
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use super::instructions::{Size, Sign, Direction, Target, Instruction};
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#[derive(Clone, Debug, PartialEq)]
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@ -147,14 +133,14 @@ impl M68kInstructionTiming {
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Target::IndirectAReg(_) => self.add_access(size),
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Target::IndirectARegInc(_) => self.add_access(size),
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Target::IndirectARegDec(_) => self.add_access(size).add_internal(2),
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Target::IndirectRegOffset(base_reg, index_reg, offset) => {
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Target::IndirectRegOffset(_, index_reg, _) => {
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match index_reg {
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None => self.add_access(size).add_internal(4),
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Some(_) => self.add_access(size).add_internal(6),
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}
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},
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Target::IndirectMemoryPreindexed(base_reg, index_reg, base_disp, outer_disp) |
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Target::IndirectMemoryPostindexed(base_reg, index_reg, base_disp, outer_disp) => {
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Target::IndirectMemoryPreindexed(_, index_reg, _, _) |
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Target::IndirectMemoryPostindexed(_, index_reg, _, _) => {
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// TODO this is very wrong, but the 68020 timings are complicated
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match index_reg {
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None => self.add_access(size).add_internal(4),
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@ -205,21 +191,21 @@ impl M68kInstructionTiming {
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pub fn add_instruction_68000(&mut self, instruction: &Instruction) -> &mut Self {
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match instruction {
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Instruction::ABCD(src, dest) => self.add_reg_v_mem(dest, 6, 18),
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Instruction::ABCD(_, dest) => self.add_reg_v_mem(dest, 6, 18),
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Instruction::ADD(src @ Target::Immediate(x), dest, size) if *x <= 8 => self.add_immediate_set(*size, dest, (4, 8), (8, 12)).add_target(*size, dest),// ADDQ
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Instruction::ADD(src @ Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest), // ADDI
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Instruction::ADD(Target::Immediate(x), dest, size) if *x <= 8 => self.add_immediate_set(*size, dest, (4, 8), (8, 12)).add_target(*size, dest),// ADDQ
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Instruction::ADD(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest), // ADDI
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Instruction::ADD(src, dest, size) => self.add_standard_set(*size, dest, (8, 6), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::ADDA(target, reg, size) => self.add_word_v_long(*size, 8, 6).add_target(*size, target),
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Instruction::ADDX(src, dest, size) => self.add_reg_mem_set(*size, dest, (4, 8), (18, 30)),
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Instruction::ADDA(target, _, size) => self.add_word_v_long(*size, 8, 6).add_target(*size, target),
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Instruction::ADDX(_, dest, size) => self.add_reg_mem_set(*size, dest, (4, 8), (18, 30)),
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Instruction::AND(src @ Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 14), (12, 20)).add_target(*size, dest),
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Instruction::AND(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 14), (12, 20)).add_target(*size, dest),
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Instruction::AND(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::ANDtoCCR(_) => self.add_internal(20),
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Instruction::ANDtoSR(_) => self.add_internal(20),
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Instruction::ASd(count, target, size, dir) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::ASd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::Bcc(_, _) => self.add_internal(8).add_on_branch(2),
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Instruction::BRA(_) => self.add_internal(10),
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@ -242,10 +228,10 @@ impl M68kInstructionTiming {
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_ => self.add_reg_v_mem(target, 6, 4),
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}.add_target(*size, target),
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Instruction::CHK(target, reg, size) => self.add_internal(10),
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Instruction::CHK(_, _, _) => self.add_internal(10),
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Instruction::CLR(target, size) => self.add_reg_v_mem(target, 4, 8).add_word_v_long(*size, 0, 2).add_target(*size, target),
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Instruction::CMP(src @ Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 14), (8, 12)).add_target(*size, dest),
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Instruction::CMP(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 14), (8, 12)).add_target(*size, dest),
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Instruction::CMP(src, dest, size) => self.add_standard_set(*size, dest, (6, 6), (4, 6), (0, 0)).add_two_targets(*size, src, dest),
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Instruction::CMPA(target, _, size) => self.add_word_v_long(*size, 6, 6).add_target(*size, target),
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@ -255,7 +241,7 @@ impl M68kInstructionTiming {
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Sign::Signed => self.add_internal(158).add_target(Size::Long, src),
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},
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Instruction::EOR(src @ Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest),
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Instruction::EOR(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest),
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Instruction::EOR(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 8), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::EORtoCCR(_) => self.add_internal(20),
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Instruction::EORtoSR(_) => self.add_internal(20),
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@ -268,9 +254,9 @@ impl M68kInstructionTiming {
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Instruction::JMP(target) => self.add_indirect_set(target, 8, 10, 14, 10, 12),
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Instruction::JSR(target) => self.add_indirect_set(target, 16, 18, 22, 18, 20),
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Instruction::LEA(target, reg) => self.add_indirect_set(target, 4, 8, 12, 8, 12),
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Instruction::LEA(target, _) => self.add_indirect_set(target, 4, 8, 12, 8, 12),
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Instruction::LINK(_, _) => self.add_internal(16),
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Instruction::LSd(count, target, size, dir) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::LSd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::MOVE(src, dest, size) => self.add_internal(4).add_two_targets(*size, src, dest),
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Instruction::MOVEA(target, _, size) => self.add_internal(4).add_target(*size, target),
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@ -278,10 +264,10 @@ impl M68kInstructionTiming {
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Instruction::MOVEtoSR(target) => self.add_internal(12).add_target(Size::Word, target),
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Instruction::MOVEfromCCR(target) => self.add_internal(12).add_target(Size::Word, target),
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Instruction::MOVEtoCCR(target) => self.add_internal(12).add_target(Size::Word, target),
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Instruction::MOVEC(target, reg, dir) => self.add_reg_v_mem(target, 10, 12),
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Instruction::MOVEC(target, _, _) => self.add_reg_v_mem(target, 10, 12),
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Instruction::MOVEM(target, size, dir, mask) => self.add_movem(*size, target, *dir, mask.count_ones() as u8),
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Instruction::MOVEP(_, _, _, size, _) => self.add_word_v_long(*size, 16, 24),
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Instruction::MOVEQ(value, reg) => self.add_internal(4),
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Instruction::MOVEQ(_, _) => self.add_internal(4),
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Instruction::MOVEUSP(_, _) => self.add_internal(4),
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Instruction::MULW(src, _, _) => self.add_internal(70).add_target(Size::Word, src),
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@ -293,7 +279,7 @@ impl M68kInstructionTiming {
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Instruction::NOP => self.add_internal(4),
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Instruction::NOT(target, size) => self.add_reg_mem_set(*size, target, (4, 6), (8, 12)).add_target(*size, target),
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Instruction::OR(src @ Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest),
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Instruction::OR(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest),
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Instruction::OR(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::ORtoCCR(_) => self.add_internal(20),
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Instruction::ORtoSR(_) => self.add_internal(20),
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@ -302,26 +288,26 @@ impl M68kInstructionTiming {
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Instruction::RESET => self.add_internal(132),
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Instruction::ROd(count, target, size, dir) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::ROXd(count, target, size, dir) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::ROd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::ROXd(_, target, size, _) => self.add_word_v_long(*size, 6, 8).add_per_rep(2).add_target(*size, target),
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Instruction::RTE => self.add_internal(20),
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Instruction::RTR => self.add_internal(20),
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Instruction::RTS => self.add_internal(16),
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//Instruction::RTD(offset) => ,
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Instruction::SBCD(src, dest) => self.add_reg_v_mem(dest, 6, 18),
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Instruction::SBCD(_, dest) => self.add_reg_v_mem(dest, 6, 18),
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Instruction::Scc(_, target) => self.add_reg_v_mem(target, 4, 8).add_on_branch(2).add_target(Size::Byte, target),
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Instruction::STOP(_) => self.add_internal(4),
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Instruction::SUB(Target::Immediate(x), Target::DirectAReg(_), Size::Byte)
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| Instruction::SUB(Target::Immediate(x), Target::DirectAReg(_), Size::Word) if *x <= 8 => self.add_internal(8), // SUBQ with an address reg as dest
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Instruction::SUB(src @ Target::Immediate(x), dest, size) if *x <= 8 => self.add_immediate_set(*size, dest, (4, 8), (8, 12)).add_target(*size, dest), // SUBQ
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Instruction::SUB(src @ Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest), // SUBI
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Instruction::SUB(Target::Immediate(x), dest, size) if *x <= 8 => self.add_immediate_set(*size, dest, (4, 8), (8, 12)).add_target(*size, dest), // SUBQ
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Instruction::SUB(Target::Immediate(_), dest, size) => self.add_immediate_set(*size, dest, (8, 16), (12, 20)).add_target(*size, dest), // SUBI
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Instruction::SUB(src, dest, size) => self.add_standard_set(*size, dest, (0, 0), (4, 6), (8, 12)).add_two_targets(*size, src, dest),
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Instruction::SUBA(target, reg, size) => self.add_word_v_long(*size, 8, 6).add_target(*size, target),
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Instruction::SUBX(src, dest, size) => self.add_reg_mem_set(*size, dest, (4, 8), (18, 30)),
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Instruction::SUBA(target, _, size) => self.add_word_v_long(*size, 8, 6).add_target(*size, target),
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Instruction::SUBX(_, dest, size) => self.add_reg_mem_set(*size, dest, (4, 8), (18, 30)),
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Instruction::SWAP(_) => self.add_internal(4),
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