mirror of
https://github.com/transistorfet/moa.git
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Added start of Z80 decoder
This commit is contained in:
transistor
parent
58fc9ac827
commit
e0ef1d8fd9
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@ -1,3 +1,4 @@
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pub mod m68k;
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pub mod z80;
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522
src/cpus/z80/decode.rs
Normal file
522
src/cpus/z80/decode.rs
Normal file
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@ -0,0 +1,522 @@
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use crate::error::Error;
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use crate::devices::{Address, Addressable};
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use super::state::{Z80, Z80Type};
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#[derive(Copy, Clone, Debug)]
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pub enum Condition {
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NotZero,
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Zero,
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NotCarry,
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Carry,
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ParityOdd,
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ParityEven,
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Positive,
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Negative,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum Register {
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A,
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B,
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C,
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D,
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E,
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H,
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L,
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F,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum RegisterPair {
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BC,
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DE,
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HL,
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SP,
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AF,
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}
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#[derive(Copy, Clone, Debug)]
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pub enum Target {
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DirectRegByte(Register),
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IndirectRegByte(RegisterPair),
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ImmediateByte(u8),
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}
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#[derive(Copy, Clone, Debug)]
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pub enum LoadTarget {
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DirectRegByte(Register),
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DirectRegWord(RegisterPair),
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IndirectRegByte(RegisterPair),
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IndirectRegWord(RegisterPair),
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DirectAltRegByte(Register),
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IndirectByte(u16),
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IndirectWord(u16),
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ImmediateByte(u8),
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ImmediateWord(u16),
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}
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#[derive(Clone, Debug)]
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pub enum Instruction {
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ADDa(Target),
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ADCa(Target),
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ADDhl(RegisterPair),
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AND(Target),
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CP(Target),
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CALL(u16),
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CALLcc(Condition, u16),
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DEC8(Target),
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DEC16(RegisterPair),
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DJNZ(i8),
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DI,
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EI,
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EXX,
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EXafaf,
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EXhlsp,
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EXhlde,
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INx(u8),
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INic(Register),
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INC8(Target),
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INC16(RegisterPair),
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JP(u16),
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JPcc(Condition, u16),
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JPIndirectHL,
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JR(i8),
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JRcc(Condition, i8),
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LD(LoadTarget, LoadTarget),
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NOP,
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HALT,
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POP(RegisterPair),
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PUSH(RegisterPair),
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RET,
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RETcc(Condition),
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RST(u8),
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OR(Target),
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OUTx(u8),
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OUTic(Register),
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SUB(Target),
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SBCa(Target),
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XOR(Target),
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RLC(Target),
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RRC(Target),
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RL(Target),
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RR(Target),
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SLA(Target),
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SRA(Target),
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SLL(Target),
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SRL(Target),
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BIT(u8, Target),
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RES(u8, Target),
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SET(u8, Target),
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RLCA,
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RRCA,
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RLA,
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RRA,
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DAA,
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CPL,
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SCF,
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CCF,
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}
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pub struct Z80Decoder {
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pub start: u16,
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pub end: u16,
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pub instruction: Instruction,
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}
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impl Z80Decoder {
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pub fn new() -> Self {
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Self {
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start: 0,
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end: 0,
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instruction: Instruction::NOP,
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}
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}
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}
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impl Z80Decoder {
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pub fn decode_at(&mut self, memory: &mut dyn Addressable, start: u16) -> Result<(), Error> {
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self.start = start;
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self.end = start;
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self.instruction = self.decode_one(memory)?;
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Ok(())
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}
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pub fn decode_one(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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let ins = self.read_instruction_byte(memory)?;
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match get_ins_x(ins) {
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0 => {
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match get_ins_z(ins) {
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0 => {
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match get_ins_y(ins) {
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0 => Ok(Instruction::NOP),
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1 => Ok(Instruction::EXafaf),
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2 => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::DJNZ(offset))
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},
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3 => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::JR(offset))
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},
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y => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::JRcc(get_condition(y - 4), offset))
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},
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}
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},
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1 => {
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if get_ins_q(ins) == 0 {
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let data = self.read_instruction_word(memory)?;
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Ok(Instruction::LD(LoadTarget::DirectRegWord(get_register_pair(get_ins_p(ins))), LoadTarget::ImmediateWord(data)))
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} else {
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Ok(Instruction::ADDhl(get_register_pair(get_ins_p(ins))))
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}
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},
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2 => {
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if (ins & 0x20) == 0 {
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let target = match (ins & 0x10) != 0 {
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false => LoadTarget::IndirectRegByte(RegisterPair::BC),
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true => LoadTarget::IndirectRegByte(RegisterPair::DE),
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};
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match (ins & 0x08) != 0 {
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false => Ok(Instruction::LD(target, LoadTarget::DirectRegByte(Register::A))),
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true => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), target)),
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}
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} else {
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let addr = self.read_instruction_word(memory)?;
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match ((ins >> 3) & 0x03) {
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0 => Ok(Instruction::LD(LoadTarget::IndirectWord(addr), LoadTarget::DirectRegWord(RegisterPair::HL))),
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1 => Ok(Instruction::LD(LoadTarget::IndirectByte(addr), LoadTarget::DirectRegByte(Register::A))),
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2 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::HL), LoadTarget::IndirectWord(addr))),
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3 => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), LoadTarget::IndirectByte(addr))),
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_ => panic!("InternalError: impossible value"),
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}
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}
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},
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3 => {
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if get_ins_q(ins) == 0 {
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Ok(Instruction::INC16(get_register_pair(get_ins_p(ins))))
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} else {
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Ok(Instruction::DEC16(get_register_pair(get_ins_p(ins))))
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}
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},
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4 => {
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Ok(Instruction::INC8(get_register(get_ins_y(ins))))
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},
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5 => {
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Ok(Instruction::DEC8(get_register(get_ins_y(ins))))
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},
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6 => {
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let data = self.read_instruction_byte(memory)?;
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Ok(Instruction::LD(to_load_target(get_register(get_ins_y(ins))), LoadTarget::ImmediateByte(data)))
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},
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7 => {
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match get_ins_y(ins) {
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0 => Ok(Instruction::RLCA),
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1 => Ok(Instruction::RRCA),
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2 => Ok(Instruction::RLA),
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3 => Ok(Instruction::RRA),
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4 => Ok(Instruction::DAA),
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5 => Ok(Instruction::CPL),
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6 => Ok(Instruction::SCF),
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7 => Ok(Instruction::CCF),
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_ => panic!("InternalError: impossible value"),
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}
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},
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_ => panic!("InternalError: impossible value"),
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}
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},
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1 => {
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if ins == 0x76 {
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Ok(Instruction::HALT)
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} else {
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Ok(Instruction::LD(to_load_target(get_register(get_ins_y(ins))), to_load_target(get_register(get_ins_z(ins)))))
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}
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},
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2 => {
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Ok(get_alu_instruction(get_ins_y(ins), get_register(get_ins_z(ins))))
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},
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3 => {
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match get_ins_z(ins) {
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0 => {
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Ok(Instruction::RETcc(get_condition(get_ins_y(ins))))
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},
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1 => {
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if get_ins_q(ins) == 0 {
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Ok(Instruction::POP(get_register_pair_alt(get_ins_p(ins))))
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} else {
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match get_ins_p(ins) {
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0 => Ok(Instruction::RET),
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1 => Ok(Instruction::EXX),
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2 => Ok(Instruction::JPIndirectHL),
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3 => Ok(Instruction::LD(LoadTarget::DirectRegWord(RegisterPair::SP), LoadTarget::DirectRegWord(RegisterPair::HL))),
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_ => panic!("InternalError: impossible value"),
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}
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}
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},
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2 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::JPcc(get_condition(get_ins_y(ins)), addr))
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},
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3 => {
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match get_ins_y(ins) {
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0 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::JP(addr))
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},
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1 => {
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self.decode_prefix_cb(memory)
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},
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2 => {
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let port = self.read_instruction_byte(memory)?;
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Ok(Instruction::OUTx(port))
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},
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3 => {
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let port = self.read_instruction_byte(memory)?;
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Ok(Instruction::INx(port))
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},
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4 => Ok(Instruction::EXhlsp),
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5 => Ok(Instruction::EXhlde),
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6 => Ok(Instruction::DI),
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7 => Ok(Instruction::EI),
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_ => panic!("InternalError: impossible value"),
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}
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},
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4 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::CALLcc(get_condition(get_ins_y(ins)), addr))
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}
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5 => {
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if get_ins_q(ins) == 0 {
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Ok(Instruction::PUSH(get_register_pair_alt(get_ins_p(ins))))
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} else {
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match get_ins_p(ins) {
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0 => {
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let addr = self.read_instruction_word(memory)?;
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Ok(Instruction::CALL(addr))
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},
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1 => self.decode_prefix_dd(memory),
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2 => self.decode_prefix_ed(memory),
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3 => self.decode_prefix_fd(memory),
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_ => panic!("Undecoded Instruction"),
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}
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}
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}
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6 => {
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let data = self.read_instruction_byte(memory)?;
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Ok(get_alu_instruction(get_ins_y(ins), Target::ImmediateByte(data)))
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},
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7 => {
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Ok(Instruction::RST(get_ins_y(ins) * 8))
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},
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_ => panic!("InternalError: impossible value"),
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}
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},
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_ => panic!("Undecoded Instruction"),
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}
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}
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pub fn decode_prefix_cb(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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let ins = self.read_instruction_byte(memory)?;
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match get_ins_x(ins) {
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0 => Ok(get_rot_instruction(get_ins_y(ins), get_register(get_ins_z(ins)))),
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1 => Ok(Instruction::BIT(get_ins_y(ins), get_register(get_ins_z(ins)))),
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2 => Ok(Instruction::RES(get_ins_y(ins), get_register(get_ins_z(ins)))),
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3 => Ok(Instruction::SET(get_ins_y(ins), get_register(get_ins_z(ins)))),
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_ => panic!("InternalError: impossible value"),
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}
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}
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pub fn decode_prefix_dd(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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panic!("DD instructions unimplemented")
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}
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pub fn decode_prefix_ed(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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let ins = self.read_instruction_byte(memory)?;
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match get_ins_x(ins) {
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0 => Ok(Instruction::NOP),
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1 => {
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/*
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match get_ins_z(ins) {
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0 => {
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let y = get_ins_y(ins);
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if y == 6 {
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//Ok(Instruction::INic),
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panic!("");
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} else {
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//Ok(Instruction::INic(get_register(y))),
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}
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},
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1 => {
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},
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2 => {
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},
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3 => {
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},
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4 => {
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},
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5 => {
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},
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6 => {
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},
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7 => {
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},
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_ => panic!("InternalError: impossible value"),
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}
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*/
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panic!("random instructions are unimplemented");
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},
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2 => {
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match ins & 0xF0 {
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// TODO implement block
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//0xA0 => {
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//},
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//0xB0 => {
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//},
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_ => Ok(Instruction::NOP),
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}
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},
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3 => Ok(Instruction::NOP),
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_ => panic!("InternalError: impossible value"),
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}
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}
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pub fn decode_prefix_fd(&mut self, memory: &mut dyn Addressable) -> Result<Instruction, Error> {
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panic!("FD instructions unimplemented")
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}
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fn read_instruction_byte(&mut self, device: &mut dyn Addressable) -> Result<u8, Error> {
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let byte = device.read_u8(self.end as Address)?;
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self.end += 1;
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Ok(byte)
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}
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fn read_instruction_word(&mut self, device: &mut dyn Addressable) -> Result<u16, Error> {
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let word = device.read_beu16(self.end as Address)?;
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self.end += 2;
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Ok(word)
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}
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pub fn dump_decoded(&mut self, memory: &mut dyn Addressable) {
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let ins_data: Result<String, Error> =
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(0..((self.end - self.start) / 2)).map(|offset|
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Ok(format!("{:02x} ", memory.read_u8((self.start + offset) as Address).unwrap()))
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).collect();
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println!("{:#06x}: {}\n\t{:?}\n", self.start, ins_data.unwrap(), self.instruction);
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}
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}
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fn get_alu_instruction(alu: u8, target: Target) -> Instruction {
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match alu {
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0 => Instruction::ADDa(target),
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1 => Instruction::ADCa(target),
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2 => Instruction::SUB(target),
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3 => Instruction::SBCa(target),
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4 => Instruction::AND(target),
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5 => Instruction::XOR(target),
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6 => Instruction::OR(target),
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7 => Instruction::CP(target),
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_ => panic!("InternalError: impossible value"),
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}
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}
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fn get_rot_instruction(rot: u8, target: Target) -> Instruction {
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match rot {
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0 => Instruction::RLC(target),
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1 => Instruction::RRC(target),
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2 => Instruction::RL(target),
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3 => Instruction::RR(target),
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4 => Instruction::SLA(target),
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5 => Instruction::SRA(target),
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6 => Instruction::SLL(target),
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7 => Instruction::SRL(target),
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_ => panic!("InternalError: impossible value"),
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}
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}
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fn get_register(reg: u8) -> Target {
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match reg {
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0 => Target::DirectRegByte(Register::B),
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1 => Target::DirectRegByte(Register::C),
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2 => Target::DirectRegByte(Register::D),
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3 => Target::DirectRegByte(Register::E),
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4 => Target::DirectRegByte(Register::H),
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5 => Target::DirectRegByte(Register::L),
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6 => Target::IndirectRegByte(RegisterPair::HL),
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7 => Target::DirectRegByte(Register::A),
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_ => panic!("InternalError: impossible value"),
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}
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}
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fn to_load_target(target: Target) -> LoadTarget {
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match target {
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Target::DirectRegByte(reg) => LoadTarget::DirectRegByte(reg),
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Target::IndirectRegByte(reg) => LoadTarget::IndirectRegByte(reg),
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Target::ImmediateByte(data) => LoadTarget::ImmediateByte(data),
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}
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}
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fn get_register_pair(reg: u8) -> RegisterPair {
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match reg {
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0 => RegisterPair::BC,
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1 => RegisterPair::DE,
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2 => RegisterPair::HL,
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3 => RegisterPair::SP,
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_ => panic!("InternalError: impossible value"),
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}
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}
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fn get_register_pair_alt(reg: u8) -> RegisterPair {
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match reg {
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0 => RegisterPair::BC,
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1 => RegisterPair::DE,
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2 => RegisterPair::HL,
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3 => RegisterPair::AF,
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_ => panic!("InternalError: impossible value"),
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}
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}
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fn get_condition(cond: u8) -> Condition {
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match cond {
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0 => Condition::NotZero,
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1 => Condition::Zero,
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2 => Condition::NotCarry,
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3 => Condition::Carry,
|
||||
4 => Condition::ParityOdd,
|
||||
5 => Condition::ParityEven,
|
||||
6 => Condition::Positive,
|
||||
7 => Condition::Negative,
|
||||
_ => panic!("InternalError: impossible value"),
|
||||
}
|
||||
}
|
||||
|
||||
fn get_ins_x(ins: u8) -> u8 {
|
||||
(ins >> 6) & 0x03
|
||||
}
|
||||
|
||||
fn get_ins_y(ins: u8) -> u8 {
|
||||
(ins >> 3) & 0x07
|
||||
}
|
||||
|
||||
fn get_ins_z(ins: u8) -> u8 {
|
||||
ins & 0x07
|
||||
}
|
||||
|
||||
fn get_ins_p(ins: u8) -> u8 {
|
||||
(ins >> 4) & 0x03
|
||||
}
|
||||
|
||||
fn get_ins_q(ins: u8) -> u8 {
|
||||
(ins >> 3) & 0x01
|
||||
}
|
||||
|
||||
97
src/cpus/z80/execute.rs
Normal file
97
src/cpus/z80/execute.rs
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
|
||||
use crate::system::System;
|
||||
use crate::error::{ErrorType, Error};
|
||||
use crate::devices::{ClockElapsed, Address, Steppable, Interruptable, Addressable, Debuggable, Transmutable};
|
||||
|
||||
use super::decode::Z80Decoder;
|
||||
use super::state::{Z80, Z80State, Status};
|
||||
|
||||
impl Steppable for Z80 {
|
||||
fn step(&mut self, system: &System) -> Result<ClockElapsed, Error> {
|
||||
self.step_internal(system)?;
|
||||
Ok((1_000_000_000 / self.frequency as u64) * 4)
|
||||
}
|
||||
|
||||
fn on_error(&mut self, system: &System) {
|
||||
//self.dump_state(system);
|
||||
}
|
||||
}
|
||||
|
||||
impl Interruptable for Z80 { }
|
||||
|
||||
impl Transmutable for Z80 {
|
||||
fn as_steppable(&mut self) -> Option<&mut dyn Steppable> {
|
||||
Some(self)
|
||||
}
|
||||
|
||||
fn as_interruptable(&mut self) -> Option<&mut dyn Interruptable> {
|
||||
Some(self)
|
||||
}
|
||||
|
||||
//fn as_debuggable(&mut self) -> Option<&mut dyn Debuggable> {
|
||||
// Some(self)
|
||||
//}
|
||||
}
|
||||
|
||||
|
||||
|
||||
impl Z80 {
|
||||
pub fn step_internal(&mut self, system: &System) -> Result<(), Error> {
|
||||
match self.state.status {
|
||||
Status::Init => self.init(system),
|
||||
Status::Halted => Err(Error::new("CPU stopped")),
|
||||
Status::Running => {
|
||||
match self.cycle_one(system) {
|
||||
Ok(()) => Ok(()),
|
||||
//Err(Error { err: ErrorType::Processor, native, .. }) => {
|
||||
Err(Error { err: ErrorType::Processor, native, .. }) => {
|
||||
//self.exception(system, native as u8, false)?;
|
||||
Ok(())
|
||||
},
|
||||
Err(err) => Err(err),
|
||||
}
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
pub fn init(&mut self, system: &System) -> Result<(), Error> {
|
||||
//self.state.msp = self.port.read_beu32(0)?;
|
||||
//self.state.pc = self.port.read_beu32(4)?;
|
||||
self.state.status = Status::Running;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn cycle_one(&mut self, system: &System) -> Result<(), Error> {
|
||||
//self.timer.cycle.start();
|
||||
self.decode_next(system)?;
|
||||
//self.execute_current(system)?;
|
||||
//self.timer.cycle.end();
|
||||
|
||||
//if (self.timer.cycle.events % 500) == 0 {
|
||||
// println!("{}", self.timer);
|
||||
//}
|
||||
|
||||
//self.check_pending_interrupts(system)?;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn decode_next(&mut self, system: &System) -> Result<(), Error> {
|
||||
//self.check_breakpoints(system);
|
||||
|
||||
//self.timer.decode.start();
|
||||
self.decoder.decode_at(&mut self.port, self.state.pc)?;
|
||||
//self.timer.decode.end();
|
||||
|
||||
//if self.debugger.use_tracing {
|
||||
self.decoder.dump_decoded(&mut self.port);
|
||||
//}
|
||||
|
||||
self.state.pc = self.decoder.end;
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub fn execute_current(&mut self, system: &System) -> Result<(), Error> {
|
||||
panic!("unimplemented");
|
||||
}
|
||||
}
|
||||
|
||||
7
src/cpus/z80/mod.rs
Normal file
7
src/cpus/z80/mod.rs
Normal file
|
|
@ -0,0 +1,7 @@
|
|||
|
||||
pub mod state;
|
||||
pub mod decode;
|
||||
pub mod execute;
|
||||
|
||||
pub use self::state::{Z80, Z80Type};
|
||||
|
||||
161
src/cpus/z80/state.rs
Normal file
161
src/cpus/z80/state.rs
Normal file
|
|
@ -0,0 +1,161 @@
|
|||
|
||||
use crate::system::System;
|
||||
use crate::devices::Address;
|
||||
use crate::memory::BusPort;
|
||||
|
||||
use super::decode::Z80Decoder;
|
||||
//use super::debugger::M68kDebugger;
|
||||
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord)]
|
||||
pub enum Z80Type {
|
||||
Z80,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq)]
|
||||
pub enum Status {
|
||||
Init,
|
||||
Running,
|
||||
Halted,
|
||||
}
|
||||
|
||||
|
||||
#[repr(u8)]
|
||||
#[allow(dead_code)]
|
||||
#[derive(Copy, Clone, Debug, PartialEq)]
|
||||
pub enum Flags {
|
||||
Carry = 0x0001,
|
||||
Overflow = 0x0002,
|
||||
Zero = 0x0004,
|
||||
Negative = 0x0008,
|
||||
Extend = 0x0010,
|
||||
}
|
||||
|
||||
/*
|
||||
#[repr(u8)]
|
||||
#[allow(dead_code)]
|
||||
#[derive(Copy, Clone, Debug, PartialEq)]
|
||||
pub enum Exceptions {
|
||||
BusError = 2,
|
||||
AddressError = 3,
|
||||
IllegalInstruction = 4,
|
||||
ZeroDivide = 5,
|
||||
ChkInstruction = 6,
|
||||
TrapvInstruction = 7,
|
||||
PrivilegeViolation = 8,
|
||||
}
|
||||
|
||||
|
||||
#[repr(u8)]
|
||||
#[derive(Copy, Clone, Debug, PartialEq)]
|
||||
pub enum InterruptPriority {
|
||||
NoInterrupt = 0,
|
||||
Level1 = 1,
|
||||
Level2 = 2,
|
||||
Level3 = 3,
|
||||
Level4 = 4,
|
||||
Level5 = 5,
|
||||
Level6 = 6,
|
||||
Level7 = 7,
|
||||
}
|
||||
|
||||
impl InterruptPriority {
|
||||
pub fn from_u8(priority: u8) -> InterruptPriority {
|
||||
match priority {
|
||||
0 => InterruptPriority::NoInterrupt,
|
||||
1 => InterruptPriority::Level1,
|
||||
2 => InterruptPriority::Level2,
|
||||
3 => InterruptPriority::Level3,
|
||||
4 => InterruptPriority::Level4,
|
||||
5 => InterruptPriority::Level5,
|
||||
6 => InterruptPriority::Level6,
|
||||
_ => InterruptPriority::Level7,
|
||||
}
|
||||
}
|
||||
}
|
||||
*/
|
||||
|
||||
#[derive(Clone, Debug, PartialEq)]
|
||||
pub struct Z80State {
|
||||
pub status: Status,
|
||||
|
||||
pub pc: u16,
|
||||
pub sp: u16,
|
||||
pub ix: u16,
|
||||
pub iy: u16,
|
||||
|
||||
pub reg: [u8; 8],
|
||||
pub alt_reg: [u8; 8],
|
||||
|
||||
pub i: u8,
|
||||
pub r: u8,
|
||||
}
|
||||
|
||||
impl Z80State {
|
||||
pub fn new() -> Self {
|
||||
Self {
|
||||
status: Status::Init,
|
||||
|
||||
pc: 0,
|
||||
sp: 0,
|
||||
ix: 0,
|
||||
iy: 0,
|
||||
|
||||
reg: [0; 8],
|
||||
alt_reg: [0; 8],
|
||||
|
||||
i: 0,
|
||||
r: 0,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Z80 {
|
||||
pub cputype: Z80Type,
|
||||
pub frequency: u32,
|
||||
pub state: Z80State,
|
||||
pub decoder: Z80Decoder,
|
||||
//pub debugger: M68kDebugger,
|
||||
pub port: BusPort,
|
||||
}
|
||||
|
||||
impl Z80 {
|
||||
pub fn new(cputype: Z80Type, frequency: u32, port: BusPort) -> Self {
|
||||
Self {
|
||||
cputype,
|
||||
frequency,
|
||||
state: Z80State::new(),
|
||||
decoder: Z80Decoder::new(),
|
||||
//debugger: M68kDebugger::new(),
|
||||
port: port,
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
pub fn reset(&mut self) {
|
||||
self.state = Z80State::new();
|
||||
//self.decoder = M68kDecoder::new(self.cputype, 0);
|
||||
//self.debugger = M68kDebugger::new();
|
||||
}
|
||||
|
||||
/*
|
||||
pub fn dump_state(&mut self, system: &System) {
|
||||
println!("Status: {:?}", self.state.status);
|
||||
println!("PC: {:#010x}", self.state.pc);
|
||||
println!("SR: {:#06x}", self.state.sr);
|
||||
for i in 0..7 {
|
||||
println!("D{}: {:#010x} A{}: {:#010x}", i, self.state.d_reg[i as usize], i, self.state.a_reg[i as usize]);
|
||||
}
|
||||
println!("D7: {:#010x}", self.state.d_reg[7]);
|
||||
println!("MSP: {:#010x}", self.state.msp);
|
||||
println!("USP: {:#010x}", self.state.usp);
|
||||
|
||||
println!("Current Instruction: {:#010x} {:?}", self.decoder.start, self.decoder.instruction);
|
||||
println!("");
|
||||
self.port.dump_memory(self.state.msp as Address, 0x40);
|
||||
println!("");
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
11
todo.txt
11
todo.txt
|
|
@ -2,11 +2,6 @@
|
|||
* fix ym7101 to better handle V/H interrupts (right now it sets and then the next step will clear, but it'd be nice if it could 'edge trigger')
|
||||
|
||||
* could have a remapper device, which takes a big swath of addresses in and maps them to another set of addresses (for Mac VIA generic to bus-hookup-in-mac adapter)
|
||||
|
||||
* sort out how inputing keys will work
|
||||
* separate the debugger out of m68k, use on_debug or something to print out debug info
|
||||
* make devices nameable, using a hashmap to store them
|
||||
|
||||
* how can you do devices that change their address map during operation, like mac which puts rom at 0 and ram at 600000 temporarily
|
||||
* i need a better way of handling disperate reads/writes to I/O spaces, rather than having multiple devices or having a massive chunk of address space allocated, continuously
|
||||
* should you modify Addressable to also take the absolute address as input? I'm thinking of how the same device could be mapped to multiple addresses in memory instead
|
||||
|
|
@ -15,12 +10,6 @@
|
|||
So both could share the same Signal, one setting it and the other reading it, but how would you actually configure/build that?
|
||||
|
||||
|
||||
We Need:
|
||||
* devices that change address mapping during operation
|
||||
* device that can be mapped to multiple separated locations while sharing data
|
||||
* subdevices that can share data (eg. signal from one to another (mac128 via outputs), or being a subdevice with a special trait (joystick))
|
||||
|
||||
|
||||
|
||||
* implement a Z80
|
||||
* maybe see about a Mac 128k or something
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user