mirror of
https://github.com/transistorfet/moa.git
synced 2024-06-25 18:29:33 +00:00
Fixed decode and excute issues with Z80
This commit is contained in:
transistor
parent
0836b6de8b
commit
f6105de939
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@ -65,7 +65,7 @@ impl Debuggable for M68k {
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fn print_disassembly(&mut self, addr: Address, count: usize) {
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let mut decoder = M68kDecoder::new(self.cputype, 0);
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decoder.dump_disassembly(&mut self.port, self.state.pc, 0x1000);
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decoder.dump_disassembly(&mut self.port, addr as u32, count as u32);
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}
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fn execute_command(&mut self, system: &System, args: &[&str]) -> Result<bool, Error> {
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@ -39,10 +39,17 @@ impl Debuggable for Z80 {
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fn print_disassembly(&mut self, addr: Address, count: usize) {
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let mut decoder = Z80Decoder::new();
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//decoder.dump_disassembly(&mut self.port, self.state.pc, 0x1000);
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decoder.dump_disassembly(&mut self.port, addr as u16, count as u16);
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}
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fn execute_command(&mut self, system: &System, args: &[&str]) -> Result<bool, Error> {
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match args[0] {
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"l" => {
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use super::state::Register;
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self.state.reg[Register::L as usize] = 0x05
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},
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_ => { return Ok(true); },
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}
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Ok(false)
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}
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}
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@ -5,6 +5,12 @@ use crate::devices::{Address, Addressable};
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use super::state::{Z80, Z80Type, Register};
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Direction {
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ToAcc,
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FromAcc,
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}
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#[derive(Copy, Clone, Debug, PartialEq)]
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pub enum Size {
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Byte,
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@ -72,14 +78,13 @@ pub enum LoadTarget {
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IndirectRegWord(RegisterPair),
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IndirectOffsetByte(IndexRegister, i8),
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DirectAltRegByte(Register),
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DirectSpecialRegByte(SpecialRegister),
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IndirectByte(u16),
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IndirectWord(u16),
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ImmediateByte(u8),
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ImmediateWord(u16),
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}
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pub type OptionalSource = Option<(IndexRegister, i8)>;
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pub type UndocumentedCopy = Option<Target>;
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#[derive(Clone, Debug, PartialEq)]
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pub enum Instruction {
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@ -124,6 +129,7 @@ pub enum Instruction {
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JR(i8),
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JRcc(Condition, i8),
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LD(LoadTarget, LoadTarget),
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LDsr(SpecialRegister, Direction),
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LDD,
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LDDR,
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LDI,
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@ -139,30 +145,30 @@ pub enum Instruction {
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OUTx(u8),
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POP(RegisterPair),
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PUSH(RegisterPair),
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RES(u8, Target, OptionalSource),
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RES(u8, Target, UndocumentedCopy),
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RET,
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RETI,
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RETN,
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RETcc(Condition),
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RL(Target, OptionalSource),
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RL(Target, UndocumentedCopy),
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RLA,
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RLC(Target, OptionalSource),
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RLC(Target, UndocumentedCopy),
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RLCA,
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RLD,
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RR(Target, OptionalSource),
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RR(Target, UndocumentedCopy),
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RRA,
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RRC(Target, OptionalSource),
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RRC(Target, UndocumentedCopy),
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RRCA,
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RRD,
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RST(u8),
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SBCa(Target),
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SBC16(RegisterPair, RegisterPair),
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SCF,
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SET(u8, Target, OptionalSource),
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SLA(Target, OptionalSource),
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SLL(Target, OptionalSource),
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SRA(Target, OptionalSource),
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SRL(Target, OptionalSource),
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SET(u8, Target, UndocumentedCopy),
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SLA(Target, UndocumentedCopy),
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SLL(Target, UndocumentedCopy),
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SRA(Target, UndocumentedCopy),
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SRL(Target, UndocumentedCopy),
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SUB(Target),
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XOR(Target),
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}
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@ -380,25 +386,18 @@ impl Z80Decoder {
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}
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pub fn decode_sub_prefix_cb(&mut self, memory: &mut dyn Addressable, reg: IndexRegister) -> Result<Instruction, Error> {
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let offset = self.read_instruction_byte(memory)? as i8;
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let ins = self.read_instruction_byte(memory)?;
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let opt_copy = match get_ins_z(ins) {
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6 => None, //Some(Target::DirectReg(Register::F)),
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z => Some(get_register(z)),
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};
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match get_ins_x(ins) {
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0 => {
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// TODO you need to fix the case where (HL) is specified...
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let opt_src = Some((reg, self.read_instruction_byte(memory)? as i8));
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Ok(get_rot_instruction(get_ins_y(ins), get_register(get_ins_z(ins)), opt_src))
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},
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1 => {
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let offset = self.read_instruction_byte(memory)? as i8;
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Ok(Instruction::BIT(get_ins_y(ins), Target::IndirectOffset(reg, offset)))
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},
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2 => {
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let opt_src = Some((reg, self.read_instruction_byte(memory)? as i8));
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Ok(Instruction::RES(get_ins_y(ins), get_register(get_ins_z(ins)), opt_src))
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},
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3 => {
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let opt_src = Some((reg, self.read_instruction_byte(memory)? as i8));
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Ok(Instruction::SET(get_ins_y(ins), get_register(get_ins_z(ins)), opt_src))
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},
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0 => Ok(get_rot_instruction(get_ins_y(ins), Target::IndirectOffset(reg, offset), opt_copy)),
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1 => Ok(Instruction::BIT(get_ins_y(ins), Target::IndirectOffset(reg, offset))),
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2 => Ok(Instruction::RES(get_ins_y(ins), Target::IndirectOffset(reg, offset), opt_copy)),
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3 => Ok(Instruction::SET(get_ins_y(ins), Target::IndirectOffset(reg, offset), opt_copy)),
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_ => panic!("InternalError: impossible value"),
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}
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}
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@ -458,10 +457,10 @@ impl Z80Decoder {
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},
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7 => {
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match get_ins_y(ins) {
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0 => Ok(Instruction::LD(LoadTarget::DirectSpecialRegByte(SpecialRegister::I), LoadTarget::DirectRegByte(Register::A))),
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1 => Ok(Instruction::LD(LoadTarget::DirectSpecialRegByte(SpecialRegister::R), LoadTarget::DirectRegByte(Register::A))),
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2 => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), LoadTarget::DirectSpecialRegByte(SpecialRegister::I))),
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3 => Ok(Instruction::LD(LoadTarget::DirectRegByte(Register::A), LoadTarget::DirectSpecialRegByte(SpecialRegister::R))),
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0 => Ok(Instruction::LDsr(SpecialRegister::I, Direction::FromAcc)),
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1 => Ok(Instruction::LDsr(SpecialRegister::R, Direction::FromAcc)),
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2 => Ok(Instruction::LDsr(SpecialRegister::I, Direction::ToAcc)),
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3 => Ok(Instruction::LDsr(SpecialRegister::R, Direction::ToAcc)),
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4 => Ok(Instruction::RRD),
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5 => Ok(Instruction::RLD),
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_ => Ok(Instruction::NOP),
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@ -690,6 +689,22 @@ impl Z80Decoder {
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let ins_data = self.format_instruction_bytes(memory);
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println!("{:#06x}: {}\n\t{:?}\n", self.start, ins_data, self.instruction);
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}
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pub fn dump_disassembly(&mut self, memory: &mut dyn Addressable, start: u16, length: u16) {
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let mut next = start;
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while next < (start + length) {
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match self.decode_at(memory, next) {
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Ok(()) => {
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self.dump_decoded(memory);
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next = self.end;
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},
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Err(err) => {
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println!("{:?}", err);
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return;
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},
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}
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}
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}
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}
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fn get_alu_instruction(alu: u8, target: Target) -> Instruction {
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@ -706,16 +721,16 @@ fn get_alu_instruction(alu: u8, target: Target) -> Instruction {
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}
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}
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fn get_rot_instruction(rot: u8, target: Target, opt_src: OptionalSource) -> Instruction {
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fn get_rot_instruction(rot: u8, target: Target, opt_copy: UndocumentedCopy) -> Instruction {
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match rot {
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0 => Instruction::RLC(target, opt_src),
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1 => Instruction::RRC(target, opt_src),
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2 => Instruction::RL(target, opt_src),
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3 => Instruction::RR(target, opt_src),
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4 => Instruction::SLA(target, opt_src),
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5 => Instruction::SRA(target, opt_src),
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6 => Instruction::SLL(target, opt_src),
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7 => Instruction::SRL(target, opt_src),
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0 => Instruction::RLC(target, opt_copy),
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1 => Instruction::RRC(target, opt_copy),
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2 => Instruction::RL(target, opt_copy),
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3 => Instruction::RR(target, opt_copy),
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4 => Instruction::SLA(target, opt_copy),
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5 => Instruction::SRA(target, opt_copy),
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6 => Instruction::SLL(target, opt_copy),
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7 => Instruction::SRL(target, opt_copy),
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_ => panic!("InternalError: impossible value"),
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}
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}
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@ -3,7 +3,7 @@ use crate::system::System;
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use crate::error::{ErrorType, Error};
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use crate::devices::{ClockElapsed, Address, Steppable, Addressable, Interruptable, Debuggable, Transmutable, read_beu16, write_beu16};
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use super::decode::{Condition, Instruction, LoadTarget, Target, OptionalSource, RegisterPair, IndexRegister, IndexRegisterHalf, Size};
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use super::decode::{Condition, Instruction, LoadTarget, Target, RegisterPair, IndexRegister, IndexRegisterHalf, Size, Direction, UndocumentedCopy};
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use super::state::{Z80, Status, Flags, Register};
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@ -273,6 +273,7 @@ impl Z80 {
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let value = self.get_target_value(target)?;
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let (result, carry, overflow) = add_bytes(value, 1);
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let carry = self.get_flag(Flags::Carry); // Preserve the carry bit, according to Z80 reference
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self.set_arithmetic_op_flags(result as u16, Size::Byte, false, carry, overflow, (result & 0x10) != 0);
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self.set_target_value(target, result)?;
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@ -312,11 +313,10 @@ impl Z80 {
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},
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Instruction::LD(dest, src) => {
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let src_value = self.get_load_target_value(src)?;
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if let LoadTarget::DirectSpecialRegByte(_) = src {
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self.set_logic_op_flags(src_value as u8, self.get_flag(Flags::Carry), false);
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}
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self.set_load_target_value(dest, src_value)?;
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},
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//Instruction::LDsr(special_reg, dir) => {
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//}
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//Instruction::LDD => {
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//},
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//Instruction::LDDR => {
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@ -364,7 +364,7 @@ impl Z80 {
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//},
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Instruction::OUTx(port) => {
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// TODO this needs to be fixed
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println!("OUT ({:x}), {:x}", port, self.state.reg[Register::A as usize]);
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println!("OUT ({:x}), {:x} {}", port, self.state.reg[Register::A as usize], self.state.reg[Register::A as usize] as char);
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},
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Instruction::POP(regpair) => {
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let value = self.pop_word()?;
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@ -374,10 +374,13 @@ impl Z80 {
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let value = self.get_register_pair_value(regpair);
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self.push_word(value)?;
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},
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Instruction::RES(bit, target, opt_src) => {
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let mut value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::RES(bit, target, opt_copy) => {
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let mut value = self.get_target_value(target)?;
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value = value & !(1 << bit);
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self.set_target_value(target, value);
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self.set_target_value(target, value)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::RET => {
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self.state.pc = self.pop_word()?;
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@ -391,11 +394,14 @@ impl Z80 {
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self.state.pc = self.pop_word()?;
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}
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},
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Instruction::RL(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::RL(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let (result, out_bit) = self.rotate_left(value, RotateType::Bit9);
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::RLA => {
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let value = self.get_register_value(Register::A);
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@ -403,11 +409,14 @@ impl Z80 {
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self.set_logic_op_flags(result, out_bit, false);
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self.set_register_value(Register::A, result);
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},
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Instruction::RLC(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::RLC(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let (result, out_bit) = self.rotate_left(value, RotateType::Bit8);
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::RLCA => {
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let value = self.get_register_value(Register::A);
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@ -417,11 +426,14 @@ impl Z80 {
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},
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//Instruction::RLD => {
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//},
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Instruction::RR(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::RR(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let (result, out_bit) = self.rotate_right(value, RotateType::Bit9);
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::RRA => {
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let value = self.get_register_value(Register::A);
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@ -429,11 +441,14 @@ impl Z80 {
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self.set_logic_op_flags(result, out_bit, false);
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self.set_register_value(Register::A, result);
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},
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Instruction::RRC(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::RRC(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let (result, out_bit) = self.rotate_right(value, RotateType::Bit8);
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::RRCA => {
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let value = self.get_register_value(Register::A);
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@ -472,39 +487,54 @@ impl Z80 {
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self.set_flag(Flags::HalfCarry, false);
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self.set_flag(Flags::Carry, true);
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},
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Instruction::SET(bit, target, opt_src) => {
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let mut value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::SET(bit, target, opt_copy) => {
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let mut value = self.get_target_value(target)?;
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value = value | (1 << bit);
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self.set_target_value(target, value)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::SLA(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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let out_bit = get_msb(value as u16, Size::Byte);
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let result = (value << 1) | 0x01;
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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},
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Instruction::SLL(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::SLA(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let out_bit = get_msb(value as u16, Size::Byte);
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let result = value << 1;
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::SRA(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::SLL(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let out_bit = get_msb(value as u16, Size::Byte);
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let result = value << 1;
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::SRA(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let out_bit = (value & 0x01) != 0;
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let msb_mask = if get_msb(value as u16, Size::Byte) { 0x80 } else { 0 };
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let result = (value >> 1) | msb_mask;
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self.set_logic_op_flags(result, out_bit, false);
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self.set_target_value(target, result)?;
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if let Some(target) = opt_copy {
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self.set_target_value(target, value)?;
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}
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},
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Instruction::SRL(target, opt_src) => {
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let value = self.get_opt_src_target_value(opt_src, target)?;
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Instruction::SRL(target, opt_copy) => {
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let value = self.get_target_value(target)?;
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let out_bit = (value & 0x01) != 0;
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let result = value >> 1;
|
||||
self.set_logic_op_flags(result, out_bit, false);
|
||||
self.set_target_value(target, result)?;
|
||||
if let Some(target) = opt_copy {
|
||||
self.set_target_value(target, value)?;
|
||||
}
|
||||
},
|
||||
Instruction::SUB(target) => {
|
||||
let src = self.get_target_value(target)?;
|
||||
|
|
@ -675,21 +705,15 @@ impl Z80 {
|
|||
let addr = self.get_register_pair_value(regpair);
|
||||
self.port.write_u8(addr as Address, value)?;
|
||||
},
|
||||
Target::IndirectOffset(reg, offset) => {
|
||||
let addr = (self.get_index_register_value(reg) as i16) + (offset as i16);
|
||||
self.port.write_u8(addr as Address, value)?;
|
||||
},
|
||||
_ => panic!("Unsupported LoadTarget for set"),
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
fn get_opt_src_target_value(&mut self, opt_src: OptionalSource, target: Target) -> Result<u8, Error> {
|
||||
match opt_src {
|
||||
None => self.get_target_value(target),
|
||||
Some((reg, offset)) => {
|
||||
let addr = (self.get_index_register_value(reg) as i16) + (offset as i16);
|
||||
self.port.read_u8(addr as Address)
|
||||
},
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
fn get_register_value(&mut self, reg: Register) -> u8 {
|
||||
self.state.reg[reg as usize]
|
||||
|
|
|
|||
|
|
@ -127,10 +127,10 @@ impl Z80 {
|
|||
println!("IX: {:#06x}", self.state.ix);
|
||||
println!("IY: {:#06x}", self.state.iy);
|
||||
|
||||
println!("A: {:#04x} F: {:#04x}", self.state.reg[Register::A as usize], self.state.reg[Register::F as usize]);
|
||||
println!("B: {:#04x} C: {:#04x}", self.state.reg[Register::B as usize], self.state.reg[Register::C as usize]);
|
||||
println!("D: {:#04x} E: {:#04x}", self.state.reg[Register::D as usize], self.state.reg[Register::E as usize]);
|
||||
println!("H: {:#04x} L: {:#04x}", self.state.reg[Register::H as usize], self.state.reg[Register::L as usize]);
|
||||
println!("A: {:#04x} F: {:#04x} A': {:#04x} F': {:#04x}", self.state.reg[Register::A as usize], self.state.reg[Register::F as usize], self.state.shadow_reg[Register::A as usize], self.state.shadow_reg[Register::F as usize]);
|
||||
println!("B: {:#04x} C: {:#04x} B': {:#04x} C': {:#04x}", self.state.reg[Register::B as usize], self.state.reg[Register::C as usize], self.state.shadow_reg[Register::B as usize], self.state.shadow_reg[Register::C as usize]);
|
||||
println!("D: {:#04x} E: {:#04x} D': {:#04x} E': {:#04x}", self.state.reg[Register::D as usize], self.state.reg[Register::E as usize], self.state.shadow_reg[Register::D as usize], self.state.shadow_reg[Register::E as usize]);
|
||||
println!("H: {:#04x} L: {:#04x} H': {:#04x} L': {:#04x}", self.state.reg[Register::H as usize], self.state.reg[Register::L as usize], self.state.shadow_reg[Register::H as usize], self.state.shadow_reg[Register::L as usize]);
|
||||
|
||||
println!("Current Instruction: {} {:?}", self.decoder.format_instruction_bytes(&mut self.port), self.decoder.instruction);
|
||||
println!("");
|
||||
|
|
|
|||
|
|
@ -73,44 +73,6 @@ mod decode_tests {
|
|||
(&[0xDD, 0x84], Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXH))),
|
||||
(&[0xDD, 0x85], Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXL))),
|
||||
];
|
||||
|
||||
/*
|
||||
#[test]
|
||||
fn decode_add_ix_bc() {
|
||||
let instruction = run_decode_test(&[0xDD, 0x09]);
|
||||
assert_eq!(instruction, Instruction::ADD16(RegisterPair::IX, RegisterPair::BC));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn decode_ld_b_ixh() {
|
||||
let instruction = run_decode_test(&[0xDD, 0x44]);
|
||||
assert_eq!(instruction, Instruction::LD(LoadTarget::DirectRegByte(Register::B), LoadTarget::DirectRegHalfByte(IndexRegisterHalf::IXH)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn decode_ld_h_ix_offset() {
|
||||
let instruction = run_decode_test(&[0xDD, 0x66, 0x12]);
|
||||
assert_eq!(instruction, Instruction::LD(LoadTarget::DirectRegByte(Register::H), LoadTarget::IndirectOffsetByte(IndexRegister::IX, 0x12)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn decode_ld_l_ix_offset() {
|
||||
let instruction = run_decode_test(&[0xDD, 0x6E, 0x12]);
|
||||
assert_eq!(instruction, Instruction::LD(LoadTarget::DirectRegByte(Register::L), LoadTarget::IndirectOffsetByte(IndexRegister::IX, 0x12)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn decode_add_ixh() {
|
||||
let instruction = run_decode_test(&[0xDD, 0x84]);
|
||||
assert_eq!(instruction, Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXH)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn decode_add_ixl() {
|
||||
let instruction = run_decode_test(&[0xDD, 0x85]);
|
||||
assert_eq!(instruction, Instruction::ADDa(Target::DirectRegHalf(IndexRegisterHalf::IXL)));
|
||||
}
|
||||
*/
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -124,6 +86,216 @@ mod execute_tests {
|
|||
use super::super::state::{Z80State, Register};
|
||||
use super::super::decode::{Instruction, LoadTarget, Target, RegisterPair, IndexRegister, IndexRegisterHalf, Condition};
|
||||
|
||||
struct TestState {
|
||||
pc: u16,
|
||||
sp: u16,
|
||||
ix: u16,
|
||||
iy: u16,
|
||||
bc: u16,
|
||||
de: u16,
|
||||
hl: u16,
|
||||
af: u16,
|
||||
}
|
||||
|
||||
struct TestCase {
|
||||
name: &'static str,
|
||||
ins: Instruction,
|
||||
data: &'static [u8],
|
||||
init: TestState,
|
||||
fini: TestState,
|
||||
}
|
||||
|
||||
const TEST_CASES: &'static [TestCase] = &[
|
||||
/*
|
||||
TestCase {
|
||||
name: ,
|
||||
ins: ,
|
||||
data: &[ 0x88 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
fini: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
},
|
||||
*/
|
||||
|
||||
TestCase {
|
||||
name: "adc with no carry",
|
||||
ins: Instruction::ADCa(Target::DirectReg(Register::B)),
|
||||
data: &[ 0x88 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0100, de: 0x0000, hl: 0x0000, af: 0xFE00 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0100, de: 0x0000, hl: 0x0000, af: 0xFF90 },
|
||||
},
|
||||
TestCase {
|
||||
name: "adc with carry already set",
|
||||
ins: Instruction::ADCa(Target::DirectReg(Register::B)),
|
||||
data: &[ 0x88 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0xFE01 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0xFF90 },
|
||||
},
|
||||
TestCase {
|
||||
name: "adc with carry already set while causing a carry",
|
||||
ins: Instruction::ADCa(Target::DirectReg(Register::B)),
|
||||
data: &[ 0x88 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0100, de: 0x0000, hl: 0x0000, af: 0xFE01 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0100, de: 0x0000, hl: 0x0000, af: 0x0041 },
|
||||
},
|
||||
TestCase {
|
||||
name: "adc16 with bc",
|
||||
ins: Instruction::ADC16(RegisterPair::HL, RegisterPair::BC),
|
||||
data: &[ 0xED, 0x4A ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x1010, de: 0x0000, hl: 0x8080, af: 0x0000 },
|
||||
fini: TestState { pc: 0x0002, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x1010, de: 0x0000, hl: 0x9090, af: 0x0090 },
|
||||
},
|
||||
TestCase {
|
||||
name: "add a with h",
|
||||
ins: Instruction::ADDa(Target::DirectReg(Register::H)),
|
||||
data: &[ 0x84 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x2200, af: 0x1000 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x2200, af: 0x3210 },
|
||||
},
|
||||
TestCase {
|
||||
name: "add a with h with overflow",
|
||||
ins: Instruction::ADDa(Target::DirectReg(Register::H)),
|
||||
data: &[ 0x84 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0100, af: 0x7F00 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0100, af: 0x8084 },
|
||||
},
|
||||
TestCase {
|
||||
name: "add hl and bc",
|
||||
ins: Instruction::ADD16(RegisterPair::HL, RegisterPair::BC),
|
||||
data: &[ 0x09 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x1080, de: 0x0000, hl: 0x0080, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x1080, de: 0x0000, hl: 0x1100, af: 0x00FC },
|
||||
},
|
||||
TestCase {
|
||||
name: "and with c",
|
||||
ins: Instruction::AND(Target::DirectReg(Register::C)),
|
||||
data: &[ 0xA1 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x00F0, de: 0x0000, hl: 0x0000, af: 0x55FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x00F0, de: 0x0000, hl: 0x0000, af: 0x5014 },
|
||||
},
|
||||
TestCase {
|
||||
name: "bit 3, c",
|
||||
ins: Instruction::BIT(3, Target::DirectReg(Register::C)),
|
||||
data: &[ 0xCB, 0x59 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x000F, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0002, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x000F, de: 0x0000, hl: 0x0000, af: 0x00BD },
|
||||
},
|
||||
TestCase {
|
||||
name: "call",
|
||||
ins: Instruction::CALL(0x1234),
|
||||
data: &[ 0xCD, 0x34, 0x12 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
fini: TestState { pc: 0x1234, sp: 0xFFFE, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
},
|
||||
TestCase {
|
||||
name: "call cc true",
|
||||
ins: Instruction::CALLcc(Condition::Zero, 0x1234),
|
||||
data: &[ 0xCC, 0x34, 0x12 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x1234, sp: 0xFFFE, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
},
|
||||
TestCase {
|
||||
name: "call cc false",
|
||||
ins: Instruction::CALLcc(Condition::Zero, 0x1234),
|
||||
data: &[ 0xCC, 0x34, 0x12 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
fini: TestState { pc: 0x0003, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
},
|
||||
TestCase {
|
||||
name: "ccf",
|
||||
ins: Instruction::CCF,
|
||||
data: &[ 0x3F ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FC },
|
||||
},
|
||||
TestCase {
|
||||
name: "ccf invert",
|
||||
ins: Instruction::CCF,
|
||||
data: &[ 0x3F ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0001 },
|
||||
},
|
||||
TestCase {
|
||||
name: "cp c where not equal",
|
||||
ins: Instruction::CP(Target::DirectReg(Register::C)),
|
||||
data: &[ 0xB9 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x00F0, de: 0x0000, hl: 0x0000, af: 0x55FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x00F0, de: 0x0000, hl: 0x0000, af: 0x5503 },
|
||||
},
|
||||
TestCase {
|
||||
name: "cp c where not equal",
|
||||
ins: Instruction::CP(Target::DirectReg(Register::C)),
|
||||
data: &[ 0xB9 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0055, de: 0x0000, hl: 0x0000, af: 0x55FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0055, de: 0x0000, hl: 0x0000, af: 0x5542 },
|
||||
},
|
||||
TestCase {
|
||||
name: "cpl",
|
||||
ins: Instruction::CPL,
|
||||
data: &[ 0x2F ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x5500 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0xAA12 },
|
||||
},
|
||||
TestCase {
|
||||
name: "dec hl",
|
||||
ins: Instruction::DEC16(RegisterPair::HL),
|
||||
data: &[ 0x2B ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0xFFFF, af: 0x00FF },
|
||||
},
|
||||
TestCase {
|
||||
name: "dec8",
|
||||
ins: Instruction::DEC8(Target::DirectReg(Register::C)),
|
||||
data: &[ 0x0D ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x0000 },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x00ff, de: 0x0000, hl: 0x0000, af: 0x0092 },
|
||||
},
|
||||
TestCase {
|
||||
name: "djnz with jump",
|
||||
ins: Instruction::DJNZ(0x10),
|
||||
data: &[ 0x10, 0x10 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0012, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0xff00, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
},
|
||||
TestCase {
|
||||
name: "djnz without jump",
|
||||
ins: Instruction::DJNZ(0x10),
|
||||
data: &[ 0x10, 0x10 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0100, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0002, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
},
|
||||
TestCase {
|
||||
name: "ex de, hl",
|
||||
ins: Instruction::EXhlde,
|
||||
data: &[ 0xEB ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x55AA, hl: 0x1234, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x1234, hl: 0x55AA, af: 0x00FF },
|
||||
},
|
||||
//TestCase {
|
||||
// name: "ex sp location",
|
||||
// ins: Instruction::EXhlde,
|
||||
// data: &[ 0xEB ],
|
||||
// init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x55AA, hl: 0x1234, af: 0x00FF },
|
||||
// fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x1234, hl: 0x55AA, af: 0x00FF },
|
||||
//},
|
||||
|
||||
TestCase {
|
||||
name: "inc ix",
|
||||
ins: Instruction::INC16(RegisterPair::IX),
|
||||
data: &[ 0xDD, 0x23 ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0002, sp: 0x0000, ix: 0x0001, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
},
|
||||
TestCase {
|
||||
name: "inc c",
|
||||
ins: Instruction::INC8(Target::DirectReg(Register::C)),
|
||||
data: &[ 0x0C ],
|
||||
init: TestState { pc: 0x0000, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0000, de: 0x0000, hl: 0x0000, af: 0x00FF },
|
||||
fini: TestState { pc: 0x0001, sp: 0x0000, ix: 0x0000, iy: 0x0000, bc: 0x0001, de: 0x0000, hl: 0x0000, af: 0x0001 },
|
||||
},
|
||||
|
||||
|
||||
];
|
||||
|
||||
fn init_execute_test() -> (Z80, System) {
|
||||
let mut system = System::new();
|
||||
|
||||
|
|
@ -139,239 +311,51 @@ mod execute_tests {
|
|||
(cpu, system)
|
||||
}
|
||||
|
||||
fn run_execute_test(init_state: Z80State, expected_state: Z80State, instruction: Instruction) {
|
||||
fn build_state(state: &TestState) -> Z80State {
|
||||
let mut new_state = Z80State::new();
|
||||
new_state.pc = state.pc;
|
||||
new_state.sp = state.sp;
|
||||
new_state.ix = state.ix;
|
||||
new_state.iy = state.iy;
|
||||
new_state.set_register(Register::B, (state.bc >> 8) as u8);
|
||||
new_state.set_register(Register::C, state.bc as u8);
|
||||
new_state.set_register(Register::D, (state.de >> 8) as u8);
|
||||
new_state.set_register(Register::E, state.de as u8);
|
||||
new_state.set_register(Register::H, (state.hl >> 8) as u8);
|
||||
new_state.set_register(Register::L, state.hl as u8);
|
||||
new_state.set_register(Register::A, (state.af >> 8) as u8);
|
||||
new_state.set_register(Register::F, state.af as u8);
|
||||
new_state
|
||||
}
|
||||
|
||||
fn load_memory(system: &System, data: &[u8]) {
|
||||
for i in 0..data.len() {
|
||||
system.get_bus().write_u8(i as Address, data[i]).unwrap();
|
||||
}
|
||||
}
|
||||
|
||||
fn run_test(case: &TestCase) {
|
||||
let (mut cpu, system) = init_execute_test();
|
||||
|
||||
let init_state = build_state(&case.init);
|
||||
let expected_state = build_state(&case.fini);
|
||||
|
||||
load_memory(&system, case.data);
|
||||
cpu.state = init_state;
|
||||
cpu.decoder.instruction = instruction;
|
||||
|
||||
cpu.decode_next(&system).unwrap();
|
||||
assert_eq!(cpu.decoder.instruction, case.ins);
|
||||
|
||||
cpu.execute_current(&system).unwrap();
|
||||
assert_eq!(cpu.state, expected_state);
|
||||
}
|
||||
|
||||
|
||||
/////////////////////
|
||||
// Execution Tests //
|
||||
/////////////////////
|
||||
|
||||
|
||||
#[test]
|
||||
fn execute_adca_b_carry_clear() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0xFE);
|
||||
init_state.set_register(Register::B, 0x01);
|
||||
init_state.set_register(Register::F, 0x00);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0xFF);
|
||||
expected_state.set_register(Register::F, 0x90);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADCa(Target::DirectReg(Register::B)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_adca_b_carry_set() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0xFE);
|
||||
init_state.set_register(Register::B, 0x00);
|
||||
init_state.set_register(Register::F, 0x01);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0xFF);
|
||||
expected_state.set_register(Register::F, 0x90);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADCa(Target::DirectReg(Register::B)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_adca_b_carry_set_with_carry() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0xFE);
|
||||
init_state.set_register(Register::B, 0x01);
|
||||
init_state.set_register(Register::F, 0x01);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0x00);
|
||||
expected_state.set_register(Register::F, 0x41);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADCa(Target::DirectReg(Register::B)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_adc16_ixl() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::H, 0x80);
|
||||
init_state.set_register(Register::L, 0x80);
|
||||
init_state.ix = 0x1010;
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::H, 0x90);
|
||||
expected_state.set_register(Register::L, 0x90);
|
||||
expected_state.set_register(Register::F, 0x90);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADC16(RegisterPair::HL, RegisterPair::IX));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_adda_h() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0x10);
|
||||
init_state.set_register(Register::H, 0x22);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0x32);
|
||||
expected_state.set_register(Register::F, 0x10);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADDa(Target::DirectReg(Register::H)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_adda_h_with_overflow() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0x7F);
|
||||
init_state.set_register(Register::H, 0x01);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0x80);
|
||||
expected_state.set_register(Register::F, 0x84);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADDa(Target::DirectReg(Register::H)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_add16_ixl() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.ix = 0x1080;
|
||||
init_state.set_register(Register::H, 0x00);
|
||||
init_state.set_register(Register::L, 0x80);
|
||||
init_state.set_register(Register::F, 0xFF); // S and Z flags should not be affected
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::H, 0x11);
|
||||
expected_state.set_register(Register::L, 0x00);
|
||||
expected_state.set_register(Register::F, 0xFC);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::ADD16(RegisterPair::HL, RegisterPair::IX));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_and_c() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0x55);
|
||||
init_state.set_register(Register::C, 0xF0);
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0x50);
|
||||
expected_state.set_register(Register::F, 0x14);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::AND(Target::DirectReg(Register::C)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_bit() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::C, 0x0F);
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::F, 0xBD);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::BIT(3, Target::DirectReg(Register::C)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_call() {
|
||||
let mut init_state = Z80State::new();
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.pc = 0x1234;
|
||||
expected_state.sp = 0xFFFE;
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CALL(0x1234));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_call_cc_true() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.pc = 0x1234;
|
||||
expected_state.sp = 0xFFFE;
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CALLcc(Condition::Zero, 0x1234));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_call_cc_false() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let expected_state = init_state.clone();
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CALLcc(Condition::NotZero, 0x1234));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_ccf() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::F, 0xFC);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CCF);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_ccf_invert() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::F, 0x00);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::F, 0x01);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CCF);
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_cp_c_diff() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0x55);
|
||||
init_state.set_register(Register::C, 0xF0);
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::F, 0x03);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CP(Target::DirectReg(Register::C)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_cp_c_equal() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0x55);
|
||||
init_state.set_register(Register::C, 0x55);
|
||||
init_state.set_register(Register::F, 0xFF);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::F, 0x42);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CP(Target::DirectReg(Register::C)));
|
||||
}
|
||||
|
||||
#[test]
|
||||
fn execute_cpl() {
|
||||
let mut init_state = Z80State::new();
|
||||
init_state.set_register(Register::A, 0x55);
|
||||
init_state.set_register(Register::F, 0x00);
|
||||
|
||||
let mut expected_state = init_state.clone();
|
||||
expected_state.set_register(Register::A, 0xAA);
|
||||
expected_state.set_register(Register::F, 0x12);
|
||||
|
||||
run_execute_test(init_state, expected_state, Instruction::CPL);
|
||||
pub fn run_execute_tests() {
|
||||
for case in TEST_CASES {
|
||||
println!("Running test {}", case.name);
|
||||
run_test(case);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -115,7 +115,19 @@ impl Debugger {
|
|||
}
|
||||
},
|
||||
"dis" | "disassemble" => {
|
||||
debug_obj.print_disassembly(0, 0);
|
||||
let addr = if args.len() > 1 {
|
||||
Address::from_str_radix(args[1], 16).map_err(|_| Error::new("Unable to parse address"))?
|
||||
} else {
|
||||
0
|
||||
};
|
||||
|
||||
let count = if args.len() > 2 {
|
||||
usize::from_str_radix(args[2], 16).map_err(|_| Error::new("Unable to parse address"))?
|
||||
} else {
|
||||
0x1000
|
||||
};
|
||||
|
||||
debug_obj.print_disassembly(addr, count);
|
||||
},
|
||||
"c" | "continue" => {
|
||||
self.check_repeat_arg(args)?;
|
||||
|
|
|
|||
|
|
@ -8,7 +8,6 @@ use crate::cpus::z80::{Z80, Z80Type};
|
|||
use crate::peripherals::trs80;
|
||||
|
||||
use crate::host::traits::Host;
|
||||
use crate::host::tty::SimplePty;
|
||||
|
||||
|
||||
pub fn build_trs80<H: Host>(host: &mut H) -> Result<System, Error> {
|
||||
|
|
@ -16,11 +15,11 @@ pub fn build_trs80<H: Host>(host: &mut H) -> Result<System, Error> {
|
|||
|
||||
let mut rom = MemoryBlock::new(vec![0; 0x4000]);
|
||||
rom.load_at(0x0000, "binaries/trs80/level1.rom")?;
|
||||
rom.load_at(0x1000, "binaries/trs80/level2.rom")?;
|
||||
//rom.load_at(0x0000, "binaries/trs80/level2.rom")?;
|
||||
rom.read_only();
|
||||
system.add_addressable_device(0x0000, wrap_transmutable(rom))?;
|
||||
|
||||
let mut ram = MemoryBlock::new(vec![0; 0xC000]);
|
||||
let ram = MemoryBlock::new(vec![0; 0xC000]);
|
||||
system.add_addressable_device(0x4000, wrap_transmutable(ram))?;
|
||||
|
||||
let model1 = trs80::model1::Model1Peripherals::create(host)?;
|
||||
|
|
@ -33,6 +32,24 @@ pub fn build_trs80<H: Host>(host: &mut H) -> Result<System, Error> {
|
|||
//cpu.add_breakpoint(0x1e5);
|
||||
//cpu.add_breakpoint(0x340); // "exec", the function that executes the line typed in
|
||||
//cpu.add_breakpoint(0x357);
|
||||
//cpu.add_breakpoint(0x401); // LIST command exec
|
||||
//cpu.add_breakpoint(0x10); // putchar
|
||||
//cpu.add_breakpoint(0x970);
|
||||
//cpu.add_breakpoint(0x9f9);
|
||||
//cpu.add_breakpoint(0xa58); // return from printing the line number
|
||||
//cpu.add_breakpoint(0xc59); // the function called first thing when printing a decimal number
|
||||
//cpu.add_breakpoint(0xe00); // normalize the float??
|
||||
//cpu.add_breakpoint(0x970); // just after the decimal number print function is called, but after the call at the start is complete
|
||||
//cpu.add_breakpoint(0xa6c);
|
||||
|
||||
//cpu.add_breakpoint(0xe00);
|
||||
//cpu.add_breakpoint(0xc77);
|
||||
//cpu.add_breakpoint(0xc83);
|
||||
//cpu.add_breakpoint(0x96d);
|
||||
cpu.add_breakpoint(0x970);
|
||||
cpu.add_breakpoint(0x9e2);
|
||||
cpu.add_breakpoint(0x9f9);
|
||||
|
||||
system.add_interruptable_device("cpu", wrap_transmutable(cpu))?;
|
||||
|
||||
Ok(system)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user