Commit Graph

61 Commits

Author SHA1 Message Date
transistor
24e050a840 Added supervisor checks 2021-10-16 10:01:14 -07:00
transistor
1732c90f5b Added formatter for Instruction to output assembly 2021-10-15 11:12:47 -07:00
transistor
eba1f9c9fc Fixed bug with ANDtoSR, which was actually using "or" 2021-10-14 22:04:14 -07:00
transistor
43b1abfa19 Minor changes 2021-10-14 21:16:31 -07:00
transistor
39ecd1b0d9 Added decode for ABCD and SBCD 2021-10-10 20:47:51 -07:00
transistor
94141e112e Reorganized decode and add some support for other m68k processors 2021-10-10 14:26:54 -07:00
transistor
b588563acc Updated readme 2021-10-09 20:35:52 -07:00
transistor
8bb43f61ee Fixed interrupts and added tx enable for OS buffered output 2021-10-08 10:52:15 -07:00
transistor
73d11ddb79 Switched to using Rc<RefCell<Box<dyn Trait>>> for devices 2021-10-07 09:41:01 -07:00
transistor
5ea2ccc128 Added TRAP instruction and exception handling 2021-10-05 21:53:18 -07:00
transistor
338e68a1d9 Fixed some erroneous instruction decodes and added binaries 2021-10-03 09:55:20 -07:00