More half-baked newfpu goodness
Once the framework for handling exceptions, accrued exceptions, condition codes, and rounding is done, I can start implementing actual "fmath" instructions. Everything not handled by softfloat will be imprecisely and hackily implemented by using the best available native float math (e.g. cosf(), cos(), or cosl())
This commit is contained in:
pruten
parent
bb2ec0a27d
commit
bb6d1e719f
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@ -1,23 +0,0 @@
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#include <stdio.h>
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#include <stdint.h>
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#include <math.h>
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#include "softfloat.h"
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floatx80 f[8];
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int main (void)
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{
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float128 a = int64_to_float128(123);
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float128 b = int64_to_float128(123);
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float128 c = float128_mul(a, b);
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int32_t c_int = float128_to_int32(c);
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printf("123 * 123 = %d (expected %d)\n", c_int, 123 * 123);
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printf("%f\n", a);
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return 0;
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}
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552
core/newfpu.c
552
core/newfpu.c
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@ -131,6 +131,40 @@ typedef struct {
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} fpu_state_t;
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enum rounding_precision_t {
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prec_extended = 0,
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prec_single = 1,
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prec_double = 2,
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};
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enum rounding_mode_t {
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mode_nearest = 0,
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mode_zero = 1,
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mode_neg = 2,
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mode_pos = 3
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};
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/*
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* 0 L long word integer
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* 1 S single precision real
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* 2 X extended precision real
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* 3 P{#k} packed decimal real with static k factor
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* 4 W word integer
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* 5 D double precision real
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* 6 B byte integer
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* 7 P{Dn} packed decimal real with dynamic k factor
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*/
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static const uint8_t _format_sizes[8] = {4, 4, 12, 12, 2, 8, 1, 12};
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enum {
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format_L = 0,
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format_S = 1,
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format_X = 2,
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format_Ps = 3,
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format_W = 4,
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format_D = 5,
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format_B = 6,
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format_Pd = 7
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} fpu_formats;
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#define fpu_get_state_ptr() fpu_state_t *fpu = (fpu_state_t*)shoe.fpu_state
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#define nextword() ({const uint16_t w=lget(shoe.pc,2); if (shoe.abort) {return;}; shoe.pc+=2; w;})
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@ -189,10 +223,215 @@ static _Bool _bsun_test()
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return 1;
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}
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#pragma mark Float format translators
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static float128 _int8_to_intermediate(int8_t byte)
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{
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return int32_to_float128((int32_t)byte);
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}
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static float128 _int16_to_intermediate(int16_t sh)
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{
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return int32_to_float128((int32_t)sh);
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}
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static float128 _int32_to_intermediate(int32_t in)
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{
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return int32_to_float128(in);
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}
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static float128 _float_to_intermediate(uint32_t f)
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{
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assert(sizeof(uint32_t) == sizeof(float32));
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return float32_to_float128((float32)f);
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}
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/*
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* _double_to_intermediate(d): d needs to be 68k-native order (8 bytes)
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*/
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static float128 _double_to_intermediate(uint8_t *d)
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{
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assert(sizeof(uint64_t) == sizeof(float64));
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return float64_to_float128((float64) ntohll(*(uint64_t*)d));
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}
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/*
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* _extended_to_intermediate(e): e needs to be 68k-native order (12 bytes)
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*/
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static float128 _extended_to_intermediate(uint8_t *e)
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{
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/*
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* softfloat floatx80 format:
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* uint64_t low; // the low part of the extended float (significand, low exponent bits)
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* uint16_t high; // the high part, sign, high exponent bits
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*/
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floatx80 x80 = {
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.high = (e[0] << 8) | e[1],
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.low = ntohll(*(uint64_t*)&e[4])
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};
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return floatx80_to_float128(x80);
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}
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/*
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* Set softfloat's rounding mode
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* (fpcr.mc_rnd and softfloat use different values for these modes)
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*/
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static void _set_rounding_mode(enum rounding_mode_t mode)
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{
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const int8 rounding_map[4] = {
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float_round_nearest_even, float_round_to_zero,
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float_round_up, float_round_down
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};
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float_rounding_mode = rounding_map[mode];
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}
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#pragma mark EA routines
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/*
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* Note: fpu_read_ea modifies shoe.pc, and fpu_read_ea_commit
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* modifies shoe.a[x] for pre/post-inc/decrement
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* Returns false if we're aborting
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*/
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static _Bool _fpu_read_ea(const uint8_t format, float128 *result)
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{
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fpu_get_state_ptr();
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~decompose(shoe.op, 0000 0000 00 mmmrrr);
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const uint8_t size = _format_sizes[format];
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uint32_t addr = 0;
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/*
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* Step 1: find the effective address, store it in addr
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* (or the actual data, if unavailable)
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*/
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switch (m) {
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case 0:
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if (format == format_S)
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*result = _float_to_intermediate(shoe.d[r]);
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else if (format == format_B)
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*result = _int8_to_intermediate(shoe.d[r] & 0xff);
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else if (format == format_W)
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*result = _int16_to_intermediate(shoe.d[r] & 0xffff);
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else if (format == format_L)
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*result = int32_to_float128(shoe.d[r]);
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else {
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/*
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* No other format can be used with a data register
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* (because they require >4 bytes)
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*/
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throw_illegal_instruction();
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return 0;
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}
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goto got_data;
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case 1:
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/* Address regisers can't be used */
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throw_illegal_instruction();
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return 0;
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case 3:
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addr = shoe.a[r];
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assert(!( r==7 && size==1));
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goto got_address;
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case 4:
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addr = shoe.a[r] - size;
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assert(!( r==7 && size==1));
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goto got_address;
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case 7:
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if (r == 4) {
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addr = shoe.pc;
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shoe.pc += size;
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goto got_address;
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}
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// fall through to default:
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default: {
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~decompose(shoe.op, 0000 0000 00 MMMMMM);
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shoe.mr = M;
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ea_addr();
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if (shoe.abort)
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return 0;
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addr = (uint32_t)shoe.dat;
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goto got_address;
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}
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}
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got_address:
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/*
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* Step 2: Load the data from the effective address
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*/
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if (size <= 4) {
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const uint32_t raw = lget(addr, size);
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if (shoe.abort)
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return 0;
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switch (format) {
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case format_B:
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*result = _int8_to_intermediate(raw & 0xff);
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break;
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case format_W:
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*result = _int16_to_intermediate(raw & 0xffff);
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break;
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case format_L:
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*result = _int32_to_intermediate(raw);
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break;
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case format_S:
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*result = _int32_to_intermediate(raw);
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break;
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default:
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assert(0); /* never get here */
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}
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}
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else { // if (size > 4) -> if format is double, extended, or packed
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uint8_t buf[12];
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uint32_t i;
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for (i = 0; i < size; i++) {
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buf[i] = lget(addr + i, 1);
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if (shoe.abort)
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return 0;
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}
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switch (format) {
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case format_D:
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*result = _double_to_intermediate(buf);
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break;
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case format_X:
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*result = _extended_to_intermediate(buf);
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break;
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case format_Ps:
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case format_Pd:
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// FIXME: implement packed formats
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assert(!"Somebody tried to use a packed format!\n");
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// throw_illegal_instruction();
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// return 0;
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default:
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assert(0); // never get here
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}
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}
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got_data:
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return 1;
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}
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#pragma mark Second-hop instructions
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static void inst_fmath (const uint16_t ext)
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{
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fpu_get_state_ptr();
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~decompose(shoe.op, 1111 001 000 MMMMMM);
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~decompose(ext, 0 a 0 sss ddd eeeeeee);
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@ -206,8 +445,7 @@ static void inst_fmath (const uint16_t ext)
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float128 source, result;
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if (src_in_ea) {
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source = _fpu_read_ea(M, source_specifier);
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if (shoe.abort)
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if (!_fpu_read_ea(source_specifier, &source))
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return ;
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}
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else
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@ -215,22 +453,328 @@ static void inst_fmath (const uint16_t ext)
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float128 dest = floatx80_to_float128(fpu->fp[dest_register]);
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/*
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* Thoughts on the meaning of the bits in the fmath opcode
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* Bits 6543210
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*
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* The 6th bit (Bxxxxx) is only implemented on 68040,
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* and it is only used to force the rounding mode.
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* If bit 6 is set, then bit 2 controls whether it rounds to
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* single or double. (Bit 2 is unchanged from the extended version
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* for single-rounding, and flipped for double-rounding)
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*
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* Wait no, this doesn't work for fsqrt.
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* Maybe the bits don't have any specific meaning...
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*/
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/*
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* We'll shrink the precision and perform rounding
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* just prior to writing back the result.
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* Certain instructions override the precision
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* in fpcr, so keep track of the prefered prec here.
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*/
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enum rounding_precision_t rounding_prec = mc_prec;
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/*
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* For all the intermediate calculations, we
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* probably want to use nearest-rounding mode.
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*/
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_set_rounding_mode(mode_nearest);
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/* Reset softfloat's exception flags */
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float_exception_flags = 0;
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/* Reset fpsr's exception flags */
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es_inex1 = 0; // this is only set for imprecisely-rounded packed inputs (not implemented)
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es_inex2 = 0; // set if we ever lose precision (during the op or during rounding)
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es_dz = 0; // set if we divided by zero
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es_unfl = 0; // set if we underflowed (inex2 should be set too, I think)
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es_ovfl = 0; // set if we overflowed (inex2 should be set too, I think)
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es_operr = 0; // ?
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es_snan = 0; // Set if one of the inputs was a signaling NaN
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es_bsun = 0; // never set here
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switch (e) {
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case ~b(1000000): // fsmove
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case ~b(1000100): // fdmove
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1000000)) rounding_prec = prec_single;
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else if (e == ~b(1000100)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0000000): // fmove
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result = source;
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break;
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case ~b(0000001): // fint
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break;
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case ~b(0000010): // fsinh
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break;
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case ~b(0000011): // fintrz
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break;
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case ~b(1000001): // fssqrt
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case ~b(1000101): // fdsqrt
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1000001)) rounding_prec = prec_single;
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else if (e == ~b(1000101)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0000100): // fsqrt;
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break;
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case ~b(0000110): // flognp1
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break;
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case ~b(0001000): // fetoxm1
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break;
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case ~b(0001001): // ftanh
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break;
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case ~b(0001010): // fatan
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break;
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case ~b(0001100): // fasin
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break;
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case ~b(0001101): // fatanh
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break;
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case ~b(0001110): // fsin
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break;
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case ~b(0001111): // ftan
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break;
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case ~b(0010000): // fetox
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break;
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case ~b(0010001): // ftwotox
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break;
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case ~b(0010010): // ftentox
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break;
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case ~b(0010100): // flogn
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break;
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case ~b(0010101): // flog10
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break;
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case ~b(0010110): // flog2
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break;
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case ~b(1011000): // fsabs
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case ~b(1011100): // fdabs
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1011000)) rounding_prec = prec_single;
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else if (e == ~b(1011100)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0011000): // fabs
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break;
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case ~b(0011001): // fcosh
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break;
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case ~b(1011010): // fsneg
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case ~b(1011110): // fdneg
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1011010)) rounding_prec = prec_single;
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else if (e == ~b(1011110)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0011010): // fneg
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break;
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case ~b(0011100): // facos
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break;
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case ~b(0011101): // fcos
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break;
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case ~b(0011110): // fgetexp
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break;
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case ~b(0011111): // fgetman
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break;
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case ~b(0100001): // fmod
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break;
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case ~b(1100010): // fsadd
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case ~b(1100110): // fdadd
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1100010)) rounding_prec = prec_single;
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else if (e == ~b(1100110)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0100010): // fadd
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break;
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case ~b(0100100): // fsgldiv
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break;
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case ~b(0100111): // fsglmul
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break;
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case ~b(0100101): // frem
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break;
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case ~b(0100110): // fscale
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break;
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case ~b(0111000): // fcmp
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break;
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case ~b(0111010): // ftst
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break;
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case ~b(1100000): // fsdiv
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case ~b(1100100): // fddiv
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1100000)) rounding_prec = prec_single;
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else if (e == ~b(1100100)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0100000): // fdiv
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break;
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case ~b(1100011): // fsmul
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case ~b(1100111): // fdmul
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1100011)) rounding_prec = prec_single;
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else if (e == ~b(1100111)) rounding_prec = prec_double;
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else assert(0);
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case ~b(0100011): // fmul
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break;
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case ~b(1101000): // fssub
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case ~b(1101100): // fdsub
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/* These are only legal on 68040 */
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throw_illegal_instruction();
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return ;
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if (e == ~b(1101000)) rounding_prec = prec_single;
|
||||
else if (e == ~b(1101100)) rounding_prec = prec_double;
|
||||
else assert(0);
|
||||
case ~b(0101000): // fsub
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Now update all the exception flags,
|
||||
* and determine whether we want to
|
||||
* actually throw an exception.
|
||||
*/
|
||||
|
||||
/*
|
||||
es_inex1 = 0;
|
||||
es_inex2 = 0;
|
||||
es_dz = 0;
|
||||
es_unfl = 0;
|
||||
es_ovfl = 0;
|
||||
es_operr = 0;
|
||||
es_snan = 0;
|
||||
es_bsun = 0;
|
||||
*/
|
||||
if (float_exception_flags & float_flag_divbyzero)
|
||||
es_dz = 1;
|
||||
if (float_exception_flags & float_flag_overflow)
|
||||
es_ovfl = 1;
|
||||
if (float_exception_flags & float_flag_underflow) {
|
||||
/* Wait... this might not be right */
|
||||
es_unfl = 1;
|
||||
es_inex2 = 1;
|
||||
}
|
||||
|
||||
/*
|
||||
Accrued -iff- exception
|
||||
|
||||
invalid bsun or snan or operr
|
||||
overflow overflow
|
||||
underflow (underflow AND inex2)
|
||||
divzero divzero
|
||||
inexact inex1 or inex2 or overflow
|
||||
*/
|
||||
|
||||
/*
|
||||
Exception -> Accrued
|
||||
|
||||
bsun -> invalid (can't happen here)
|
||||
snan -> invalid (we can check for this manually)
|
||||
operr -> invalid
|
||||
overflow -> overflow
|
||||
underflow...
|
||||
divzero -> divzero
|
||||
inex1 -> inexact
|
||||
inex2 -> inexact
|
||||
overflow -> inexact
|
||||
*/
|
||||
|
||||
/*
|
||||
bsun -> only set for f*cc* instructions
|
||||
snan -> was one of the operands a signaling NaN?
|
||||
operr ->
|
||||
overflow -> The result didn't fit, rounded to +/- infinity
|
||||
underflow-> The result didn't fit, rounded to +/- 0
|
||||
divzero -> divided by zero
|
||||
inex1 -> The input (packed) format was imprecisely converted
|
||||
inex2 -> The resulting output couldn't be precisely represented
|
||||
*/
|
||||
|
||||
// Presumably if overflow or underflow happen, inex2 must be set?
|
||||
// Underflow and overflow can't be set at the same time?
|
||||
|
||||
|
||||
assert(!"fmath");
|
||||
}
|
||||
|
||||
static void inst_fmove (const uint16_t ext)
|
||||
{
|
||||
fpu_get_state_ptr();
|
||||
|
||||
assert(!"fmove");
|
||||
}
|
||||
|
||||
static void inst_fmovem_control (const uint16_t ext)
|
||||
{
|
||||
fpu_get_state_ptr();
|
||||
|
||||
assert(!"fmovem_control");
|
||||
}
|
||||
|
||||
static void inst_fmovem (const uint16_t ext)
|
||||
{
|
||||
fpu_get_state_ptr();
|
||||
|
||||
assert(!"fmovem");
|
||||
}
|
||||
|
||||
|
|
@ -472,8 +1016,8 @@ void inst_ftrapcc () {
|
|||
}
|
||||
|
||||
void inst_fnop() {
|
||||
// This is technically fbcc, so we should set fpiar too
|
||||
fpu->fpiar = shoe.orig_pc;
|
||||
// This is technically fbcc
|
||||
inst_fbcc();
|
||||
}
|
||||
|
||||
void inst_fpu_other () {
|
||||
|
|
|
|||
Loading…
Reference in New Issue