1543 lines
46 KiB
C
1543 lines
46 KiB
C
/*
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* Copyright (c) 2013, Peter Rutenbar <pruten@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <assert.h>
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#include <stdlib.h>
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#include "../core/shoebill.h"
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/* --- Physical_get jump table --- */
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#pragma mark Physical_get jump table
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void _physical_get_ram (void)
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{
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uint64_t *addr;
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if slikely(shoe.physical_addr < shoe.physical_mem_size)
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addr = (uint64_t*)&shoe.physical_mem_base[shoe.physical_addr];
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else
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addr = (uint64_t*)&shoe.physical_mem_base[shoe.physical_addr % shoe.physical_mem_size];
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const uint8_t bits = (8 - shoe.physical_size) * 8;
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shoe.physical_dat = ntohll(*addr) >> bits;
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}
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void _physical_get_rom (void)
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{
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uint64_t *addr = (uint64_t*)&shoe.physical_rom_base[shoe.physical_addr & (shoe.physical_rom_size-1)];
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const uint8_t bits = (8 - shoe.physical_size) * 8;
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shoe.physical_dat = ntohll(*addr) >> bits;
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}
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void _physical_get_io (void)
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{
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switch (shoe.physical_addr & 0x5003ffff) {
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case 0x50000000 ... 0x50003fff: // VIA1 + VIA2
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via_read_raw();
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return ;
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case 0x50004000 ... 0x50005fff: {// SCC
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//slog("physical_get: got read to SCC\n");
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const uint32_t a = shoe.physical_addr & 0x1fff;
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if (a == 2 && shoe.physical_size==1)
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shoe.physical_dat = 0x4; // R0TXRDY
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return ;
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}
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case 0x50006000 ... 0x50007fff: // SCSI (pseudo-DMA with DRQ?)
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assert(shoe.logical_size == 4);
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shoe.physical_dat = scsi_dma_read_long();
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return ;
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case 0x50010000 ... 0x50011fff: // SCSI (normal mode?)
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scsi_reg_read();
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return ;
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case 0x50012000 ... 0x50013fff: // SCSI (pseudo-DMA with no DRQ?)
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assert(shoe.logical_size == 1);
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shoe.physical_dat = scsi_dma_read();
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return ;
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case 0x50014000 ... 0x50015fff: // Sound
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// slog("physical_get: got read to sound\n");
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shoe.physical_dat = sound_dma_read_raw(shoe.physical_addr & 0x1fff, shoe.physical_size);
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// slog("soundsound read : register 0x%04x sz=%u\n",
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//shoe.physical_addr - 0x50014000, shoe.physical_size);
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// shoe.physical_dat = 0;
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return ;
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case 0x50016000 ... 0x50017fff: // SWIM (IWM?)
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// slog("physical_get: got read to IWM\n");
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shoe.physical_dat = iwm_dma_read();
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return ;
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default:
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//slog("physical_get: got read to UNKNOWN IO ADDR %x\n", shoe.physical_addr);
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return ;
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}
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}
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void _physical_get_super_slot (void)
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{
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const uint32_t slot = shoe.physical_addr >> 28;
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if slikely(shoe.slots[slot].connected)
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shoe.physical_dat = shoe.slots[slot].read_func(shoe.physical_addr,
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shoe.physical_size,
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slot);
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else
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shoe.abort = 1; // throw a bus error for reads to disconnected slots
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// XXX: Do super slot accesses raise bus errors?
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}
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void _physical_get_standard_slot (void)
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{
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const uint32_t slot = (shoe.physical_addr >> 24) & 0xf;
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if slikely(shoe.slots[slot].connected)
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shoe.physical_dat = shoe.slots[slot].read_func(shoe.physical_addr,
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shoe.physical_size,
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slot);
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else
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shoe.abort = 1; // throw a bus error for reads to disconnected slots
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}
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const physical_get_ptr physical_get_jump_table[16] = {
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_physical_get_ram, // 0x0
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_physical_get_ram, // 0x1
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_physical_get_ram, // 0x2
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_physical_get_ram, // 0x3
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_physical_get_rom, // 0x4
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_physical_get_io, // 0x5
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_physical_get_super_slot, // 0x6
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_physical_get_super_slot, // 0x7
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_physical_get_super_slot, // 0x8
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_physical_get_super_slot, // 0x9
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_physical_get_super_slot, // 0xa
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_physical_get_super_slot, // 0xb
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_physical_get_super_slot, // 0xc
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_physical_get_super_slot, // 0xd
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_physical_get_super_slot, // 0xe
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_physical_get_standard_slot // 0xf
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};
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/* --- Physical_set jump table --- */
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#pragma mark Physical_set jump table
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void _physical_set_ram (void)
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{
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uint8_t *addr;
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if (shoe.physical_addr >= shoe.physical_mem_size)
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addr = &shoe.physical_mem_base[shoe.physical_addr % shoe.physical_mem_size];
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else
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addr = &shoe.physical_mem_base[shoe.physical_addr];
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if ((shoe.physical_addr >= 0x100) && (shoe.physical_addr < (0x8000))) {
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slog("LOMEM set: *0x%08x = 0x%x\n", shoe.physical_addr, (uint32_t)chop(shoe.physical_dat, shoe.physical_size));
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}
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const uint32_t sz = shoe.physical_size;
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switch (sz) {
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case 1:
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*addr = (uint8_t)shoe.physical_dat;
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return ;
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case 2:
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*((uint16_t*)addr) = htons((uint16_t)shoe.physical_dat);
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return ;
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case 4:
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*((uint32_t*)addr) = htonl((uint32_t)shoe.physical_dat);
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return ;
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case 8:
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*(uint64_t*)addr = ntohll(shoe.physical_dat);
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return ;
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default: {
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uint64_t q = shoe.physical_dat;
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uint8_t i;
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for (i=1; i<=sz; i++) {
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addr[sz-i] = (uint8_t)q;
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q >>= 8;
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}
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return ;
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}
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}
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}
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void _physical_set_rom (void)
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{
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// nothing happens when you try to modify ROM
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}
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void _physical_set_io (void)
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{
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switch (shoe.physical_addr & 0x5003ffff) {
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case 0x50000000 ... 0x50003fff: // VIA1 + VIA2
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via_write_raw();
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return ;
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case 0x50004000 ... 0x50005fff: // SCC
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//slog("physical_set: got write to SCC\n");
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return ;
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case 0x50006000 ... 0x50007fff: // SCSI (pseudo-DMA with DRQ?)
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assert(shoe.physical_size == 4);
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scsi_dma_write_long(shoe.physical_dat);
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return ;
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case 0x50010000 ... 0x50011fff: // SCSI (normal mode?)
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scsi_reg_write();
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return ;
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case 0x50012000 ... 0x50013fff: // SCSI (pseudo-DMA with no DRQ?)
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assert(shoe.physical_size == 1);
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scsi_dma_write(shoe.physical_dat);
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return ;
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case 0x50014000 ... 0x50015fff: // Sound
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sound_dma_write_raw(shoe.physical_addr & 0x1fff, shoe.physical_size, shoe.physical_dat);
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// slog("soundsound write: register 0x%04x sz=%u dat=0x%x\n",
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// shoe.physical_addr - 0x50014000, shoe.physical_size, (uint32_t)shoe.physical_dat);
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// slog("physical_set: got write to sound\n");
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return ;
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case 0x50016000 ... 0x50017fff: // SWIM (IWM?)
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//slog("physical_set: got write to IWM\n");
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iwm_dma_write();
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return ;
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default:
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//slog("physical_set: got write to UNKNOWN IO ADDR %x\n", shoe.physical_addr);
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return ;
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}
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}
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void _physical_set_super_slot (void)
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{
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const uint32_t slot = shoe.physical_addr >> 28;
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if (shoe.slots[slot].connected)
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shoe.slots[slot].write_func(shoe.physical_addr,
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shoe.physical_size,
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shoe.physical_dat,
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slot);
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}
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void _physical_set_standard_slot (void)
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{
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const uint32_t slot = (shoe.physical_addr >> 24) & 0xf;
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if (shoe.slots[slot].connected)
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shoe.slots[slot].write_func(shoe.physical_addr,
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shoe.physical_size,
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shoe.physical_dat,
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slot);
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}
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const physical_set_ptr physical_set_jump_table[16] = {
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_physical_set_ram, // 0x0
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_physical_set_ram, // 0x1
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_physical_set_ram, // 0x2
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_physical_set_ram, // 0x3
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_physical_set_rom, // 0x4
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_physical_set_io, // 0x5
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_physical_set_super_slot, // 0x6
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_physical_set_super_slot, // 0x7
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_physical_set_super_slot, // 0x8
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_physical_set_super_slot, // 0x9
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_physical_set_super_slot, // 0xa
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_physical_set_super_slot, // 0xb
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_physical_set_super_slot, // 0xc
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_physical_set_super_slot, // 0xd
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_physical_set_super_slot, // 0xe
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_physical_set_standard_slot // 0xf
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};
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/* --- PMMU logical address translation --- */
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#pragma mark PMMU logical address translation
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#define PMMU_CACHE_CRP 0
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#define PMMU_CACHE_SRP 1
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/*typedef struct {
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uint32_t logical_value : 24; // At most the high 24 bits of the logical address
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uint32_t used_bits : 5;
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uint32_t wp : 1; // whether the page is write protected
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uint32_t modified : 1; // whether the page has been modified
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uint32_t unused1 : 1;
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uint32_t unused2 : 8;
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uint32_t physical_addr : 24;
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} pmmu_cache_entry;
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struct {
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pmmu_cache_entry entry[512];
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uint8_t valid_map[512 / 8];
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} pmmu_cache[2];*/
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#define write_back_desc() { \
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if (desc_addr < 0) { \
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*rootp_ptr = desc; \
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} else { \
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pset((uint32_t)desc_addr, 4<<desc_size, desc); \
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} \
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}
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static _Bool check_pmmu_cache_write(void)
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{
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const _Bool use_srp = (shoe.tc_sre && (shoe.logical_fc >= 5));
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// logical addr [is]xxxxxxxxxxxx[ps] -> value xxxxxxxxxxxx
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const uint32_t value = (shoe.logical_addr << shoe.tc_is) >> shoe.tc_is_plus_ps;
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// value xxx[xxxxxxxxx] -> key xxxxxxxxx
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const uint32_t key = value & (PMMU_CACHE_SIZE - 1); // low PMMU_CACHE_KEY_BITS bits
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const pmmu_cache_entry_t entry = shoe.pmmu_cache[use_srp].entry[key];
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const _Bool is_set = (shoe.pmmu_cache[use_srp].valid_map[key >> 3] >> (key & 7)) & 1;
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const uint32_t ps_mask = 0xffffffff >> entry.used_bits;
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const uint32_t v_mask = ~~ps_mask;
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shoe.physical_addr = ((entry.physical_addr<<8) & v_mask) | (shoe.logical_addr & ps_mask);
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return is_set && (entry.logical_value == value) && entry.modified && !entry.wp;
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}
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static _Bool check_pmmu_cache_read(void)
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{
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const _Bool use_srp = (shoe.tc_sre && (shoe.logical_fc >= 5));
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// logical addr [is]xxxxxxxxxxxx[ps] -> value xxxxxxxxxxxx
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const uint32_t value = (shoe.logical_addr << shoe.tc_is) >> shoe.tc_is_plus_ps;
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// value xxx[xxxxxxxxx] -> key xxxxxxxxx
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const uint32_t key = value & (PMMU_CACHE_SIZE - 1); // low PMMU_CACHE_KEY_BITS bits
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const pmmu_cache_entry_t entry = shoe.pmmu_cache[use_srp].entry[key];
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const _Bool is_set = (shoe.pmmu_cache[use_srp].valid_map[key >> 3] >> (key & 7)) & 1;
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const uint32_t ps_mask = 0xffffffff >> entry.used_bits;
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const uint32_t v_mask = ~~ps_mask;
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shoe.physical_addr = ((entry.physical_addr<<8) & v_mask) | (shoe.logical_addr & ps_mask);
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return is_set && (entry.logical_value == value);
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}
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static void translate_logical_addr()
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{
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const uint8_t use_srp = (shoe.tc_sre && (shoe.logical_fc >= 5));
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assert((0x66 >> shoe.logical_fc) & 1); // we only support these FCs for now
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uint64_t *rootp_ptr = (use_srp ? (&shoe.srp) : (&shoe.crp));
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const uint64_t rootp = *rootp_ptr;
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uint8_t desc_did_change = 0;
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uint8_t desc_level = 0;
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int64_t desc_addr = -1; // address of the descriptor (-1 -> register)
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uint8_t wp = 0; // Whether any descriptor in the search has wp (write protected) set
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uint8_t i;
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uint64_t desc = rootp; // Initial descriptor is the root pointer descriptor
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uint8_t desc_size = 1; // And the root pointer descriptor is always 8 bytes (1==8 bytes, 0==4 bytes)
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uint8_t used_bits = shoe.tc_is; // Keep track of how many bits will be the effective "page size"
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// (If the table search terminates early (before used_bits == ts_ps()),
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// then (32 - used_bits) will be the effective page size. That is, the number of bits
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// we or into the physical addr from the virtual addr)
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desc_addr = -1; // address of the descriptor (-1 -> register)
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/* We'll keep shifting logical_addr such that its most significant bits are the next ti-index */
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uint32_t logical_addr = shoe.logical_addr << used_bits;
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// TODO: Check limit here
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// If root descriptor is invalid, throw a bus error
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if sunlikely(rp_dt(rootp) == 0) {
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throw_bus_error(shoe.logical_addr, shoe.logical_is_write);
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return ;
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}
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// desc is a page descriptor, skip right ahead to search_done:
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if (rp_dt(rootp) == 1)
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goto search_done;
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// for (i=0; i < 4; i++) { // (the condition is unnecessary - just leaving it in for clarity)
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for (i=0; 1; i++) {
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// desc must be a table descriptor here
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const uint8_t ti = tc_ti(i);
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used_bits += ti;
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// TODO: do the limit check here
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// Find the index into our current i-level table
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const uint32_t index = logical_addr >> (32-ti);
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logical_addr <<= ti;
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// load the child descriptor
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const uint32_t table_base_addr = desc_table_addr(desc);
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const uint8_t s = desc_dt(desc, desc_size) & 1;
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// desc = pget(table_base_addr + (4 << s)*index, (4 << s));
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get_desc(table_base_addr + (4 << s)*index, (4 << s));
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desc_size = s;
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// Desc may be a table descriptor, page descriptor, indirect descriptor, or invalid descriptor
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const uint8_t dt = desc_dt(desc, desc_size);
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// If this descriptor is invalid, throw a bus error
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if sunlikely(dt == 0) {
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throw_bus_error(shoe.logical_addr, shoe.logical_is_write);
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return ;
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}
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if (dt == 1) {
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// TODO: do a limit check here
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goto search_done; // it's a page descriptor
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}
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else if ((i==3) || (tc_ti(i+1)==0)) {
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desc_size = desc_dt(desc, s) & 1;
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/* Otherwise, if this is a leaf in the tree, it's an indirect descriptor.
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The size of the page descriptor is indicated by DT in the indirect descriptor. (or is it???) */
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//desc = pget(desc & 0xfffffff0, (4 << desc_size));
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get_desc(desc & 0xfffffff0, (4 << desc_size));
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// I think it's possible for an indirect descriptor to point to an invalid descriptor...
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if sunlikely(desc_dt(desc, desc_size) == 0) {
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throw_bus_error(shoe.logical_addr, shoe.logical_is_write);
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return ;
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}
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goto search_done;
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}
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// Now it must be a table descriptor
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// TODO: set the U (used) bit in this table descriptor
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wp |= desc_wp(desc, desc_size); // or in the wp flag for this table descriptor
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}
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// never get here
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assert(!"translate_logical_addr: never get here");
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search_done:
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// Desc must be a page descriptor
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// NOTE: The limit checks have been done already
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// (or would be, if they were implemented yet)
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// TODO: update U (used) bit
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wp |= desc_wp(desc, desc_size); // or in the wp flag for this page descriptor
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// And finally throw a bus error
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if sunlikely(wp && shoe.logical_is_write) {
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throw_bus_error(shoe.logical_addr, shoe.logical_is_write);
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return ;
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}
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// If we're writing, set the modified flag
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if (shoe.logical_is_write && !(desc & ( desc_size ? desc_m_long : desc_m_short ))) {
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desc |= ( desc_size ? desc_m_long : desc_m_short );
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write_back_desc();
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}
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const uint32_t ps_mask = 0xffffffff >> used_bits;
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const uint32_t v_mask = ~~ps_mask;
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|
|
const uint32_t paddr = (desc_page_addr(desc) & v_mask) | (shoe.logical_addr & ps_mask);
|
|
shoe.physical_addr = paddr;
|
|
|
|
|
|
/* --- insert this translation into pmmu_cache --- */
|
|
|
|
// logical addr [is]xxxxxxxxxxxx[ps] -> value xxxxxxxxxxxx
|
|
const uint32_t value = (shoe.logical_addr << shoe.tc_is) >> shoe.tc_is_plus_ps;
|
|
// value xxx[xxxxxxxxx] -> key xxxxxxxxx
|
|
const uint32_t key = value & (PMMU_CACHE_SIZE-1); // low PMMU_CACHE_KEY_BITS bits
|
|
|
|
pmmu_cache_entry_t entry;
|
|
shoe.pmmu_cache[use_srp].valid_map[key/8] |= (1 << (key & 7));
|
|
entry.logical_value = value;
|
|
entry.physical_addr = (desc_page_addr(desc)) >> 8;
|
|
entry.wp = wp;
|
|
entry.modified = desc_m(desc, desc_size);
|
|
entry.used_bits = used_bits;
|
|
shoe.pmmu_cache[use_srp].entry[key] = entry;
|
|
|
|
}
|
|
|
|
|
|
void logical_get (void)
|
|
{
|
|
|
|
// If address translation isn't enabled, this is a physical address
|
|
if sunlikely(!shoe.tc_enable) {
|
|
shoe.physical_addr = shoe.logical_addr;
|
|
shoe.physical_size = shoe.logical_size;
|
|
physical_get();
|
|
if sunlikely(shoe.abort) {
|
|
shoe.abort = 0;
|
|
throw_long_bus_error(shoe.logical_addr, 0);
|
|
return ;
|
|
}
|
|
shoe.logical_dat = shoe.physical_dat;
|
|
return ;
|
|
}
|
|
|
|
const uint32_t logical_size = shoe.logical_size;
|
|
const uint32_t logical_addr = shoe.logical_addr;
|
|
|
|
const uint32_t pagemask = shoe.tc_pagemask;
|
|
const uint32_t pageoffset = logical_addr & pagemask;
|
|
|
|
// Common case: the read is contained entirely within a page
|
|
if slikely(!((pageoffset + logical_size - 1) >> shoe.tc_ps)) {
|
|
if sunlikely(!check_pmmu_cache_read()) {
|
|
shoe.logical_is_write = 0;
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
return ;
|
|
}
|
|
|
|
if slikely(shoe.physical_addr < shoe.physical_mem_size) {
|
|
// Fast path
|
|
shoe.logical_dat = ntohll(*(uint64_t*)&shoe.physical_mem_base[shoe.physical_addr]) >> ((8-logical_size)*8);
|
|
}
|
|
else {
|
|
shoe.physical_size = logical_size;
|
|
physical_get();
|
|
if sunlikely(shoe.abort) {
|
|
shoe.abort = 0;
|
|
throw_long_bus_error(logical_addr, 0);
|
|
return ;
|
|
}
|
|
shoe.logical_dat = shoe.physical_dat;
|
|
}
|
|
}
|
|
else { // This read crosses a page boundary
|
|
const uint32_t addr_a = logical_addr;
|
|
const uint32_t size_b = (pageoffset + logical_size) & pagemask;
|
|
const uint32_t size_a = logical_size - size_b;
|
|
const uint32_t addr_b = addr_a + size_a;
|
|
|
|
shoe.logical_is_write = 0;
|
|
|
|
shoe.logical_addr = addr_a;
|
|
shoe.logical_size = size_a;
|
|
if sunlikely(!check_pmmu_cache_read()) {
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
return ;
|
|
}
|
|
|
|
const uint32_t p_addr_a = shoe.physical_addr;
|
|
|
|
shoe.logical_addr = addr_b;
|
|
shoe.logical_size = size_b;
|
|
if sunlikely(!check_pmmu_cache_read()) {
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
return ;
|
|
}
|
|
|
|
const uint32_t p_addr_b = shoe.physical_addr;
|
|
shoe.physical_size = size_b;
|
|
physical_get();
|
|
if sunlikely(shoe.abort) {
|
|
shoe.abort = 0;
|
|
throw_long_bus_error(shoe.logical_addr, 0);
|
|
return ;
|
|
}
|
|
const uint64_t fetch_b = shoe.physical_dat;
|
|
|
|
shoe.physical_addr = p_addr_a;
|
|
shoe.physical_size = size_a;
|
|
physical_get();
|
|
if sunlikely(shoe.abort) {
|
|
shoe.abort = 0;
|
|
throw_long_bus_error(shoe.logical_addr, 0);
|
|
return ;
|
|
}
|
|
|
|
shoe.logical_dat = (shoe.physical_dat << (size_b*8)) | fetch_b;
|
|
}
|
|
}
|
|
|
|
void logical_set (void)
|
|
{
|
|
// If address translation isn't enabled, this is a physical address
|
|
if sunlikely(!shoe.tc_enable) {
|
|
shoe.physical_addr = shoe.logical_addr;
|
|
shoe.physical_size = shoe.logical_size;
|
|
shoe.physical_dat = shoe.logical_dat;
|
|
physical_set();
|
|
return ;
|
|
}
|
|
|
|
const uint32_t logical_size = shoe.logical_size;
|
|
const uint32_t logical_addr = shoe.logical_addr;
|
|
|
|
const uint32_t pagemask = shoe.tc_pagemask;
|
|
const uint32_t pageoffset = logical_addr & pagemask;
|
|
|
|
// Make the translate function fail if the page is write-protected
|
|
shoe.logical_is_write = 1;
|
|
|
|
// Common case: this write is contained entirely in one page
|
|
if slikely(!((pageoffset + logical_size - 1) >> shoe.tc_ps)) {
|
|
// Common case: the write is contained entirely within a page
|
|
if sunlikely(!check_pmmu_cache_write()) {
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
return ;
|
|
}
|
|
|
|
shoe.physical_size = shoe.logical_size;
|
|
shoe.physical_dat = shoe.logical_dat;
|
|
physical_set();
|
|
}
|
|
else { // This write crosses a page boundary
|
|
const uint32_t addr_a = shoe.logical_addr;
|
|
const uint32_t size_b = (pageoffset + logical_size) & pagemask;
|
|
const uint32_t size_a = shoe.logical_size - size_b;
|
|
const uint32_t addr_b = addr_a + size_a;
|
|
const uint64_t data_a = shoe.logical_dat >> (size_b*8);
|
|
const uint64_t data_b = bitchop_64(shoe.logical_dat, size_b*8);
|
|
|
|
shoe.logical_addr = addr_a;
|
|
shoe.logical_size = size_a;
|
|
if sunlikely(!check_pmmu_cache_write()) {
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
return ;
|
|
}
|
|
const uint32_t p_addr_a = shoe.physical_addr;
|
|
|
|
shoe.logical_addr = addr_b;
|
|
shoe.logical_size = size_b;
|
|
if sunlikely(!check_pmmu_cache_write()) {
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
return ;
|
|
}
|
|
const uint32_t p_addr_b = shoe.physical_addr;
|
|
|
|
shoe.physical_addr = p_addr_a;
|
|
shoe.physical_size = size_a;
|
|
shoe.physical_dat = data_a;
|
|
physical_set();
|
|
|
|
shoe.physical_addr = p_addr_b;
|
|
shoe.physical_size = size_b;
|
|
shoe.physical_dat = data_b;
|
|
physical_set();
|
|
|
|
return ;
|
|
}
|
|
}
|
|
|
|
/* --- PC cache routines --- */
|
|
#pragma mark PC cache routines
|
|
|
|
static uint16_t pccache_miss(const uint32_t pc)
|
|
{
|
|
const uint32_t pagemask = shoe.tc_pagemask;
|
|
const uint32_t pageoffset = pc & pagemask;
|
|
uint32_t paddr;
|
|
|
|
/*
|
|
* I think the instruction decoder uses these
|
|
* these function codes:
|
|
* 6 -> supervisor program space,
|
|
* 2 -> user program space
|
|
*/
|
|
shoe.logical_fc = sr_s() ? 6 : 2;
|
|
shoe.logical_addr = pc;
|
|
if sunlikely(!check_pmmu_cache_read()) {
|
|
shoe.logical_is_write = 0;
|
|
translate_logical_addr();
|
|
if sunlikely(shoe.abort)
|
|
goto fail;
|
|
}
|
|
|
|
paddr = shoe.physical_addr ^ pageoffset;
|
|
|
|
shoe.pccache_use_srp = shoe.tc_sre && sr_s();
|
|
shoe.pccache_logical_page = pc ^ pageoffset;
|
|
|
|
if (paddr < 0x40000000) {
|
|
/* Address in RAM */
|
|
|
|
if sunlikely(paddr >= shoe.physical_mem_size)
|
|
paddr %= shoe.physical_mem_size;
|
|
|
|
shoe.pccache_ptr = &shoe.physical_mem_base[paddr];
|
|
return ntohs(*(uint16_t*)(shoe.pccache_ptr + pageoffset));
|
|
}
|
|
else if (paddr < 0x50000000) {
|
|
/* Address in ROM */
|
|
shoe.pccache_ptr = &shoe.physical_rom_base[paddr & (shoe.physical_rom_size - 1)];
|
|
return ntohs(*(uint16_t*)(shoe.pccache_ptr + pageoffset));
|
|
}
|
|
|
|
/*
|
|
* For now, only supporting reads from RAM and ROM.
|
|
* This could easily be supported by just calling
|
|
* physical_get() and leaving the cache invalid,
|
|
* but I don't think A/UX ever tries to execute outside
|
|
* RAM/ROM.
|
|
*/
|
|
assert(!"pccache_miss: neither RAM nor ROM!\n");
|
|
|
|
fail:
|
|
invalidate_pccache();
|
|
return 0;
|
|
}
|
|
|
|
uint16_t pccache_nextword(const uint32_t pc)
|
|
{
|
|
if (sunlikely(pc & 1))
|
|
goto odd_addr;
|
|
|
|
if slikely(shoe.tc_enable) {
|
|
const uint32_t pc_offset = pc & shoe.tc_pagemask;
|
|
const uint32_t pc_page = pc ^ pc_offset;
|
|
const uint32_t use_srp = shoe.tc_sre && sr_s();
|
|
|
|
/* If the cache exists and is valid */
|
|
if slikely((shoe.pccache_use_srp == use_srp) && (shoe.pccache_logical_page == pc_page)) {
|
|
// printf("pccache_nextword: hit: pc=%x\n", pc);
|
|
return ntohs(*(uint16_t*)(shoe.pccache_ptr + pc_offset));
|
|
}
|
|
// printf("pccache_nextword: miss: pc=%x\n", pc);
|
|
|
|
return pccache_miss(pc);
|
|
}
|
|
else {
|
|
uint32_t paddr = pc;
|
|
|
|
if (paddr < 0x40000000) {
|
|
/* Address in RAM */
|
|
|
|
if sunlikely(paddr >= shoe.physical_mem_size)
|
|
paddr %= shoe.physical_mem_size;
|
|
|
|
return ntohs(*(uint16_t*)(&shoe.physical_mem_base[paddr]));
|
|
}
|
|
else if (paddr < 0x50000000) {
|
|
/* Address in ROM */
|
|
|
|
return ntohs(*(uint16_t*)&shoe.physical_rom_base[paddr & (shoe.physical_rom_size - 1)]);
|
|
}
|
|
assert(!"!tc_enable: neither RAM nor RAM\n");
|
|
}
|
|
|
|
odd_addr:
|
|
assert(!"odd pc address!\n");
|
|
return 0;
|
|
}
|
|
|
|
uint32_t pccache_nextlong(const uint32_t pc)
|
|
{
|
|
if slikely(shoe.tc_enable) {
|
|
const uint32_t lastpage = shoe.pccache_logical_page;
|
|
const uint32_t pc_offset = pc & shoe.tc_pagemask;
|
|
const uint32_t pc_page = pc ^ pc_offset;
|
|
const uint32_t use_srp = shoe.tc_sre && sr_s();
|
|
|
|
|
|
/* If the cache exists, is valid, and the read is contained entirely within 1 page */
|
|
if slikely((shoe.pccache_use_srp == use_srp) && (lastpage == pc_page) && !((pc_offset + 3) >> shoe.tc_ps)) {
|
|
const uint32_t result = ntohl(*(uint32_t*)(shoe.pccache_ptr + pc_offset));
|
|
if (sunlikely(pc_offset & 1))
|
|
goto odd_addr;
|
|
return result;
|
|
}
|
|
|
|
const uint32_t result_high = pccache_nextword(pc) << 16;
|
|
if sunlikely(shoe.abort)
|
|
return 0;
|
|
|
|
return result_high | pccache_nextword(pc + 2);
|
|
}
|
|
else {
|
|
uint32_t paddr = pc;
|
|
|
|
if sunlikely(paddr & 1)
|
|
goto odd_addr;
|
|
|
|
if (paddr < 0x40000000) {
|
|
/* Address in RAM */
|
|
|
|
if sunlikely(paddr >= shoe.physical_mem_size)
|
|
paddr %= shoe.physical_mem_size;
|
|
|
|
return ntohl(*(uint32_t*)(&shoe.physical_mem_base[paddr]));
|
|
}
|
|
else if (paddr < 0x50000000) {
|
|
/* Address in ROM */
|
|
|
|
return ntohl(*(uint32_t*)&shoe.physical_rom_base[paddr & (shoe.physical_rom_size - 1)]);
|
|
}
|
|
assert(!"!tc_enable: neither RAM nor RAM\n");
|
|
}
|
|
|
|
odd_addr:
|
|
assert(!"odd pc address!\n");
|
|
return 0;
|
|
}
|
|
|
|
|
|
/* --- EA routines --- */
|
|
#pragma mark EA routines
|
|
|
|
#define nextword(pc) ({const uint16_t w = pccache_nextword(pc); if sunlikely(shoe.abort) return; (pc) += 2; w;})
|
|
#define nextlong(pc) ({const uint32_t L = pccache_nextlong(pc); if sunlikely(shoe.abort) return; (pc) += 4; L;})
|
|
|
|
// ea_decode_extended() - find the EA for those hiddeous 68020 addr modes
|
|
static void ea_decode_extended()
|
|
{
|
|
const uint32_t start_pc = shoe.pc; // the original PC
|
|
uint32_t mypc = start_pc; // our local PC (don't modify up the real PC)
|
|
const uint32_t ext_a = nextword(mypc); // the extension word
|
|
~decompose(ext_a, d rrr w ss F b i zz 0 III)
|
|
|
|
// d == index register type
|
|
// r == index register
|
|
// w == word/long-word index size
|
|
// s == scale factor
|
|
// F == extension word format (0==brief, 1==full)
|
|
// b == base register suppress
|
|
// i == index suppress
|
|
// z == base displacement size
|
|
// I == index/indirect selection
|
|
|
|
|
|
if (F == 0) { // If this is the brief extension word
|
|
// use the sign-extended least significant byte in the extension word
|
|
uint32_t base_disp = (int8_t)(ext_a & 0xff);
|
|
|
|
// load the base_address
|
|
uint32_t base_addr;
|
|
if (~bmatch(shoe.mr, 00xx1xxx)) { // consult the MR, use the PC?
|
|
base_addr = start_pc; // start at the beginning of the extension word
|
|
}
|
|
else { // otherwise, it's shoe.a[shoe.mr&7]
|
|
base_addr = shoe.a[shoe.mr&7];
|
|
}
|
|
|
|
// load the index value
|
|
uint32_t index_val;
|
|
if (w==0) { // use signed-extended lower word of the register
|
|
if (d==0) // shoe.d[]
|
|
index_val = (int16_t)(get_d(r, 2));
|
|
else // shoe.a[]
|
|
index_val = (int16_t)(get_a(r, 2));
|
|
} else { // use entire register
|
|
if (d==0) index_val = shoe.d[r];
|
|
else index_val = shoe.a[r];
|
|
}
|
|
// Scale the index value
|
|
index_val <<= s;
|
|
|
|
// the brief extension word is implicitly preindexed
|
|
shoe.extended_addr = base_addr + base_disp + index_val;
|
|
shoe.extended_len = mypc - start_pc;
|
|
//slog("I found address 0x%x\n", shoe.extended_addr);
|
|
return ;
|
|
}
|
|
else { // If this is a full extension word,
|
|
|
|
// first find the base address, which may be shoe.a[?] or shoe.pc
|
|
uint32_t base_addr = 0;
|
|
if (b == 0) { // only if it isn't suppressed
|
|
if (~bmatch(shoe.mr, 00xx1xxx)) { // consult the MR,
|
|
base_addr = start_pc; // start at the beginning of the extension word
|
|
}
|
|
else { // otherwise, it's shoe.a[shoe.mr&7]
|
|
base_addr = shoe.a[shoe.mr&7];
|
|
}
|
|
}
|
|
|
|
// Find the index value
|
|
uint32_t index_val = 0;
|
|
if (i == 0) { // only if it isn't suppressed
|
|
if (w==0) { // use signed-extended lower word of the register
|
|
if (d==0) // shoe.d[]
|
|
index_val = (int16_t)(get_d(r, 2));
|
|
else // shoe.a[]
|
|
index_val = (int16_t)(get_a(r, 2));
|
|
} else { // use entire register
|
|
if (d==0) index_val = shoe.d[r];
|
|
else index_val = shoe.a[r];
|
|
}
|
|
// Scale the index value
|
|
index_val <<= s;
|
|
}
|
|
|
|
// Find the base displacement
|
|
uint32_t base_disp = 0;
|
|
// ... but only if the size is > null
|
|
if (z > 1) {
|
|
if (z == 2) { // if word-length, fetch nextword() and sign-extend
|
|
base_disp = (int16_t)(nextword(mypc));
|
|
} else { // otherwise, it's a longword
|
|
base_disp = nextlong(mypc);
|
|
}
|
|
}
|
|
|
|
// Find the outer displacement
|
|
uint32_t outer_disp = 0;
|
|
// based on the I/IS behavior
|
|
switch ((i<<3)|I) {
|
|
case ~b(0010): case ~b(0110): case ~b(1010):
|
|
// sign-extended word-length outer displacement
|
|
outer_disp = (int16_t)nextword(mypc);
|
|
break;
|
|
case ~b(0011): case ~b(0111): case ~b(1011): {
|
|
// long word outer displacement
|
|
outer_disp = nextlong(mypc);
|
|
break ;
|
|
}
|
|
}
|
|
|
|
//slog("D/A=%u, reg=%u, W/L=%u, Scale=%u, F=%u, BS=%u, IS=%u, BDSize=%u, I/IS=%u\n",
|
|
//d, r, w, s, F, b, i, z, I);
|
|
//slog("base_addr=%x, index_val=%x, base_disp=%x, outer_disp=%x\n",
|
|
//base_addr, index_val, base_disp, outer_disp);
|
|
|
|
// Now mash all these numbers together to get an EA
|
|
switch ((i<<3)|I) {
|
|
case ~b(0001): case ~b(0010): case ~b(0011):
|
|
case ~b(1001): case ~b(1010): case ~b(1011): {
|
|
// Indirect preindexed
|
|
const uint32_t intermediate = lget(base_addr + base_disp + index_val, 4);
|
|
if sunlikely(shoe.abort) return ;
|
|
shoe.extended_addr = intermediate + outer_disp;
|
|
shoe.extended_len = mypc - start_pc;
|
|
// slog("addr=0x%x len=%u\n", shoe.extended_addr, shoe.extended_len);
|
|
return ;
|
|
}
|
|
|
|
case ~b(0101): case ~b(0110): case ~b(0111): {
|
|
// Indirect postindexed
|
|
const uint32_t intermediate = lget(base_addr + base_disp, 4);
|
|
if sunlikely(shoe.abort) return ;
|
|
shoe.extended_addr = intermediate + index_val + outer_disp;
|
|
shoe.extended_len = mypc - start_pc;
|
|
return ;
|
|
}
|
|
|
|
case ~b(1000): case ~b(0000): {
|
|
// No memory indirect action
|
|
// EA = base_addr + base_disp + index
|
|
shoe.extended_addr = base_addr + base_disp + index_val;
|
|
shoe.extended_len = mypc - start_pc;
|
|
return ;
|
|
}
|
|
default:
|
|
assert(!"ea_decode_extended: oh noes! invalid I/IS!\n");
|
|
// I think that 68040 *doesn't* throw an exception here...
|
|
// FIXME: figure out what actually happens here
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
// Data register direct mode
|
|
void _ea_000_read (void)
|
|
{
|
|
shoe.dat = get_d(shoe.mr & 7, shoe.sz);
|
|
}
|
|
void _ea_000_write (void)
|
|
{
|
|
set_d(shoe.mr & 7, shoe.dat, shoe.sz);
|
|
}
|
|
|
|
|
|
// address register direct mode
|
|
void _ea_001_read (void)
|
|
{
|
|
shoe.dat = get_a(shoe.mr & 7, shoe.sz);
|
|
}
|
|
void _ea_001_write (void)
|
|
{
|
|
assert(shoe.sz==4);
|
|
shoe.a[shoe.mr & 7] = shoe.dat;
|
|
}
|
|
|
|
|
|
// address register indirect mode
|
|
void _ea_010_read (void)
|
|
{
|
|
shoe.dat = lget(shoe.a[shoe.mr & 7], shoe.sz);
|
|
}
|
|
void _ea_010_write (void)
|
|
{
|
|
lset(shoe.a[shoe.mr & 7], shoe.sz, shoe.dat);
|
|
}
|
|
void _ea_010_addr (void)
|
|
{
|
|
shoe.dat = shoe.a[shoe.mr & 7];
|
|
}
|
|
|
|
|
|
// address register indirect with postincrement mode
|
|
void _ea_011_read (void)
|
|
{
|
|
shoe.dat = lget(shoe.a[shoe.mr & 7], shoe.sz);
|
|
}
|
|
void _ea_011_read_commit (void)
|
|
{
|
|
const uint8_t reg = shoe.mr & 7;
|
|
shoe.a[reg] += (((reg==7) && (shoe.sz==1)) ? 2 : shoe.sz);
|
|
}
|
|
void _ea_011_write (void)
|
|
{
|
|
const uint8_t reg = shoe.mr & 7;
|
|
const uint8_t delta = ((reg==7) && (shoe.sz==1)) ? 2 : shoe.sz;
|
|
|
|
lset(shoe.a[reg], shoe.sz, shoe.dat);
|
|
if slikely(!shoe.abort)
|
|
shoe.a[reg] += delta;
|
|
}
|
|
|
|
|
|
// address register indirect with predecrement mode
|
|
void _ea_100_read (void)
|
|
{
|
|
const uint8_t reg = shoe.mr & 7;
|
|
const uint8_t delta = ((reg==7) && (shoe.sz==1))?2:shoe.sz;
|
|
shoe.dat = lget(shoe.a[reg]-delta, shoe.sz);
|
|
}
|
|
void _ea_100_read_commit (void)
|
|
{
|
|
const uint8_t reg = shoe.mr & 7;
|
|
shoe.a[reg] -= (((reg==7) && (shoe.sz==1)) ? 2 : shoe.sz);
|
|
}
|
|
void _ea_100_write (void)
|
|
{
|
|
const uint8_t reg = shoe.mr & 7;
|
|
const uint8_t delta = ((reg==7) && (shoe.sz==1)) ? 2 : shoe.sz;
|
|
|
|
lset(shoe.a[reg] - delta, shoe.sz, shoe.dat);
|
|
if slikely(!shoe.abort)
|
|
shoe.a[reg] -= delta;
|
|
}
|
|
|
|
|
|
// address register indirect with displacement mode
|
|
void _ea_101_read (void)
|
|
{
|
|
shoe.uncommitted_ea_read_pc = shoe.pc;
|
|
const int16_t disp = nextword(shoe.uncommitted_ea_read_pc);
|
|
shoe.dat = lget(shoe.a[shoe.mr & 7] + disp, shoe.sz);
|
|
}
|
|
void _ea_101_read_commit (void)
|
|
{
|
|
shoe.pc += 2;
|
|
}
|
|
void _ea_101_write (void)
|
|
{
|
|
const int16_t disp = nextword(shoe.pc);
|
|
lset(shoe.a[shoe.mr & 7] + disp, shoe.sz, shoe.dat);
|
|
}
|
|
void _ea_101_addr (void)
|
|
{
|
|
const int16_t disp = nextword(shoe.pc);
|
|
shoe.dat = shoe.a[shoe.mr & 7] + disp;
|
|
}
|
|
|
|
|
|
// memory/address register indirect with index
|
|
void _ea_110_read (void)
|
|
{
|
|
ea_decode_extended();
|
|
if slikely(!shoe.abort)
|
|
shoe.dat = lget(shoe.extended_addr, shoe.sz);
|
|
shoe.uncommitted_ea_read_pc = shoe.pc + shoe.extended_len;
|
|
}
|
|
void _ea_110_read_commit (void)
|
|
{
|
|
shoe.pc = shoe.uncommitted_ea_read_pc;
|
|
}
|
|
void _ea_110_write (void)
|
|
{
|
|
ea_decode_extended();
|
|
if slikely(!shoe.abort) {
|
|
lset(shoe.extended_addr, shoe.sz, shoe.dat);
|
|
if slikely(!shoe.abort)
|
|
shoe.pc += shoe.extended_len;
|
|
}
|
|
}
|
|
void _ea_110_addr (void)
|
|
{
|
|
ea_decode_extended();
|
|
if slikely(!shoe.abort) {
|
|
shoe.dat = shoe.extended_addr;
|
|
shoe.pc += shoe.extended_len;
|
|
}
|
|
}
|
|
|
|
|
|
// absolute short addressing mode
|
|
void _ea_111_000_read (void)
|
|
{
|
|
shoe.uncommitted_ea_read_pc = shoe.pc;
|
|
const int32_t addr = (int16_t)nextword(shoe.uncommitted_ea_read_pc);
|
|
shoe.dat = lget((uint32_t)addr, shoe.sz);
|
|
}
|
|
void _ea_111_000_read_commit (void)
|
|
{
|
|
shoe.pc += 2;
|
|
}
|
|
void _ea_111_000_write (void)
|
|
{
|
|
const int32_t addr = (int16_t)nextword(shoe.pc);
|
|
lset((uint32_t)addr, shoe.sz, shoe.dat);
|
|
}
|
|
void _ea_111_000_addr (void)
|
|
{
|
|
const int32_t addr = (int16_t)nextword(shoe.pc);
|
|
shoe.dat = (uint32_t)addr;
|
|
}
|
|
|
|
|
|
// absolute long addressing mode
|
|
void _ea_111_001_read (void)
|
|
{
|
|
shoe.uncommitted_ea_read_pc = shoe.pc;
|
|
const uint32_t addr = nextlong(shoe.uncommitted_ea_read_pc);
|
|
shoe.dat = lget(addr, shoe.sz);
|
|
}
|
|
void _ea_111_001_read_commit (void)
|
|
{
|
|
shoe.pc += 4;
|
|
}
|
|
void _ea_111_001_write (void)
|
|
{
|
|
const uint32_t addr = nextlong(shoe.pc);
|
|
lset(addr, shoe.sz, shoe.dat);
|
|
}
|
|
void _ea_111_001_addr (void)
|
|
{
|
|
const uint32_t addr = nextlong(shoe.pc);
|
|
shoe.dat = addr;
|
|
}
|
|
|
|
// program counter indirect with displacement mode
|
|
void _ea_111_010_read (void)
|
|
{
|
|
const uint32_t base_pc = shoe.pc;
|
|
shoe.uncommitted_ea_read_pc = base_pc;
|
|
const int16_t disp = nextword(shoe.uncommitted_ea_read_pc);
|
|
shoe.dat = lget(base_pc + disp, shoe.sz);
|
|
}
|
|
void _ea_111_010_read_commit (void)
|
|
{
|
|
shoe.pc += 2;
|
|
}
|
|
void _ea_111_010_addr (void)
|
|
{
|
|
const uint32_t oldpc = shoe.pc;
|
|
const int16_t displacement = nextword(shoe.pc);
|
|
shoe.dat = oldpc + displacement;
|
|
}
|
|
|
|
|
|
// (program counter ...)
|
|
void _ea_111_011_read (void)
|
|
{
|
|
ea_decode_extended();
|
|
if slikely(!shoe.abort)
|
|
shoe.dat = lget(shoe.extended_addr, shoe.sz);
|
|
shoe.uncommitted_ea_read_pc = shoe.pc + shoe.extended_len;
|
|
}
|
|
void _ea_111_011_read_commit (void)
|
|
{
|
|
shoe.pc = shoe.uncommitted_ea_read_pc;
|
|
}
|
|
void _ea_111_011_addr (void)
|
|
{
|
|
ea_decode_extended();
|
|
if slikely(!shoe.abort) {
|
|
shoe.dat = shoe.extended_addr;
|
|
shoe.pc += shoe.extended_len;
|
|
}
|
|
}
|
|
|
|
|
|
// immediate data
|
|
void _ea_111_100_read (void)
|
|
{
|
|
if (shoe.sz == 1) {
|
|
shoe.uncommitted_ea_read_pc = shoe.pc + 2;
|
|
shoe.dat = lget(shoe.pc, 2) & 0xff;
|
|
}
|
|
else {
|
|
shoe.uncommitted_ea_read_pc = shoe.pc + shoe.sz;
|
|
shoe.dat = lget(shoe.pc, shoe.sz);
|
|
}
|
|
}
|
|
void _ea_111_100_read_commit (void)
|
|
{
|
|
shoe.pc = shoe.uncommitted_ea_read_pc;
|
|
}
|
|
|
|
|
|
// illegal EA mode
|
|
void _ea_illegal (void)
|
|
{
|
|
throw_illegal_instruction();
|
|
}
|
|
|
|
// nothing to do
|
|
void _ea_nop (void)
|
|
{
|
|
}
|
|
|
|
|
|
const _ea_func ea_read_jump_table[64] = {
|
|
// Data register direct mode
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
_ea_000_read,
|
|
// address register direct mode
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
_ea_001_read,
|
|
// address register indirect mode
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
_ea_010_read,
|
|
// address register indirect with postincrement mode
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
_ea_011_read,
|
|
// address register indirect with predecrement mode
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
_ea_100_read,
|
|
// address register indirect with displacement mode
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
_ea_101_read,
|
|
// memory/address register indirect with index
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
_ea_110_read,
|
|
// absolute short addressing mode
|
|
_ea_111_000_read,
|
|
// absolute long addressing mode
|
|
_ea_111_001_read,
|
|
// program counter indirect with displacement mode
|
|
_ea_111_010_read,
|
|
// program counter indirect with index
|
|
_ea_111_011_read,
|
|
// immediate
|
|
_ea_111_100_read,
|
|
// The rest are illegal EA modes
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal
|
|
};
|
|
|
|
const _ea_func ea_read_commit_jump_table[64] = {
|
|
// Data register direct mode
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
// address register direct mode
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
// address register indirect mode
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
_ea_nop,
|
|
// address register indirect with postincrement mode
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
_ea_011_read_commit,
|
|
// address register indirect with predecrement mode
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
_ea_100_read_commit,
|
|
// address register indirect with displacement mode
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
_ea_101_read_commit,
|
|
// memory/address register indirect with index
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
_ea_110_read_commit,
|
|
// absolute short addressing mode
|
|
_ea_111_000_read_commit,
|
|
// absolute long addressing mode
|
|
_ea_111_001_read_commit,
|
|
// program counter indirect with displacement mode
|
|
_ea_111_010_read_commit,
|
|
// program counter indirect with index
|
|
_ea_111_011_read_commit,
|
|
// immediate
|
|
_ea_111_100_read_commit,
|
|
// The rest are illegal EA modes
|
|
NULL,
|
|
NULL,
|
|
NULL
|
|
};
|
|
|
|
const _ea_func ea_write_jump_table[64] = {
|
|
// Data register direct mode
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
_ea_000_write,
|
|
// address register direct mode
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
_ea_001_write,
|
|
// address register indirect mode
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
_ea_010_write,
|
|
// address register indirect with postincrement mode
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
_ea_011_write,
|
|
// address register indirect with predecrement mode
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
_ea_100_write,
|
|
// address register indirect with displacement mode
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
_ea_101_write,
|
|
// memory/address register indirect with index
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
_ea_110_write,
|
|
// absolute short addressing mode
|
|
_ea_111_000_write,
|
|
// absolute long addressing mode
|
|
_ea_111_001_write,
|
|
// program counter indirect with displacement mode
|
|
_ea_illegal,
|
|
// program counter indirect with index
|
|
_ea_illegal,
|
|
// immediate
|
|
_ea_illegal,
|
|
// The rest are illegal EA modes
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal
|
|
};
|
|
|
|
|
|
const _ea_func ea_addr_jump_table[64] = {
|
|
// Data register direct mode
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
// address register direct mode
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
// address register indirect mode
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
_ea_010_addr,
|
|
// address register indirect with postincrement mode
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
// address register indirect with predecrement mode
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
// address register indirect with displacement mode
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
_ea_101_addr,
|
|
// memory/address register indirect with index
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
_ea_110_addr,
|
|
// absolute short addressing mode
|
|
_ea_111_000_addr,
|
|
// absolute long addressing mode
|
|
_ea_111_001_addr,
|
|
// program counter indirect with displacement mode
|
|
_ea_111_010_addr,
|
|
// program counter indirect with index
|
|
_ea_111_011_addr,
|
|
// immediate
|
|
_ea_illegal,
|
|
// The rest are illegal EA modes
|
|
_ea_illegal,
|
|
_ea_illegal,
|
|
_ea_illegal
|
|
};
|
|
|
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|