280 lines
9.1 KiB
C
280 lines
9.1 KiB
C
/*
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* Copyright (c) 2014, Peter Rutenbar <pruten@gmail.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Props to MESS for their EASC register map: http://www.mess.org/mess/driver_info/easc
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* EASC's PCM mode is backwards compatible with ASC, so their registers are very similar.
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*/
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#include <assert.h>
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#include <string.h>
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#include "../core/shoebill.h"
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#define r_ptr (0x400 + (asc->right_ptr & 0x3ff)) /* right buf ptr */
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#define l_ptr (asc->left_ptr & 0x3ff) /* left buf ptr */
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#define m_ptr (asc->left_ptr & 0x7ff) /* mono buf ptr */
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void init_asc_state(void)
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{
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memset(&shoe.asc, 0, sizeof(shoe.asc));
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shoe.asc.version = 0x00; // My Mac II's ASC reports 0x00 as its version.
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// From the ROM, it looks like other Mac II ASC masks have different version numbers
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}
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static uint8_t sound_dma_read_byte(uint16_t addr)
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{
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apple_sound_chip_registers_t *asc = &shoe.asc;
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if (addr < 0x800) {
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if (asc->asc_mode == 1) {
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// PCM mode (FIFO is append-only)
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if (asc->channel_ctrl & 2) {
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// stereo mode - return the byte referenced by the right pointer
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return asc->buf[r_ptr];
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}
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else {
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// mono mode - return the byte referenced by the left pointer
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return asc->buf[m_ptr];
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}
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}
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else {
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// Off or wavetable mode (FIFO is random access)
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return asc->buf[addr];
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}
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}
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switch (addr) {
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case 0x800: // Version
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return asc->version;
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case 0x801: // ASC-mode
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return asc->asc_mode;
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case 0x802: // Channel control
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return asc->channel_ctrl;
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case 0x803: // FIFO control
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return asc->fifo_ctrl;
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case 0x804: // FIFO interrupt
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//return asc->fifo_intr;
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return 0xff;
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case 0x805: // Unknown (??)
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return asc->unknown1;
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case 0x806: // Volume control
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return asc->volume_ctrl;
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case 0x807: // Clock control
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return asc->clock_ctrl;
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}
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return 0;
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}
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static void sound_dma_write_byte(uint16_t addr, uint8_t data)
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{
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apple_sound_chip_registers_t *asc = &shoe.asc;
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if (addr < 0x800) { // buf_a/b
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if (asc->asc_mode == 1) {
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// PCM mode (FIFO is append-only)
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if (asc->channel_ctrl & 2) {
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// stereo mode - each channel has its own buffer pointer
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if (addr < 0x400) {
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// left buffer
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asc->buf[l_ptr] = data;
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asc->left_ptr++;
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}
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else {
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// right buffer
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asc->buf[r_ptr] = data;
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asc->right_ptr++;
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}
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return ;
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}
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else {
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// Mono mode
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asc->buf[m_ptr] = data;
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asc->left_ptr++;
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return ;
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}
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}
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else {
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// Off or wavetable mode (FIFO is random access)
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asc->buf[addr] = data;
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return ;
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}
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}
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else {
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switch (addr) {
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case 0x800: // Version
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// Version is read-only
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break;
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case 0x801: // ASC-mode
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// ASC version 0x00 preserves the low 2 bits
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asc->asc_mode = data & 0x03;
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assert(asc->asc_mode != 3); // mode-3 produces noise, but isn't deterministic
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break;
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case 0x802: // Channel control
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// ASC version 0x00 preserves the high bit and low 2 bits
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asc->channel_ctrl = data & 0x83;
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break;
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case 0x803: // FIFO control
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// ASC version 0x00 preserves the low 2 bits
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asc->fifo_ctrl = data & 0x83;
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break;
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case 0x804: // FIFO interrupt
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// FIFO interrupt is read-only
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break;
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case 0x805: // unknown (???)
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// ASC version 0x00 preserves the high bit and low 4 bits
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// (But what does it do?)
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asc->unknown1 = data & 0x8f;
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break;
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case 0x806: // Volume control
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// ASC version 0x00 preserves the high 6 bits
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asc->volume_ctrl = data & 0xfc;
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break;
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case 0x807: // Clock control
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// ASC version 0x00 preserves the low 2 bits
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asc->clock_ctrl = data & 0x03;
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break;
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}
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}
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}
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void sound_dma_write_raw(uint16_t addr, uint8_t sz, uint32_t data)
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{
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int32_t i;
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slog("sound_dma_write: addr=0x%04x sz=%u dat=0x%x\n", addr, sz, data);
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for (i = (sz-1) * 8; i >= 0; i -= 8)
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sound_dma_write_byte(addr, (data >> i) & 0xff);
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}
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uint32_t sound_dma_read_raw(uint16_t addr, uint8_t sz)
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{
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uint32_t i, result = 0;
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slog("sound_dma_read: addr=0x%04x sz=%u\n", addr, sz);
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for (i=0; i<sz; i++) {
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result <<= 8;
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result |= sound_dma_read_byte(addr + i);
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}
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return result;
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}
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/*
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ASC notes:
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buf_a (0x000-0x3ff) -> left
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buf_b (0x400-0x7ff) -> right
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writing to any address in buf_a or buf_b appends to the end pointer in the ring buffer (ignoring the address)
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reading from any address returns... the currently-being-read byte? Or the about-to-be-overwritten byte?
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(def one or the other)
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- Update: MODE=0: You can do regular random read/write access to buf_a/b when MODE=0.
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MODE=1: Writing anywhere within the buffer automatically appends to the end of the ring buffer
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For stereo mode, writing between 0-0x3ff appends to buf_a, 0x400-0x7ff to buf_b
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Reading anywhere in the buffer is strange - it seems non-deterministic.
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Update 2: no wait, it's returning the byte at buf_b's ring pointer, does it always do that?
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Update 3: yes, it looks like reading anywhere returns the byte at buf_b's pointer in stereo mode,
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and buf_a's pointer in mono mode
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MODE=2: Same as MODE=0 (?)
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- ASC maintains two distinct ring buffer pointers for stereo mode
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0x800 - Version (?) MacII only ever seems to TST.B it
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(READ ONLY)
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$00 -> My Mac II's ASC's version
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$?? -> Mac II's ROM is aware of other non-$00 ASC masks
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$b0 -> EASC
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————
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0x801 - Mode (?) 0 == no output, 1 == PCM, 2 == wavetable, 3 == hissing static(??)
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- Preserves low 2 bits, ignores high 6 bits
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0x802 - Channel selector
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Preserves mask 0x83 (high bit, low 2 bits)
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- High bit is set if “engine overflow” (according to MESS)
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- Low bits, 0x?2 -> stereo output (buf_a -> left, buf_b -> right)
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0x?0 -> Mono output (from buf_a)
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- Switching to stereo from mono produces a blip of sound in the right ear, unless the fifo has been cleared (buf_b), (or unless there was nothing in buf_b to start with)
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0x803 - Fifo control (cycle 0x80 to reset the internal FIFO pointer (pointers?))
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Preserves mask 0x83 (high bit, low 2 bits)
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0x804 - Fifo interrupt status
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(READ ONLY, doesn’t preserve any written bits (doesn’t acknowledge writes at all?))
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0x805 - ???
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- Preserves bits at 0x8F, (high bit, low 4 bits), doesn't seem to do anything
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0x806 - Volume control (high 3 bits)
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Preserves top 6 bits, ignores bottom 2 bits. (Only top 3 bits control volume)
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0x807 - Clock rate select (0, 2, or 3, I think)
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0x00 -> 11127hz
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0x01 -> Illegal???
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0x02 -> 11025hz
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0x03 -> 22050hz
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Writes to fifo_a/b(?) seem to block for clock rates 0, 2, and 3, but not 1. The speaker clicks like the sound chip is turning off when you set clock to 0x01.
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ASC has more registers past 0x807 for wave table control
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*/
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