From 125f6d91e18e64e16fb3190719199490db9991cd Mon Sep 17 00:00:00 2001 From: freitz85 Date: Sat, 6 May 2017 17:31:51 +0200 Subject: [PATCH] files added --- .gitignore | 71 +- SPI6502B.cel | 0 SPI6502B.lfp | 40 + SPI6502B.ucf | 43 + SPI6502B.ucf.untf | 0 SPI6502B1.1.vhd | 367 ++++ _ngo/netlist.lst | 2 + _pace.ucf | 41 + spi65.cdf | 16 + spi65.dhp | 3 + spi65.npl | 26 + spi6502b._hrpt | 1 + spi6502b.bld | 23 + spi6502b.gyd | 58 + spi6502b.imp | 1 + spi6502b.jed | 1666 ++++++++++++++++++ spi6502b.mfd | 843 +++++++++ spi6502b.ngc | 3 + spi6502b.ngd | 3 + spi6502b.ngr | 3 + spi6502b.pnx | 18 + spi6502b.prj | 1 + spi6502b.rpt | 873 ++++++++++ spi6502b.syr | 215 +++ spi6502b.vm6 | 4095 ++++++++++++++++++++++++++++++++++++++++++++ spi6502b.xml | 3 + spi6502b_build.xml | 205 +++ spi6502b_pad.csv | 73 + tmperr.err | 0 userlang.tpl | 6 + 30 files changed, 8669 insertions(+), 30 deletions(-) create mode 100644 SPI6502B.cel create mode 100644 SPI6502B.lfp create mode 100644 SPI6502B.ucf create mode 100644 SPI6502B.ucf.untf create mode 100644 SPI6502B1.1.vhd create mode 100644 _ngo/netlist.lst create mode 100644 _pace.ucf create mode 100644 spi65.cdf create mode 100644 spi65.dhp create mode 100644 spi65.npl create mode 100644 spi6502b._hrpt create mode 100644 spi6502b.bld create mode 100644 spi6502b.gyd create mode 100644 spi6502b.imp create mode 100644 spi6502b.jed create mode 100644 spi6502b.mfd create mode 100644 spi6502b.ngc create mode 100644 spi6502b.ngd create mode 100644 spi6502b.ngr create mode 100644 spi6502b.pnx create mode 100644 spi6502b.prj create mode 100644 spi6502b.rpt create mode 100644 spi6502b.syr create mode 100644 spi6502b.vm6 create mode 100644 spi6502b.xml create mode 100644 spi6502b_build.xml create mode 100644 spi6502b_pad.csv create mode 100644 tmperr.err create mode 100644 userlang.tpl diff --git a/.gitignore b/.gitignore index f805e81..aa04e65 100644 --- a/.gitignore +++ b/.gitignore @@ -1,33 +1,44 @@ -# Object files -*.o -*.ko -*.obj +#Gitignore for files generated by Xilinx ISE + +*.log +*.svf +*.scr +*.cmd +*.bak +*.lso *.elf - -# Precompiled Headers -*.gch -*.pch - -# Libraries -*.lib -*.a -*.la -*.lo - -# Shared objects (inc. Windows DLLs) -*.dll -*.so -*.so.* -*.dylib - -# Executables +*.ace +*~ +*# +*.swp +*.ini +*.html +*.vhi +*.wdb +*.stx +*.xmsgs +*.xreport *.exe -*.out -*.app -*.i*86 -*.x86_64 -*.hex +*.cmd_log +*_beh.prj +*.ncd +isim +db +incremental_db +work +*.cr.mti +vsim.wlf +transcript +webtalk.log +webtalk_impact.xml +pepExtractor.prj +impact.xsl +impact_impact.xwbt -# Debug files -*.dSYM/ -*.su +spi6502b_html*/ +__projnav*/ + +#ignore OS noise + +Thumbs.db +.DS_Store diff --git a/SPI6502B.cel b/SPI6502B.cel new file mode 100644 index 0000000..e69de29 diff --git a/SPI6502B.lfp b/SPI6502B.lfp new file mode 100644 index 0000000..8cce84c --- /dev/null +++ b/SPI6502B.lfp @@ -0,0 +1,40 @@ +# begin LFP file C:\sources\spi65\SPI6502B.lfp +designfile spi6502b.ngd +IO_GROUP "spi_Nsel" ; +IO_GROUP "spi_miso" ; +IO_GROUP "spi_int" ; +IO_GROUP "cpu_d" ; +IO_GROUP "cpu_a" ; +NET "spi_sclk" COLOR=6 ; +NET "spi_Nsel<3>" COLOR=6 IO_GROUP="spi_Nsel" ; +NET "spi_Nsel<2>" COLOR=6 IO_GROUP="spi_Nsel" ; +NET "spi_Nsel<1>" COLOR=6 IO_GROUP="spi_Nsel" ; +NET "spi_Nsel<0>" COLOR=6 IO_GROUP="spi_Nsel" ; +NET "spi_mosi" COLOR=6 ; +NET "spi_miso<3>" COLOR=6 IO_GROUP="spi_miso" ; +NET "spi_miso<2>" COLOR=6 IO_GROUP="spi_miso" ; +NET "spi_miso<1>" COLOR=6 IO_GROUP="spi_miso" ; +NET "spi_miso<0>" COLOR=6 IO_GROUP="spi_miso" ; +NET "spi_int<3>" COLOR=6 IO_GROUP="spi_int" ; +NET "spi_int<2>" COLOR=6 IO_GROUP="spi_int" ; +NET "spi_int<1>" COLOR=6 IO_GROUP="spi_int" ; +NET "spi_int<0>" COLOR=6 IO_GROUP="spi_int" ; +NET "Ncs2" COLOR=6 ; +NET "extclk" COLOR=6 ; +NET "diag" COLOR=6 ; +NET "cpu_rnw" COLOR=6 ; +NET "cpu_Nres" COLOR=6 ; +NET "cpu_Nphi2" COLOR=6 ; +NET "cpu_Nirq" COLOR=6 ; +NET "cpu_d<7>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<6>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<5>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<4>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<3>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<2>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<1>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_d<0>" COLOR=6 IO_GROUP="cpu_d" ; +NET "cpu_a<1>" COLOR=6 IO_GROUP="cpu_a" ; +NET "cpu_a<0>" COLOR=6 IO_GROUP="cpu_a" ; +INST "spi_mosi_OBUFE" COLOR=7 ; +INST "cpu_Nirq_OBUFE" COLOR=8 ; diff --git a/SPI6502B.ucf b/SPI6502B.ucf new file mode 100644 index 0000000..29233d9 --- /dev/null +++ b/SPI6502B.ucf @@ -0,0 +1,43 @@ +#net "diag" loc="P29"; + +#PACE: Start of Constraints generated by PACE + +#PACE: Start of PACE I/O Pin Assignments +NET "cpu_a<0>" LOC = "P22" ; +NET "cpu_a<1>" LOC = "P24" ; +NET "cpu_d<0>" LOC = "P2" ; +NET "cpu_d<1>" LOC = "P3" ; +NET "cpu_d<2>" LOC = "P4" ; +NET "cpu_d<3>" LOC = "P8" ; +NET "cpu_d<4>" LOC = "P9" ; +NET "cpu_d<5>" LOC = "P11" ; +NET "cpu_d<6>" LOC = "P12" ; +NET "cpu_d<7>" LOC = "P13" ; +NET "cpu_Nirq" LOC = "P14" ; +NET "cpu_Nphi2" LOC = "P5" ; +NET "cpu_Nres" LOC = "P19" ; +NET "cpu_rnw" LOC = "P7" ; +NET "cs1" LOC = "P20" ; +NET "diag" LOC = "P29" ; +NET "extclk" LOC = "P6" ; +NET "Ncs2" LOC = "P18" ; +NET "spi_int<0>" LOC = "P42" ; +NET "spi_int<1>" LOC = "P40" ; +NET "spi_int<2>" LOC = "P39" ; +NET "spi_int<3>" LOC = "P1" ; +NET "spi_miso<0>" LOC = "P44" ; +NET "spi_miso<1>" LOC = "P43" ; +NET "spi_miso<2>" LOC = "P38" ; +NET "spi_miso<3>" LOC = "P37" ; +NET "spi_mosi" LOC = "P35" ; +NET "spi_Nsel<0>" LOC = "P28" ; +NET "spi_Nsel<1>" LOC = "P27" ; +NET "spi_Nsel<2>" LOC = "P26" ; +NET "spi_Nsel<3>" LOC = "P25" ; +NET "spi_sclk" LOC = "P34" ; + +#PACE: Start of PACE Area Constraints + +#PACE: Start of PACE Prohibit Constraints + +#PACE: End of Constraints generated by PACE diff --git a/SPI6502B.ucf.untf b/SPI6502B.ucf.untf new file mode 100644 index 0000000..e69de29 diff --git a/SPI6502B1.1.vhd b/SPI6502B1.1.vhd new file mode 100644 index 0000000..e1f02a9 --- /dev/null +++ b/SPI6502B1.1.vhd @@ -0,0 +1,367 @@ +---------------------------------------------------------------------------------- +-- Company: n/a +-- Engineer: A. Fachat +-- +-- Create Date: 12:37:11 05/07/2011 +-- Design Name: SPI65B +-- Module Name: SPI6502B - Behavioral +-- Project Name: CS/A NETUSB 2.0 +-- Target Devices: CS/A NETUSB 2.0 +-- Tool versions: +-- Description: An SPI interface for 6502-based computers (or compatible). +-- modelled after the SPI65 interface by Daryl Rictor +-- (see http://sbc.rictor.org/io/65spi.html ) +-- This implementation here, however, is a complete reimplementation +-- as the ABEL language of the original implementation is not supported +-- by ISE anymore. +-- Also I added the interrupt input handling, replacing four of the +-- original SPI select outputs with four interrupt inputs +-- Also folded out the single MISO input into one input for each of the +-- four supported devices, reducing external parts count again by one. +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination, +-- to drive up SPI clock to half of input clock (and not one fourth only as before) +-- unfortunately that costed one divisor bit to fit into the CPLD +-- Additional Comments: +-- +---------------------------------------------------------------------------------- +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--use IEEE.NUMERIC_STD.ALL; + + +-- Uncomment the following library declaration if instantiating +-- any Xilinx primitives in this code. +--library UNISIM; +--use UNISIM.VComponents.all; + +entity SPI6502B is + + + Port ( cpu_d : inout STD_LOGIC_VECTOR (7 downto 0); + cpu_rnw : in STD_LOGIC; + cpu_Nirq : out STD_LOGIC; + cpu_Nres : in STD_LOGIC; + cpu_a : in STD_LOGIC_VECTOR (1 downto 0); + cpu_Nphi2 : in STD_LOGIC; + cs1 : in STD_LOGIC; + Ncs2 : in STD_LOGIC; + extclk : in STD_LOGIC; + spi_miso: in std_logic_vector (3 downto 0); + spi_mosi : out STD_LOGIC; + spi_sclk : out STD_LOGIC; + spi_Nsel : out STD_LOGIC_VECTOR (3 downto 0); + spi_int : in STD_LOGIC_VECTOR (3 downto 0); + diag : out std_logic + ); + + constant DIV_WIDTH : integer := 3; + +end SPI6502B; + +architecture Behavioral of SPI6502B is + + -- interface signals + signal selected: std_logic; + signal reset: std_logic; + signal int_out: std_logic; + signal is_read: std_logic; + signal int_din: std_logic_vector (7 downto 0); + signal int_dout: std_logic_vector (7 downto 0); + + signal int_mosi: std_logic; + signal int_miso: std_logic; + signal int_sclk: std_logic; + + -------------------------- + -- internal state + signal spidatain: std_logic_vector (7 downto 0); + signal spidataout: std_logic_vector (7 downto 0); + signal spiint: std_logic; -- spi interrupt state + + -- spi register flags + signal tc: std_logic; -- transmission complete; cleared on spi data read + signal ier: std_logic; -- enable general SPI interrupts + signal bsy: std_logic; -- SPI busy + signal frx: std_logic; -- fast receive mode + signal tmo: std_logic; -- tri-state mosi + signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock + signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge + signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge + + signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0); + + signal slavesel: std_logic_vector(3 downto 0); -- slave select output (0=selected) + signal slaveinten: std_logic_vector(3 downto 0); -- slave interrupt enable (1=enabled) + signal slaveint: std_logic_vector (3 downto 0); -- slave interrupt inputs + + -------------------------- + -- helper signals + + -- shift engine + signal start_shifting: std_logic; -- shifting data + signal shifting2: std_logic; -- shifting data + signal shiftdone: std_logic; -- shifting data done + signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit) + + -- spi clock + signal clksrc: std_logic; -- clock source (phi2 or extclk) + signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter + + signal shiftclk : std_logic; + +begin + + diag <= not (bsy or not slavesel(0)); --'0'; --shifting2; --shiftdone; --shiftcnt(2); + + -------------------------- + + bsy <= start_shifting or shifting2; + + process(start_shifting, shiftdone, shiftclk) + begin + if (rising_edge(shiftclk)) then + if (shiftdone = '1') then + shifting2 <= '0'; + else + shifting2 <= start_shifting; + end if; + end if; + end process; + + process(shiftcnt, reset, shiftclk) + begin + if (reset = '1') then + shiftdone <= '0'; + elsif (rising_edge(shiftclk)) then + if (shiftcnt = "1111") then + shiftdone <= '1'; + else + shiftdone <= '0'; + end if; + end if; + end process; + + process(reset, shifting2, shiftcnt, shiftclk) + begin + if (reset='1') then + shiftcnt <= (others => '0'); + elsif (rising_edge(shiftclk)) then + if (shifting2 = '1') then + -- count phase + shiftcnt <= shiftcnt + 1; + else + shiftcnt <= (others => '0'); + end if; + end if; + end process; + + inproc: process(reset, shifting2, + shiftcnt, shiftclk, spidatain, int_miso) + begin + if (reset='1') then + spidatain <= (others => '0'); + elsif (rising_edge(shiftclk)) then + if (shifting2 = '1' and shiftcnt(0) = '1') then + -- shift in to input register + spidatain (7 downto 1) <= spidatain (6 downto 0); + spidatain (0) <= int_miso; + end if; + end if; + end process; + + outproc: process(reset, shifting2, spidataout, cpol, cpha, + shiftcnt, shiftclk) + begin + if (reset='1') then + int_mosi <= '1'; + int_sclk <= cpol; + else + -- clock is sync'd + if (rising_edge(shiftclk)) then + if (shifting2='0' or shiftdone = '1') then + int_mosi <= '1'; + int_sclk <= cpol; + else + -- output data directly from output register + case shiftcnt(3 downto 1) is + when "000" => int_mosi <= spidataout(7); + when "001" => int_mosi <= spidataout(6); + when "010" => int_mosi <= spidataout(5); + when "011" => int_mosi <= spidataout(4); + when "100" => int_mosi <= spidataout(3); + when "101" => int_mosi <= spidataout(2); + when "110" => int_mosi <= spidataout(1); + when "111" => int_mosi <= spidataout(0); + when others => int_mosi <= '1'; + end case; + int_sclk <= cpol xor cpha xor shiftcnt(0); + end if; + end if; + end if; + end process; + + + -- shift operation enable + shiften: process(reset, selected, cpu_rnw, cpu_a, frx, shiftdone) + begin + -- start shifting + if (reset='1' or shiftdone='1') then + start_shifting <= '0'; + elsif (falling_edge(selected) and cpu_a="00" and (frx='1' or cpu_rnw='0')) then + -- access to register 00, either write (cpu_rnw=0) or fast receive bit set (frx) + -- then both types of access (write but also read) + start_shifting <= '1'; + end if; + end process; + + -------------------------- + -- spiclk - spi clock generation + -- spiclk is still 2 times the freq. than sclk + clksrc <= cpu_Nphi2 when (ece = '0') else extclk; + + -- is a pulse signal to allow for divisor==0 + --shiftclk <= clksrc when divcnt = "000000" else '0'; + shiftclk <= clksrc when bsy = '1' else '0'; + + clkgen: process(reset, divisor, clksrc) + begin + if (reset='1') then + divcnt <= divisor; + --spiclk <= '0'; + elsif (falling_edge(clksrc)) then + if (shiftclk = '1') then + divcnt <= divisor; + --spiclk <= not(spiclk); + else + divcnt <= divcnt - 1; + end if; + end if; + end process; + + -------------------------- + -- interrupt generation + int_out <= spiint + or (slaveint(0) and slaveinten(0)) + or (slaveint(1) and slaveinten(1)) + or (slaveint(2) and slaveinten(2)) + or (slaveint(3) and slaveinten(3)); + + -------------------------- + -- interface section + -- inputs + reset <= not (cpu_Nres); + selected <= cs1 and not(Ncs2); -- and cpu_phi2; + is_read <= selected and cpu_Nphi2 and cpu_rnw; + int_din <= cpu_d; + slaveint <= not(spi_int); -- active low interrupt inputs + + int_miso <= + (spi_miso(0) and not(slavesel(0))) + or (spi_miso(1) and not(slavesel(1))) + or (spi_miso(2) and not(slavesel(2))) + or (spi_miso(3) and not(slavesel(3))); + + -- outputs + cpu_d <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate + cpu_Nirq <= '0' when (int_out='1') else 'Z'; -- wired-or + spi_sclk <= int_sclk; + spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state + spi_Nsel <= slavesel; + + tc_proc: process (selected, shiftdone) + begin + if (shiftdone = '1') then + tc <= '1'; + elsif (falling_edge(selected) and cpu_a="00" + --elsif (falling_edge(cpu_phi2) and selected='1' and cpu_a="00" + --and cpu_rnw='1' -- both reads _and_ writes clear the interrupt + ) then + tc <= '0'; + end if; + end process; + + spiint <= tc and ier; + + -------------------------- + -- cpu register section + -- cpu read + cpu_read: process (is_read, cpu_a, + spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor, + slavesel, slaveint, slaveinten) + begin + if (is_read = '1') then + case cpu_a is + when "00" => -- read SPI data in + int_dout <= spidatain; + when "01" => -- read status register + int_dout(0) <= cpha; + int_dout(1) <= cpol; + int_dout(2) <= ece; + int_dout(3) <= tmo; + int_dout(4) <= frx; + int_dout(5) <= bsy; + int_dout(6) <= ier; + int_dout(7) <= tc; + when "10" => -- read sclk divisor + int_dout(DIV_WIDTH-1 downto 0) <= divisor; + int_dout(3) <= '0'; + int_dout(7 downto 4) <= slaveint; + when "11" => -- read slave select / slave interrupt state + int_dout(3 downto 0) <= slavesel; + int_dout(7 downto 4) <= slaveinten; + when others => + int_dout <= (others => '0'); + end case; + else + int_dout <= (others => '0'); + end if; + end process; + + -- cpu write + cpu_write: process(reset, selected, cpu_rnw, cpu_a, int_din) + begin + if (reset = '1') then + cpha <= '0'; + cpol <= '0'; + ece <= '0'; + tmo <= '0'; + frx <= '0'; + ier <= '0'; + slavesel <= (others => '1'); + slaveinten <= (others => '0'); + divisor <= (others => '0'); + elsif (falling_edge(selected) and cpu_rnw = '0') then + --elsif (falling_edge(cpu_phi2) and selected='1' and cpu_rnw='0') then + case cpu_a is + when "00" => -- write SPI data out (see other process above) + spidataout <= int_din; + when "01" => -- write status register + cpha <= int_din(0); + cpol <= int_din(1); + ece <= int_din(2); + tmo <= int_din(3); + frx <= int_din(4); + -- no bit 5 + ier <= int_din(6); + -- no bit 7; + when "10" => -- write divisor + divisor <= int_din(DIV_WIDTH-1 downto 0); + when "11" => -- write slave select / slave interrupt enable + slavesel <= int_din(3 downto 0); + slaveinten <= int_din(7 downto 4); + when others => + end case; + end if; + end process; + +end Behavioral; + diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst new file mode 100644 index 0000000..0956acd --- /dev/null +++ b/_ngo/netlist.lst @@ -0,0 +1,2 @@ +C:\sources\AppleIISd\spi6502b.ngc 1494084468 +OK diff --git a/_pace.ucf b/_pace.ucf new file mode 100644 index 0000000..add0940 --- /dev/null +++ b/_pace.ucf @@ -0,0 +1,41 @@ + +NET "cpu_Nphi2" loc="P5"; +NET "extclk" loc="P6"; +NET "cpu_rnw" loc="P7"; + +#net "diag" loc="P29"; + +NET "cpu_d<0>" loc="P2"; +NET "cpu_d<1>" loc="P3"; +NET "cpu_d<2>" loc="P4"; +NET "cpu_d<3>" loc="P8"; +NET "cpu_d<4>" loc="P9"; +NET "cpu_d<5>" loc="P11"; +NET "cpu_d<6>" loc="P12"; +NET "cpu_d<7>" loc="P13"; + +NET "cpu_Nirq" loc="P14"; +NET "Ncs2" loc="P18"; +NET "cs1" loc="P20"; +NET "cpu_Nres" loc="P19"; + +NET "cpu_a<0>" loc="P22"; +NET "cpu_a<1>" loc="P24"; + +NET "spi_int<0>" loc="P42"; +NET "spi_int<1>" loc="P40"; +NET "spi_int<2>" loc="P39"; +NET "spi_int<3>" loc="P1"; + +NET "spi_Nsel<0>" loc="P28"; +NET "spi_Nsel<1>" loc="P27"; +NET "spi_Nsel<2>" loc="P26"; +NET "spi_Nsel<3>" loc="P25"; + +NET "spi_sclk" loc="P34"; +NET "spi_mosi" loc="P35"; + +NET "spi_miso<0>" loc="P44"; +NET "spi_miso<1>" loc="P43"; +NET "spi_miso<2>" loc="P38"; +NET "spi_miso<3>" loc="P37"; diff --git a/spi65.cdf b/spi65.cdf new file mode 100644 index 0000000..d3ad07b --- /dev/null +++ b/spi65.cdf @@ -0,0 +1,16 @@ +JedecChain; +FileRevision(JESDxxA); +/* NoviceMode */ +/* Active Mode BS */ +/* Mode BS */ +/* Cable PlatformCableUSB usb21 6000000 */ + P ActionCode(Cfg) + Device + PartName(xc9572xl) + File("C:\sources\spi65\spi6502b.jed") + ; +/* Mode SS */ +/* Mode SM */ +/* Mode BSFILE */ +/* Mode HW140 */ +ChainEnd; diff --git a/spi65.dhp b/spi65.dhp new file mode 100644 index 0000000..769350c --- /dev/null +++ b/spi65.dhp @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e +$75x4>763-Xnzd}foo8#5+72(-k0=989971304g<9=<=5;=841c851011?9<;=o415567623:?k0=99:410;13g<9=3:94>855c851?381>?9564AsakJdkbj2KyoeAmjdaww<=Edfi`Xt~j9:ALIHOS\LN<7N\JAUGG<>EheyCeyo4Eovjp|Oi{}k0IczftxLbi`d@ndlYn~{k|a:KmgiscmFha:6B@AEGG<>Jffnjkhl4Lh`qewIido:=6Bfbscq}Vrf|lgnby}7;Lgpwdab{k1[mnengdLbi`?3Xj`dhfesd8WUO1=98I=#?!vif27>UWA??;>O?!1/tk`(77>890_]G9510A5+7)~an&==9>3:QSM337:K;%=#xgd,32045<[YC=9=2:QSM337:K;%=#xgd,1757=TX@<>.0,ula+4=880_]G9510A5+7)~an&8??=;RRJ2065J8$:"{fk-5126>UWA??;>O?!1/tk`(>59;1X\D8:03@2*4(q`m'3?;5\estfwg=Smz~]inz`rr`8PjvAaeoGe~zk;TqfWqgsmdoex~?k;YKOMK^*PMH+<#?/SUWA$5(6(HYHED84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee?6ocl`9aamgqafxj`h5meicumjtfd$;:>h5meicumjtfd$;9;h6ljh`tjkwgk%=2h7okgawklvdj*0m1iieoyinpbh(>?i2hbbiKathvzf>dnfmZjofohe59ja`ce3`dh`xjj-02;f>oikeoi ?>6c9jjfjrll':>9o4ioaoqac*;?30ecmcueg.0d=nfjf~hh#;4`9jjfjrll'3855`bkKm``~d3zid|hO}ciManf=tkfznJdbjOch`?vehxlFbbh@zm79pmhvkm11x|d8:03``?vvn><:9n ?>1b9ptl028;h&=<7l;rrj2065j$;9;o5|ph4647d*;0h0}g9510a)11f3zzb:8>=b,5a?vvn><:9n 68e:qw`Zjho`iT=<8;139ppaYkgnchSx`|iflf`2=r{l':<494urg.54603|yn!1~h#>2458qvc*9;<=7x}j-255?pub%:2=7x}j-575?pub%=<>7x}j-478qvc*>?1~h#7579vw`+?>tJK|>k4@Az7a?@=910:w^j54d82>454i9=96?o641ym70<63g9=6?5+35807>{Tk3>n6<4>32c337<5i0>:7^?8:5g95?74;h:<>7=n06096dbe>2Y:;7:j:08276g7?;09mihn;Ra90`<62898m=9=:3cf2d=T9>0?i7?5121b4fg=:j8>m6]l:5g95?74;h:hm747a:>1Xo7:j:08276g7kk0:>=ll;R34>1c=93;8?l>kb;3gffc<[j0?i7?5121b4ad=9lk;96]>7;6f>4<6;:k:><4=a31a?Ve=7g5<81X=:4;e;39565f9l31>9l:1:Q`>1c=93;8?l?j9;07a0?<[8=18h4>:010e4cf28=;;k5\c;6f>4<6;:k:il4>9660?V702=o1=7?<3`3fe?7>j990_n4;e;39565f9lk1=4l>5:Q23?2b280:?>m9a681`5cf3Zi18h4>:010g3g02;n>585\1687a?7=9:9h;=o5246b6>Ud2=o1=7?<3b53e?420h9k50;395~Uc2=o1=7?<3`246?4f1=:0b9o5819L74<73F;86=5yF3794?7=93:p_i4;e;39565d?9k1>8:n2:l255;2xj1b=92di6<5@2g83?!7e291/=?4=0:&20?6<,8o1<6*>d;:8K47=82E:97>4O5a95~{e<<0;6=4?:1ym0a5}i94O5394>I3k3;pqB?9:0y~yg3b290;6=4?{o6g>742=80(4O5a95~{H9?0:wpsm5383>5<729qe8i4=e:la>7=H:o0;7)??:5d8Kd<73F>h650;2xj1b=">2:20(>>50:&24?2a3Fo1<6Ai:19L05<73F>h6o4>f:M1g?433F9;6j5369~DE \ No newline at end of file diff --git a/spi65.npl b/spi65.npl new file mode 100644 index 0000000..9c31b13 --- /dev/null +++ b/spi65.npl @@ -0,0 +1,26 @@ +JDF G +// Created by Project Navigator ver 1.0 +PROJECT spi65 +DESIGN spi65 +DEVFAM xc9500xl +DEVFAMTIME 0 +DEVICE xc9572xl +DEVICETIME 1468568184 +DEVPKG PC44 +DEVPKGTIME 1475334247 +DEVSPEED -10 +DEVSPEEDTIME 1469967516 +DEVTOPLEVELMODULETYPE HDL +TOPLEVELMODULETYPETIME 0 +DEVSYNTHESISTOOL XST (VHDL/Verilog) +SYNTHESISTOOLTIME 0 +DEVSIMULATOR Other +SIMULATORTIME 0 +DEVGENERATEDSIMULATIONMODEL VHDL +GENERATEDSIMULATIONMODELTIME 0 +SOURCE SPI6502B1.1.vhd +DEPASSOC spi6502b SPI6502B.ucf +[STATUS-ALL] +spi6502b.ngcFile=WARNINGS,1494084467 +[STRATEGY-LIST] +Normal=True diff --git a/spi6502b._hrpt b/spi6502b._hrpt new file mode 100644 index 0000000..804880a --- /dev/null +++ b/spi6502b._hrpt @@ -0,0 +1 @@ +Up-to-date diff --git a/spi6502b.bld b/spi6502b.bld new file mode 100644 index 0000000..28cca87 --- /dev/null +++ b/spi6502b.bld @@ -0,0 +1,23 @@ +Release - ngdbuild G.38 +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. + +Command Line: ngdbuild -dd _ngo -uc SPI6502B.ucf -p xc9500xl spi6502b.ngc +spi6502b.ngd + +Reading NGO file "C:/sources/AppleIISd/spi6502b.ngc" ... +Reading component libraries for design expansion... + +Annotating constraints to design from file "SPI6502B.ucf" ... + +Checking timing specifications ... +Checking expanded design ... + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 58840 kilobytes + +Writing NGD file "spi6502b.ngd" ... + +Writing NGDBUILD log file "spi6502b.bld"... diff --git a/spi6502b.gyd b/spi6502b.gyd new file mode 100644 index 0000000..6f7ccb8 --- /dev/null +++ b/spi6502b.gyd @@ -0,0 +1,58 @@ +Pin Freeze File: version G.38 + +9572XL44PC XC9572XL-10-PC44 +Ncs2 S:PIN18 +cpu_Nphi2 S:PIN5 +cpu_Nres S:PIN19 +cpu_a<0> S:PIN22 +cpu_a<1> S:PIN24 +cpu_rnw S:PIN7 +cs1 S:PIN20 +extclk S:PIN6 +spi_int<0> S:PIN42 +spi_int<1> S:PIN40 +spi_int<2> S:PIN39 +spi_int<3> S:PIN1 +spi_miso<0> S:PIN44 +spi_miso<1> S:PIN43 +spi_miso<2> S:PIN38 +spi_miso<3> S:PIN37 +cpu_Nirq S:PIN14 +diag S:PIN29 +cpu_d<0> S:PIN2 +cpu_d<1> S:PIN3 +cpu_d<2> S:PIN4 +cpu_d<3> S:PIN8 +cpu_d<4> S:PIN9 +cpu_d<5> S:PIN11 +cpu_d<6> S:PIN12 +cpu_d<7> S:PIN13 +spi_mosi S:PIN35 +spi_sclk S:PIN34 +spi_Nsel<0> S:PIN28 +spi_Nsel<1> S:PIN27 +spi_Nsel<2> S:PIN26 +spi_Nsel<3> S:PIN25 + + +;The remaining section of the .gyd file is for documentation purposes only. +;It shows where your internal equations were placed in the last successful fit. + +PARTITION FB1_1 spidataout<3> spidataout<2> spidataout<1> spidataout<0> + int_dout<0> int_dout<1> tmo int_dout<2> + slaveinten<0> frx ece divisor<2> + divisor<1> divisor<0> int_dout<3> cpol + int_dout<4> cpha +PARTITION FB2_1 start_shifting/start_shifting_RSTF__$INT int_mosi EXP6_ + +PARTITION FB3_1 shifting2 int_dout<5> shiftdone $OpTx$INV$22__$INT + int_dout<6> start_shifting spidatain<7> int_dout<7> + cpu_Nirq_OBUFE spidatain<6> spidatain<5> spidatain<4> + spidatain<3> spidatain<2> spidatain<1> shiftcnt<3> + shiftcnt<2> cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST +PARTITION FB4_1 tc slavesel<3> shiftcnt<0> spidataout<7> + slavesel<2> spidataout<6> spidataout<5> slavesel<1> + spidataout<4> shiftcnt<1> slavesel<0> slaveinten<3> + slaveinten<2> diag_OBUF slaveinten<1> ier + int_sclk spidatain<0> + diff --git a/spi6502b.imp b/spi6502b.imp new file mode 100644 index 0000000..804880a --- /dev/null +++ b/spi6502b.imp @@ -0,0 +1 @@ +Up-to-date diff --git a/spi6502b.jed b/spi6502b.jed new file mode 100644 index 0000000..7aa95a8 --- /dev/null +++ b/spi6502b.jed @@ -0,0 +1,1666 @@ +Programmer Jedec Bit Map +Date Extracted: Sat May 06 17:27:53 2017 + +QF46656* +QP44* +QV0* +F0* +X0* +J0 0* +N DEVICE XC9572XL-10-PC44* +N PPMAP 11 1* +N PPMAP 29 11* +N PPMAP 31 12* +N PPMAP 33 13* +N PPMAP 38 14* +N PPMAP 46 18* +N PPMAP 49 19* +N PPMAP 12 2* +N PPMAP 50 20* +N PPMAP 52 22* +N PPMAP 59 24* +N PPMAP 62 25* +N PPMAP 63 26* +N PPMAP 65 27* +N PPMAP 68 28* +N PPMAP 72 29* +N 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00000000* +L0046352 00000000 00000000 00000000 00000000* +L0046384 01100100 00000000 00000000 00000000* +L0046416 01100100 00000000 00000000 10000000* +L0046448 01100100 00000000 00000000 00000000* +L0046480 01100100 00000000 00000000 00000000* +L0046512 011001 000000 000000 000000* +L0046536 010010 000000 000000 000000* +L0046560 010010 000000 000010 000000* +L0046584 010010 000000 000000 000000* +L0046608 010010 000000 000000 000000* +L0046632 010000 000000 000000 000000* +CDFEE* +1A8C diff --git a/spi6502b.mfd b/spi6502b.mfd new file mode 100644 index 0000000..96cfda5 --- /dev/null +++ b/spi6502b.mfd @@ -0,0 +1,843 @@ +MDF Database: version 1.0 +MDF_INFO | spi6502b | XC9572XL-10-PC44 +MACROCELL | 1 | 1 | int_mosi +ATTRIBUTES | 8652706 | 0 +INPUTS | 12 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<5> | shifting2 | spidataout<1> | start_shifting/start_shifting_RSTF__$INT.EXP | EXP6_.EXP | $OpTx$INV$22__$INT | cpu_Nres | tmo +INPUTMC | 11 | 2 | 15 | 2 | 16 | 3 | 9 | 2 | 2 | 3 | 6 | 2 | 0 | 0 | 2 | 1 | 0 | 1 | 2 | 2 | 3 | 0 | 6 +INPUTP | 1 | 49 +IMPORTS | 2 | 1 | 0 | 1 | 2 +EQ | 21 | + !spi_mosi.D = shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & + !shiftdone & !spidataout<1> & shifting2 + # !shiftcnt<3> & shiftcnt<2> & !shiftcnt<1> & + !shiftdone & !spidataout<5> & shifting2 +;Imported pterms FB2_1 + # shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & + !shiftdone & !spidataout<3> & shifting2 + # !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & + !shiftdone & !spidataout<7> & shifting2 +;Imported pterms FB2_3 + # shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<0> & shifting2 + # shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<2> & shifting2 + # !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<4> & shifting2 + # !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<6> & shifting2; + spi_mosi.CLK = !$OpTx$INV$22__$INT; + spi_mosi.AP = !cpu_Nres; + spi_mosi.OE = !tmo; + +MACROCELL | 3 | 10 | slavesel<0> +ATTRIBUTES | 4588514 | 0 +OUTPUTMC | 4 | 3 | 10 | 3 | 0 | 0 | 4 | 3 | 13 +INPUTS | 8 | spi_Nsel<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 10 +INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24 +EQ | 7 | + spi_Nsel<0>.T = spi_Nsel<0> & cpu_a<1> & cpu_a<0> & + !cpu_d<0>.PIN + # !spi_Nsel<0> & cpu_a<1> & cpu_a<0> & + cpu_d<0>.PIN; + !spi_Nsel<0>.CLK = cs1 & !Ncs2; + spi_Nsel<0>.AP = !cpu_Nres; + spi_Nsel<0>.CE = !cpu_rnw; + +MACROCELL | 3 | 7 | slavesel<1> +ATTRIBUTES | 4588514 | 0 +OUTPUTMC | 3 | 3 | 7 | 3 | 0 | 0 | 5 +INPUTS | 8 | spi_Nsel<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 7 +INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24 +EQ | 7 | + spi_Nsel<1>.T = spi_Nsel<1> & cpu_a<1> & cpu_a<0> & + !cpu_d<1>.PIN + # !spi_Nsel<1> & cpu_a<1> & cpu_a<0> & + cpu_d<1>.PIN; + !spi_Nsel<1>.CLK = cs1 & !Ncs2; + spi_Nsel<1>.AP = !cpu_Nres; + spi_Nsel<1>.CE = !cpu_rnw; + +MACROCELL | 3 | 4 | slavesel<2> +ATTRIBUTES | 4588514 | 0 +OUTPUTMC | 3 | 3 | 4 | 3 | 17 | 0 | 7 +INPUTS | 8 | spi_Nsel<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 4 +INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24 +EQ | 7 | + spi_Nsel<2>.T = spi_Nsel<2> & cpu_a<1> & cpu_a<0> & + !cpu_d<2>.PIN + # !spi_Nsel<2> & cpu_a<1> & cpu_a<0> & + cpu_d<2>.PIN; + !spi_Nsel<2>.CLK = cs1 & !Ncs2; + spi_Nsel<2>.AP = !cpu_Nres; + spi_Nsel<2>.CE = !cpu_rnw; + +MACROCELL | 3 | 1 | slavesel<3> +ATTRIBUTES | 4588514 | 0 +OUTPUTMC | 3 | 3 | 1 | 3 | 17 | 0 | 14 +INPUTS | 8 | spi_Nsel<3> | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 1 +INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24 +EQ | 7 | + spi_Nsel<3>.T = spi_Nsel<3> & cpu_a<1> & cpu_a<0> & + !cpu_d<3>.PIN + # !spi_Nsel<3> & cpu_a<1> & cpu_a<0> & + cpu_d<3>.PIN; + !spi_Nsel<3>.CLK = cs1 & !Ncs2; + spi_Nsel<3>.AP = !cpu_Nres; + spi_Nsel<3>.CE = !cpu_rnw; + +MACROCELL | 0 | 15 | cpol +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 0 | 15 | 3 | 16 | 0 | 5 +INPUTS | 8 | cpol | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 15 +INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24 +EQ | 5 | + cpol.T = cpol & !cpu_a<1> & cpu_a<0> & !cpu_d<1>.PIN + # !cpol & !cpu_a<1> & cpu_a<0> & cpu_d<1>.PIN; + !cpol.CLK = cs1 & !Ncs2; + cpol.AR = !cpu_Nres; + cpol.CE = !cpu_rnw; + +MACROCELL | 0 | 10 | ece +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 0 | 10 | 0 | 7 | 2 | 3 +INPUTS | 8 | ece | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 10 +INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24 +EQ | 5 | + ece.T = ece & !cpu_a<1> & cpu_a<0> & !cpu_d<2>.PIN + # !ece & !cpu_a<1> & cpu_a<0> & cpu_d<2>.PIN; + !ece.CLK = cs1 & !Ncs2; + ece.AR = !cpu_Nres; + ece.CE = !cpu_rnw; + +MACROCELL | 0 | 17 | cpha +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 4 | 0 | 17 | 3 | 16 | 0 | 4 | 3 | 15 +INPUTS | 8 | cpha | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 17 +INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24 +EQ | 5 | + cpha.T = cpha & !cpu_a<1> & cpu_a<0> & !cpu_d<0>.PIN + # !cpha & !cpu_a<1> & cpu_a<0> & cpu_d<0>.PIN; + !cpha.CLK = cs1 & !Ncs2; + cpha.AR = !cpu_Nres; + cpha.CE = !cpu_rnw; + +MACROCELL | 0 | 9 | frx +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 0 | 9 | 2 | 5 | 0 | 16 +INPUTS | 8 | frx | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 9 +INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24 +EQ | 5 | + frx.T = frx & !cpu_a<1> & cpu_a<0> & !cpu_d<4>.PIN + # !frx & !cpu_a<1> & cpu_a<0> & cpu_d<4>.PIN; + !frx.CLK = cs1 & !Ncs2; + frx.AR = !cpu_Nres; + frx.CE = !cpu_rnw; + +MACROCELL | 3 | 15 | ier +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 5 | 3 | 15 | 2 | 4 | 2 | 17 | 3 | 14 | 3 | 16 +INPUTS | 13 | ier | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw | cpha | shiftcnt<0> | shiftdone | shifting2 | slaveinten<1>.EXP +INPUTMC | 6 | 3 | 15 | 0 | 17 | 3 | 2 | 2 | 2 | 2 | 0 | 3 | 14 +INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24 +EXPORTS | 1 | 3 | 16 +IMPORTS | 1 | 3 | 14 +EQ | 8 | + ier.T = !ier & !cpu_a<1> & cpu_a<0> & cpu_d<6>.PIN +;Imported pterms FB4_15 + # ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN; + !ier.CLK = cs1 & !Ncs2; + ier.AR = !cpu_Nres; + ier.CE = !cpu_rnw; + ier.EXP = cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & + shifting2 + +MACROCELL | 0 | 8 | slaveinten<0> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 0 | 8 | 0 | 16 | 2 | 17 +INPUTS | 8 | slaveinten<0> | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 8 +INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24 +EQ | 7 | + slaveinten<0>.T = slaveinten<0> & cpu_a<1> & cpu_a<0> & + !cpu_d<4>.PIN + # !slaveinten<0> & cpu_a<1> & cpu_a<0> & + cpu_d<4>.PIN; + !slaveinten<0>.CLK = cs1 & !Ncs2; + slaveinten<0>.AR = !cpu_Nres; + slaveinten<0>.CE = !cpu_rnw; + +MACROCELL | 3 | 14 | slaveinten<1> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 5 | 3 | 14 | 2 | 1 | 2 | 17 | 3 | 13 | 3 | 15 +INPUTS | 11 | slaveinten<1> | cpu_a<1> | cpu_a<0> | cpu_d<5>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw | ier | cpu_d<6>.PIN | diag_OBUF.EXP +INPUTMC | 3 | 3 | 14 | 3 | 15 | 3 | 13 +INPUTP | 8 | 59 | 52 | 29 | 50 | 46 | 49 | 24 | 31 +EXPORTS | 1 | 3 | 15 +IMPORTS | 1 | 3 | 13 +EQ | 9 | + slaveinten<1>.T = !slaveinten<1> & cpu_a<1> & cpu_a<0> & + cpu_d<5>.PIN +;Imported pterms FB4_14 + # slaveinten<1> & cpu_a<1> & cpu_a<0> & + !cpu_d<5>.PIN; + !slaveinten<1>.CLK = cs1 & !Ncs2; + slaveinten<1>.AR = !cpu_Nres; + slaveinten<1>.CE = !cpu_rnw; + slaveinten<1>.EXP = ier & !cpu_a<1> & cpu_a<0> & !cpu_d<6>.PIN + +MACROCELL | 3 | 12 | slaveinten<2> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 3 | 12 | 2 | 4 | 2 | 17 +INPUTS | 8 | slaveinten<2> | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 12 +INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24 +EQ | 7 | + slaveinten<2>.T = slaveinten<2> & cpu_a<1> & cpu_a<0> & + !cpu_d<6>.PIN + # !slaveinten<2> & cpu_a<1> & cpu_a<0> & + cpu_d<6>.PIN; + !slaveinten<2>.CLK = cs1 & !Ncs2; + slaveinten<2>.AR = !cpu_Nres; + slaveinten<2>.CE = !cpu_rnw; + +MACROCELL | 3 | 11 | slaveinten<3> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 3 | 11 | 2 | 7 | 2 | 17 +INPUTS | 8 | slaveinten<3> | cpu_a<1> | cpu_a<0> | cpu_d<7>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 11 +INPUTP | 7 | 59 | 52 | 33 | 50 | 46 | 49 | 24 +EQ | 7 | + slaveinten<3>.T = slaveinten<3> & cpu_a<1> & cpu_a<0> & + !cpu_d<7>.PIN + # !slaveinten<3> & cpu_a<1> & cpu_a<0> & + cpu_d<7>.PIN; + !slaveinten<3>.CLK = cs1 & !Ncs2; + slaveinten<3>.AR = !cpu_Nres; + slaveinten<3>.CE = !cpu_rnw; + +MACROCELL | 0 | 6 | tmo +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 3 | 1 | 1 | 0 | 6 | 0 | 14 +INPUTS | 8 | tmo | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 6 +INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24 +EQ | 5 | + tmo.T = tmo & !cpu_a<1> & cpu_a<0> & !cpu_d<3>.PIN + # !tmo & !cpu_a<1> & cpu_a<0> & cpu_d<3>.PIN; + !tmo.CLK = cs1 & !Ncs2; + tmo.AR = !cpu_Nres; + tmo.CE = !cpu_rnw; + +MACROCELL | 0 | 13 | divisor<0> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 2 | 0 | 13 | 0 | 4 +INPUTS | 8 | divisor<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 13 +INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24 +EQ | 5 | + divisor<0>.T = divisor<0> & cpu_a<1> & !cpu_a<0> & !cpu_d<0>.PIN + # !divisor<0> & cpu_a<1> & !cpu_a<0> & cpu_d<0>.PIN; + !divisor<0>.CLK = cs1 & !Ncs2; + divisor<0>.AR = !cpu_Nres; + divisor<0>.CE = !cpu_rnw; + +MACROCELL | 0 | 12 | divisor<1> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 2 | 0 | 12 | 0 | 5 +INPUTS | 8 | divisor<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 12 +INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24 +EQ | 5 | + divisor<1>.T = divisor<1> & cpu_a<1> & !cpu_a<0> & !cpu_d<1>.PIN + # !divisor<1> & cpu_a<1> & !cpu_a<0> & cpu_d<1>.PIN; + !divisor<1>.CLK = cs1 & !Ncs2; + divisor<1>.AR = !cpu_Nres; + divisor<1>.CE = !cpu_rnw; + +MACROCELL | 0 | 11 | divisor<2> +ATTRIBUTES | 4326256 | 0 +OUTPUTMC | 2 | 0 | 11 | 0 | 7 +INPUTS | 8 | divisor<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 11 +INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24 +EQ | 5 | + divisor<2>.T = divisor<2> & cpu_a<1> & !cpu_a<0> & !cpu_d<2>.PIN + # !divisor<2> & cpu_a<1> & !cpu_a<0> & cpu_d<2>.PIN; + !divisor<2>.CLK = cs1 & !Ncs2; + divisor<2>.AR = !cpu_Nres; + divisor<2>.CE = !cpu_rnw; + +MACROCELL | 3 | 17 | spidatain<0> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 14 | 0 | 4 +INPUTS | 9 | spi_Nsel<3> | spi_miso<3> | spi_Nsel<2> | spi_miso<2> | tc.EXP | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 6 | 3 | 1 | 3 | 4 | 3 | 0 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 3 | 89 | 90 | 49 +IMPORTS | 1 | 3 | 0 +EQ | 8 | + spidatain<0>.D = !spi_Nsel<2> & spi_miso<2> + # !spi_Nsel<3> & spi_miso<3> +;Imported pterms FB4_1 + # !spi_Nsel<0> & spi_miso<0> + # !spi_Nsel<1> & spi_miso<1>; + spidatain<0>.CLK = !$OpTx$INV$22__$INT; + spidatain<0>.AR = !cpu_Nres; + spidatain<0>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 14 | spidatain<1> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 13 | 0 | 5 +INPUTS | 5 | spidatain<0> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 3 | 17 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<1>.D = spidatain<0>; + spidatain<1>.CLK = !$OpTx$INV$22__$INT; + spidatain<1>.AR = !cpu_Nres; + spidatain<1>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 13 | spidatain<2> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 12 | 0 | 7 +INPUTS | 5 | spidatain<1> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 2 | 14 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<2>.D = spidatain<1>; + spidatain<2>.CLK = !$OpTx$INV$22__$INT; + spidatain<2>.AR = !cpu_Nres; + spidatain<2>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 12 | spidatain<3> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 11 | 0 | 14 +INPUTS | 5 | spidatain<2> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 2 | 13 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<3>.D = spidatain<2>; + spidatain<3>.CLK = !$OpTx$INV$22__$INT; + spidatain<3>.AR = !cpu_Nres; + spidatain<3>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 11 | spidatain<4> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 10 | 0 | 16 +INPUTS | 5 | spidatain<3> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 2 | 12 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<4>.D = spidatain<3>; + spidatain<4>.CLK = !$OpTx$INV$22__$INT; + spidatain<4>.AR = !cpu_Nres; + spidatain<4>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 10 | spidatain<5> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 9 | 2 | 1 +INPUTS | 5 | spidatain<4> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 2 | 11 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<5>.D = spidatain<4>; + spidatain<5>.CLK = !$OpTx$INV$22__$INT; + spidatain<5>.AR = !cpu_Nres; + spidatain<5>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 9 | spidatain<6> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 2 | 2 | 6 | 2 | 4 +INPUTS | 5 | spidatain<5> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 2 | 10 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<6>.D = spidatain<5>; + spidatain<6>.CLK = !$OpTx$INV$22__$INT; + spidatain<6>.AR = !cpu_Nres; + spidatain<6>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 2 | 6 | spidatain<7> +ATTRIBUTES | 8520560 | 0 +OUTPUTMC | 1 | 2 | 7 +INPUTS | 5 | spidatain<6> | $OpTx$INV$22__$INT | cpu_Nres | shiftcnt<0> | shifting2 +INPUTMC | 4 | 2 | 9 | 2 | 3 | 3 | 2 | 2 | 0 +INPUTP | 1 | 49 +EQ | 4 | + spidatain<7>.D = spidatain<6>; + spidatain<7>.CLK = !$OpTx$INV$22__$INT; + spidatain<7>.AR = !cpu_Nres; + spidatain<7>.CE = shiftcnt<0> & shifting2; + +MACROCELL | 3 | 16 | int_sclk +ATTRIBUTES | 8651698 | 0 +INPUTS | 8 | cpol | cpu_Nres | cpha | shiftcnt<0> | shiftdone | shifting2 | $OpTx$INV$22__$INT | ier.EXP +INPUTMC | 7 | 0 | 15 | 0 | 17 | 3 | 2 | 2 | 2 | 2 | 0 | 2 | 3 | 3 | 15 +INPUTP | 1 | 49 +IMPORTS | 1 | 3 | 15 +EQ | 9 | + spi_sclk.D = cpol + $ cpu_Nres & !cpha & shiftcnt<0> & !shiftdone & + shifting2 +;Imported pterms FB4_16 + # cpu_Nres & cpha & !shiftcnt<0> & !shiftdone & + shifting2; + spi_sclk.CLK = !$OpTx$INV$22__$INT; + spi_sclk.AP = !cpu_Nres & cpol; + spi_sclk.AR = !cpu_Nres & !cpol; + +MACROCELL | 2 | 15 | shiftcnt<3> +ATTRIBUTES | 4326192 | 0 +OUTPUTMC | 5 | 1 | 1 | 2 | 15 | 2 | 2 | 1 | 0 | 1 | 2 +INPUTS | 7 | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<3> | $OpTx$INV$22__$INT | cpu_Nres +INPUTMC | 6 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 0 | 2 | 15 | 2 | 3 +INPUTP | 1 | 49 +EQ | 5 | + shiftcnt<3>.T = shiftcnt<3> & !shifting2 + # shiftcnt<2> & shiftcnt<0> & shiftcnt<1> & + shifting2; + shiftcnt<3>.CLK = !$OpTx$INV$22__$INT; + shiftcnt<3>.AR = !cpu_Nres; + +MACROCELL | 2 | 16 | shiftcnt<2> +ATTRIBUTES | 4326192 | 0 +OUTPUTMC | 6 | 1 | 1 | 2 | 15 | 2 | 16 | 2 | 2 | 1 | 0 | 1 | 2 +INPUTS | 6 | shiftcnt<0> | shiftcnt<1> | shifting2 | shiftcnt<2> | $OpTx$INV$22__$INT | cpu_Nres +INPUTMC | 5 | 3 | 2 | 3 | 9 | 2 | 0 | 2 | 16 | 2 | 3 +INPUTP | 1 | 49 +EQ | 4 | + shiftcnt<2>.T = shiftcnt<2> & !shifting2 + # shiftcnt<0> & shiftcnt<1> & shifting2; + shiftcnt<2>.CLK = !$OpTx$INV$22__$INT; + shiftcnt<2>.AR = !cpu_Nres; + +MACROCELL | 3 | 2 | shiftcnt<0> +ATTRIBUTES | 8520496 | 0 +OUTPUTMC | 15 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 2 | 3 | 15 +INPUTS | 4 | shiftcnt<0> | shifting2 | $OpTx$INV$22__$INT | cpu_Nres +INPUTMC | 3 | 3 | 2 | 2 | 0 | 2 | 3 +INPUTP | 1 | 49 +EQ | 3 | + shiftcnt<0>.D = !shiftcnt<0> & shifting2; + shiftcnt<0>.CLK = !$OpTx$INV$22__$INT; + shiftcnt<0>.AR = !cpu_Nres; + +MACROCELL | 3 | 9 | shiftcnt<1> +ATTRIBUTES | 8520496 | 0 +OUTPUTMC | 7 | 1 | 1 | 2 | 15 | 2 | 16 | 3 | 9 | 2 | 2 | 1 | 0 | 1 | 2 +INPUTS | 5 | shiftcnt<0> | shiftcnt<1> | shifting2 | $OpTx$INV$22__$INT | cpu_Nres +INPUTMC | 4 | 3 | 2 | 3 | 9 | 2 | 0 | 2 | 3 +INPUTP | 1 | 49 +EQ | 4 | + shiftcnt<1>.D = shiftcnt<0> & !shiftcnt<1> & shifting2 + # !shiftcnt<0> & shiftcnt<1> & shifting2; + shiftcnt<1>.CLK = !$OpTx$INV$22__$INT; + shiftcnt<1>.AR = !cpu_Nres; + +MACROCELL | 2 | 2 | shiftdone +ATTRIBUTES | 8520496 | 0 +OUTPUTMC | 7 | 1 | 1 | 3 | 16 | 3 | 0 | 2 | 0 | 1 | 0 | 1 | 2 | 3 | 15 +INPUTS | 6 | shiftcnt<3> | shiftcnt<2> | shiftcnt<0> | shiftcnt<1> | $OpTx$INV$22__$INT | cpu_Nres +INPUTMC | 5 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 3 +INPUTP | 1 | 49 +EQ | 4 | + shiftdone.D = shiftcnt<3> & shiftcnt<2> & shiftcnt<0> & + shiftcnt<1>; + shiftdone.CLK = !$OpTx$INV$22__$INT; + shiftdone.AR = !cpu_Nres; + +MACROCELL | 2 | 5 | start_shifting +ATTRIBUTES | 4326192 | 0 +OUTPUTMC | 5 | 2 | 5 | 2 | 1 | 2 | 0 | 3 | 13 | 2 | 3 +INPUTS | 8 | frx | start_shifting | cpu_a<1> | cpu_a<0> | cpu_rnw | cs1 | Ncs2 | start_shifting/start_shifting_RSTF__$INT +INPUTMC | 3 | 0 | 9 | 2 | 5 | 1 | 0 +INPUTP | 5 | 59 | 52 | 24 | 50 | 46 +EQ | 4 | + start_shifting.T = !cpu_rnw & !start_shifting & !cpu_a<1> & !cpu_a<0> + # frx & !start_shifting & !cpu_a<1> & !cpu_a<0>; + !start_shifting.CLK = cs1 & !Ncs2; + start_shifting.AR = !start_shifting/start_shifting_RSTF__$INT; + +MACROCELL | 3 | 0 | tc +ATTRIBUTES | 8520672 | 0 +OUTPUTMC | 3 | 2 | 7 | 2 | 17 | 3 | 17 +INPUTS | 9 | cs1 | Ncs2 | shiftdone | cpu_a<1> | cpu_a<0> | spi_Nsel<0> | spi_miso<0> | spi_Nsel<1> | spi_miso<1> +INPUTMC | 3 | 2 | 2 | 3 | 10 | 3 | 7 +INPUTP | 6 | 50 | 46 | 59 | 52 | 10 | 9 +EXPORTS | 1 | 3 | 17 +EQ | 6 | + tc.D = Gnd; + !tc.CLK = cs1 & !Ncs2; + tc.AP = shiftdone; + tc.CE = !cpu_a<1> & !cpu_a<0>; + tc.EXP = !spi_Nsel<0> & spi_miso<0> + # !spi_Nsel<1> & spi_miso<1> + +MACROCELL | 0 | 3 | spidataout<0> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 0 | 3 | 1 | 2 +INPUTS | 8 | spidataout<0> | cpu_a<1> | cpu_a<0> | cpu_d<0>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 3 +INPUTP | 7 | 59 | 52 | 12 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<0>.T = spidataout<0> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<0>.PIN + # !spidataout<0> & !cpu_a<1> & !cpu_a<0> & + cpu_d<0>.PIN; + !spidataout<0>.CLK = cs1 & !Ncs2; + spidataout<0>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 0 | 2 | spidataout<1> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 1 | 1 | 0 | 2 +INPUTS | 8 | spidataout<1> | cpu_a<1> | cpu_a<0> | cpu_d<1>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 2 +INPUTP | 7 | 59 | 52 | 13 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<1>.T = spidataout<1> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<1>.PIN + # !spidataout<1> & !cpu_a<1> & !cpu_a<0> & + cpu_d<1>.PIN; + !spidataout<1>.CLK = cs1 & !Ncs2; + spidataout<1>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 0 | 1 | spidataout<2> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 0 | 1 | 1 | 2 +INPUTS | 8 | spidataout<2> | cpu_a<1> | cpu_a<0> | cpu_d<2>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 1 +INPUTP | 7 | 59 | 52 | 15 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<2>.T = spidataout<2> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<2>.PIN + # !spidataout<2> & !cpu_a<1> & !cpu_a<0> & + cpu_d<2>.PIN; + !spidataout<2>.CLK = cs1 & !Ncs2; + spidataout<2>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 0 | 0 | spidataout<3> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 1 | 0 | 0 | 0 +INPUTS | 8 | spidataout<3> | cpu_a<1> | cpu_a<0> | cpu_d<3>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 0 | 0 +INPUTP | 7 | 59 | 52 | 26 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<3>.T = spidataout<3> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<3>.PIN + # !spidataout<3> & !cpu_a<1> & !cpu_a<0> & + cpu_d<3>.PIN; + !spidataout<3>.CLK = cs1 & !Ncs2; + spidataout<3>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 3 | 8 | spidataout<4> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 3 | 8 | 1 | 2 +INPUTS | 8 | spidataout<4> | cpu_a<1> | cpu_a<0> | cpu_d<4>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 8 +INPUTP | 7 | 59 | 52 | 27 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<4>.T = spidataout<4> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<4>.PIN + # !spidataout<4> & !cpu_a<1> & !cpu_a<0> & + cpu_d<4>.PIN; + !spidataout<4>.CLK = cs1 & !Ncs2; + spidataout<4>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 3 | 6 | spidataout<5> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 1 | 1 | 3 | 6 +INPUTS | 8 | spidataout<5> | cpu_a<1> | cpu_a<0> | cpu_d<5>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 6 +INPUTP | 7 | 59 | 52 | 29 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<5>.T = spidataout<5> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<5>.PIN + # !spidataout<5> & !cpu_a<1> & !cpu_a<0> & + cpu_d<5>.PIN; + !spidataout<5>.CLK = cs1 & !Ncs2; + spidataout<5>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 3 | 5 | spidataout<6> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 3 | 5 | 1 | 2 +INPUTS | 8 | spidataout<6> | cpu_a<1> | cpu_a<0> | cpu_d<6>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 5 +INPUTP | 7 | 59 | 52 | 31 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<6>.T = spidataout<6> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<6>.PIN + # !spidataout<6> & !cpu_a<1> & !cpu_a<0> & + cpu_d<6>.PIN; + !spidataout<6>.CLK = cs1 & !Ncs2; + spidataout<6>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 3 | 3 | spidataout<7> +ATTRIBUTES | 4326240 | 0 +OUTPUTMC | 2 | 1 | 0 | 3 | 3 +INPUTS | 8 | spidataout<7> | cpu_a<1> | cpu_a<0> | cpu_d<7>.PIN | cs1 | Ncs2 | cpu_Nres | cpu_rnw +INPUTMC | 1 | 3 | 3 +INPUTP | 7 | 59 | 52 | 33 | 50 | 46 | 49 | 24 +EQ | 6 | + spidataout<7>.T = spidataout<7> & !cpu_a<1> & !cpu_a<0> & + !cpu_d<7>.PIN + # !spidataout<7> & !cpu_a<1> & !cpu_a<0> & + cpu_d<7>.PIN; + !spidataout<7>.CLK = cs1 & !Ncs2; + spidataout<7>.CE = cpu_Nres & !cpu_rnw; + +MACROCELL | 0 | 4 | int_dout<0> +ATTRIBUTES | 265986 | 0 +INPUTS | 10 | cpu_rnw | spidatain<0> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | divisor<0> | cpha | spi_Nsel<0> +INPUTMC | 4 | 3 | 17 | 0 | 13 | 0 | 17 | 3 | 10 +INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20 +EQ | 9 | + cpu_d<0> = cpu_rnw & spi_Nsel<0> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & cpha & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & divisor<0> & cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<0> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2; + cpu_d<0>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 0 | 5 | int_dout<1> +ATTRIBUTES | 265986 | 0 +INPUTS | 10 | cpu_rnw | spidatain<1> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | divisor<1> | cpol | spi_Nsel<1> +INPUTMC | 4 | 2 | 14 | 0 | 12 | 0 | 15 | 3 | 7 +INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20 +EQ | 9 | + cpu_d<1> = cpu_rnw & spi_Nsel<1> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & cpol & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & divisor<1> & cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<1> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2; + cpu_d<1>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 0 | 7 | int_dout<2> +ATTRIBUTES | 265986 | 0 +INPUTS | 10 | cpu_rnw | spidatain<2> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | divisor<2> | ece | spi_Nsel<2> +INPUTMC | 4 | 2 | 13 | 0 | 11 | 0 | 10 | 3 | 4 +INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20 +EQ | 9 | + cpu_d<2> = cpu_rnw & spi_Nsel<2> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & ece & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & divisor<2> & cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<2> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2; + cpu_d<2>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 0 | 14 | int_dout<3> +ATTRIBUTES | 265986 | 0 +INPUTS | 9 | cpu_rnw | spidatain<3> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | tmo | spi_Nsel<3> +INPUTMC | 3 | 2 | 12 | 0 | 6 | 3 | 1 +INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20 +EQ | 7 | + cpu_d<3> = cpu_rnw & spi_Nsel<3> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & tmo & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<3> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2; + cpu_d<3>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 0 | 16 | int_dout<4> +ATTRIBUTES | 265986 | 0 +INPUTS | 10 | cpu_rnw | spidatain<4> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | spi_int<0> | frx | slaveinten<0> +INPUTMC | 3 | 2 | 11 | 0 | 9 | 0 | 8 +INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 20 | 7 +EQ | 9 | + cpu_d<4> = cpu_rnw & frx & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & slaveinten<0> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<4> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 & + !spi_int<0> & cpu_Nphi2; + cpu_d<4>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 2 | 1 | int_dout<5> +ATTRIBUTES | 265986 | 0 +INPUTS | 11 | cpu_rnw | start_shifting | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | shifting2 | slaveinten<1> | spidatain<5> | shifting2.EXP +INPUTMC | 5 | 2 | 5 | 2 | 0 | 3 | 14 | 2 | 10 | 2 | 0 +INPUTP | 6 | 24 | 59 | 52 | 50 | 46 | 20 +IMPORTS | 1 | 2 | 0 +EQ | 12 | + cpu_d<5> = cpu_rnw & slaveinten<1> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<5> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & start_shifting & !cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & !cpu_a<1> & cpu_a<0> & cs1 & !Ncs2 & + shifting2 & cpu_Nphi2 +;Imported pterms FB3_1 + # cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 & + !spi_int<1> & cpu_Nphi2; + cpu_d<5>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 2 | 4 | int_dout<6> +ATTRIBUTES | 265986 | 0 +INPUTS | 10 | cpu_rnw | spidatain<6> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | spi_int<2> | ier | slaveinten<2> +INPUTMC | 3 | 2 | 9 | 3 | 15 | 3 | 12 +INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 20 | 92 +EQ | 9 | + cpu_d<6> = cpu_rnw & ier & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & slaveinten<2> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<6> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 & + !spi_int<2> & cpu_Nphi2; + cpu_d<6>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 2 | 7 | int_dout<7> +ATTRIBUTES | 265986 | 0 +INPUTS | 10 | cpu_rnw | spidatain<7> | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | cpu_Nphi2 | spi_int<3> | tc | slaveinten<3> +INPUTMC | 3 | 2 | 6 | 3 | 0 | 3 | 11 +INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 20 | 11 +EQ | 9 | + cpu_d<7> = cpu_rnw & slaveinten<3> & cpu_a<1> & cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & spidatain<7> & !cpu_a<1> & !cpu_a<0> & + cs1 & !Ncs2 & cpu_Nphi2 + # cpu_rnw & tc & !cpu_a<1> & cpu_a<0> & cs1 & + !Ncs2 & cpu_Nphi2 + # cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 & + !spi_int<3> & cpu_Nphi2; + cpu_d<7>.OE = cpu_rnw & cs1 & !Ncs2 & cpu_Nphi2; + +MACROCELL | 2 | 0 | shifting2 +ATTRIBUTES | 8520480 | 0 +OUTPUTMC | 20 | 1 | 1 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 1 | 3 | 13 | 2 | 3 | 1 | 0 | 1 | 2 | 3 | 15 +INPUTS | 10 | shiftdone | start_shifting | $OpTx$INV$22__$INT | cpu_rnw | cpu_a<1> | cpu_a<0> | cs1 | Ncs2 | spi_int<1> | cpu_Nphi2 +INPUTMC | 3 | 2 | 2 | 2 | 5 | 2 | 3 +INPUTP | 7 | 24 | 59 | 52 | 50 | 46 | 3 | 20 +EXPORTS | 1 | 2 | 1 +EQ | 4 | + shifting2.D = !shiftdone & start_shifting; + shifting2.CLK = !$OpTx$INV$22__$INT; + shifting2.EXP = cpu_rnw & cpu_a<1> & !cpu_a<0> & cs1 & !Ncs2 & + !spi_int<1> & cpu_Nphi2 + +MACROCELL | 3 | 13 | diag_OBUF +ATTRIBUTES | 264962 | 0 +OUTPUTMC | 1 | 3 | 14 +INPUTS | 7 | spi_Nsel<0> | start_shifting | shifting2 | slaveinten<1> | cpu_a<1> | cpu_a<0> | cpu_d<5>.PIN +INPUTMC | 4 | 3 | 10 | 2 | 5 | 2 | 0 | 3 | 14 +INPUTP | 3 | 59 | 52 | 29 +EXPORTS | 1 | 3 | 14 +EQ | 3 | + diag = spi_Nsel<0> & !start_shifting & !shifting2; + diag_OBUF.EXP = slaveinten<1> & cpu_a<1> & cpu_a<0> & + !cpu_d<5>.PIN + +MACROCELL | 2 | 8 | cpu_Nirq_OBUFE +ATTRIBUTES | 265986 | 0 +INPUTS | 1 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST +INPUTMC | 1 | 2 | 17 +EQ | 2 | + cpu_Nirq = Gnd; + cpu_Nirq.OE = cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST; + +MACROCELL | 2 | 3 | $OpTx$INV$22__$INT +ATTRIBUTES | 133888 | 0 +OUTPUTMC | 16 | 1 | 1 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 2 | 2 | 0 +INPUTS | 5 | ece | cpu_Nphi2 | extclk | start_shifting | shifting2 +INPUTMC | 3 | 0 | 10 | 2 | 5 | 2 | 0 +INPUTP | 2 | 20 | 21 +EQ | 3 | + $OpTx$INV$22__$INT = ece & !extclk + # !ece & !cpu_Nphi2 + # !start_shifting & !shifting2; + +MACROCELL | 1 | 0 | start_shifting/start_shifting_RSTF__$INT +ATTRIBUTES | 133888 | 0 +OUTPUTMC | 2 | 2 | 5 | 1 | 1 +INPUTS | 8 | cpu_Nres | shiftdone | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | spidataout<3> | shifting2 | spidataout<7> +INPUTMC | 7 | 2 | 2 | 2 | 15 | 2 | 16 | 3 | 9 | 0 | 0 | 2 | 0 | 3 | 3 +INPUTP | 1 | 49 +EXPORTS | 1 | 1 | 1 +EQ | 5 | + start_shifting/start_shifting_RSTF__$INT = cpu_Nres & !shiftdone; + start_shifting/start_shifting_RSTF__$INT.EXP = shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & + !shiftdone & !spidataout<3> & shifting2 + # !shiftcnt<3> & !shiftcnt<2> & !shiftcnt<1> & + !shiftdone & !spidataout<7> & shifting2 + +MACROCELL | 2 | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST +ATTRIBUTES | 133888 | 0 +OUTPUTMC | 1 | 2 | 8 +INPUTS | 10 | ier | tc | slaveinten<3> | spi_int<3> | slaveinten<2> | spi_int<2> | slaveinten<0> | spi_int<0> | slaveinten<1> | spi_int<1> +INPUTMC | 6 | 3 | 15 | 3 | 0 | 3 | 11 | 3 | 12 | 0 | 8 | 3 | 14 +INPUTP | 4 | 11 | 92 | 7 | 3 +EQ | 5 | + cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST = ier & tc + # slaveinten<0> & !spi_int<0> + # slaveinten<1> & !spi_int<1> + # slaveinten<2> & !spi_int<2> + # slaveinten<3> & !spi_int<3>; + +MACROCELL | 1 | 2 | EXP6_ +ATTRIBUTES | 2048 | 0 +OUTPUTMC | 1 | 1 | 1 +INPUTS | 9 | shiftcnt<3> | shiftcnt<2> | shiftcnt<1> | shiftdone | spidataout<0> | shifting2 | spidataout<2> | spidataout<4> | spidataout<6> +INPUTMC | 9 | 2 | 15 | 2 | 16 | 3 | 9 | 2 | 2 | 0 | 3 | 2 | 0 | 0 | 1 | 3 | 8 | 3 | 5 +EXPORTS | 1 | 1 | 1 +EQ | 8 | + EXP6_.EXP = shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<0> & shifting2 + # shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<2> & shifting2 + # !shiftcnt<3> & shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<4> & shifting2 + # !shiftcnt<3> & !shiftcnt<2> & shiftcnt<1> & + !shiftdone & !spidataout<6> & shifting2 + +PIN | cpu_Nres | 64 | 0 | N/A | 49 | 41 | 1 | 1 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 3 | 17 | 2 | 14 | 2 | 13 | 2 | 12 | 2 | 11 | 2 | 10 | 2 | 9 | 2 | 6 | 3 | 16 | 2 | 15 | 2 | 16 | 3 | 2 | 3 | 9 | 2 | 2 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 1 | 0 +PIN | cpu_rnw | 64 | 0 | N/A | 24 | 35 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 +PIN | Ncs2 | 64 | 0 | N/A | 46 | 36 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 +PIN | cs1 | 64 | 0 | N/A | 50 | 36 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 +PIN | cpu_a<1> | 64 | 0 | N/A | 59 | 37 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 | 3 | 13 +PIN | cpu_a<0> | 64 | 0 | N/A | 52 | 37 | 3 | 10 | 3 | 7 | 3 | 4 | 3 | 1 | 0 | 15 | 0 | 10 | 0 | 17 | 0 | 9 | 3 | 15 | 0 | 8 | 3 | 14 | 3 | 12 | 3 | 11 | 0 | 6 | 0 | 13 | 0 | 12 | 0 | 11 | 2 | 5 | 3 | 0 | 0 | 3 | 0 | 2 | 0 | 1 | 0 | 0 | 3 | 8 | 3 | 6 | 3 | 5 | 3 | 3 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 0 | 3 | 13 +PIN | spi_miso<3> | 64 | 0 | N/A | 89 | 1 | 3 | 17 +PIN | spi_miso<2> | 64 | 0 | N/A | 90 | 1 | 3 | 17 +PIN | spi_miso<1> | 64 | 0 | N/A | 9 | 1 | 3 | 0 +PIN | spi_miso<0> | 64 | 0 | N/A | 10 | 1 | 3 | 0 +PIN | cpu_Nphi2 | 64 | 0 | N/A | 20 | 10 | 0 | 4 | 0 | 5 | 0 | 7 | 0 | 14 | 0 | 16 | 2 | 1 | 2 | 4 | 2 | 7 | 2 | 3 | 2 | 0 +PIN | spi_int<0> | 64 | 0 | N/A | 7 | 2 | 0 | 16 | 2 | 17 +PIN | spi_int<1> | 64 | 0 | N/A | 3 | 2 | 2 | 0 | 2 | 17 +PIN | spi_int<2> | 64 | 0 | N/A | 92 | 2 | 2 | 4 | 2 | 17 +PIN | spi_int<3> | 64 | 0 | N/A | 11 | 2 | 2 | 7 | 2 | 17 +PIN | extclk | 64 | 0 | N/A | 21 | 1 | 2 | 3 +PIN | spi_mosi | 536871040 | 0 | N/A | 87 +PIN | spi_Nsel<0> | 536871040 | 0 | N/A | 68 +PIN | spi_Nsel<1> | 536871040 | 0 | N/A | 65 +PIN | spi_Nsel<2> | 536871040 | 0 | N/A | 63 +PIN | spi_Nsel<3> | 536871040 | 0 | N/A | 62 +PIN | spi_sclk | 536871040 | 0 | N/A | 83 +PIN | diag | 536871040 | 0 | N/A | 72 +PIN | cpu_Nirq | 536871040 | 0 | N/A | 38 +PIN | cpu_d<0> | 536870976 | 0 | N/A | 12 | 4 | 3 | 10 | 0 | 17 | 0 | 13 | 0 | 3 +PIN | cpu_d<1> | 536870976 | 0 | N/A | 13 | 4 | 3 | 7 | 0 | 15 | 0 | 12 | 0 | 2 +PIN | cpu_d<2> | 536870976 | 0 | N/A | 15 | 4 | 3 | 4 | 0 | 10 | 0 | 11 | 0 | 1 +PIN | cpu_d<3> | 536870976 | 0 | N/A | 26 | 3 | 3 | 1 | 0 | 6 | 0 | 0 +PIN | cpu_d<4> | 536870976 | 0 | N/A | 27 | 3 | 0 | 9 | 0 | 8 | 3 | 8 +PIN | cpu_d<5> | 536870976 | 0 | N/A | 29 | 3 | 3 | 14 | 3 | 6 | 3 | 13 +PIN | cpu_d<6> | 536870976 | 0 | N/A | 31 | 4 | 3 | 15 | 3 | 12 | 3 | 5 | 3 | 14 +PIN | cpu_d<7> | 536870976 | 0 | N/A | 33 | 2 | 3 | 11 | 3 | 3 diff --git a/spi6502b.ngc b/spi6502b.ngc new file mode 100644 index 0000000..3660ee4 --- /dev/null +++ b/spi6502b.ngc @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e 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\ No newline at end of file diff --git a/spi6502b.ngr b/spi6502b.ngr new file mode 100644 index 0000000..54a3d6b --- /dev/null +++ b/spi6502b.ngr @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.2e 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b/spi6502b.prj @@ -0,0 +1 @@ +vhdl work SPI6502B1.1.vhd diff --git a/spi6502b.rpt b/spi6502b.rpt new file mode 100644 index 0000000..15dedb5 --- /dev/null +++ b/spi6502b.rpt @@ -0,0 +1,873 @@ + +cpldfit: version G.38 Xilinx Inc. + Fitter Report +Design Name: spi6502b Date: 5- 6-2017, 5:27PM +Device Used: XC9572XL-10-PC44 +Fitting Status: Successful + +**************************** Resource Summary **************************** + +Macrocells Product Terms Registers Pins Function Block +Used Used Used Used Inputs Used +56 /72 ( 78%) 247 /360 ( 69%) 43 /72 ( 60%) 32 /34 ( 94%) 127/216 ( 59%) + +PIN RESOURCES: + +Signal Type Required Mapped | Pin Type Used Remaining +------------------------------------|--------------------------------------- +Input : 16 16 | I/O : 26 2 +Output : 8 8 | GCK/IO : 3 0 +Bidirectional : 8 8 | GTS/IO : 2 0 +GCK : 0 0 | GSR/IO : 1 0 +GTS : 0 0 | +GSR : 0 0 | + ---- ---- + Total 32 32 + +MACROCELL RESOURCES: + +Total Macrocells Available 72 +Registered Macrocells 43 +Non-registered Macrocell driving I/O 10 + +GLOBAL RESOURCES: + +Global clock net(s) unused. +Global output enable net(s) unused. +Global set/reset net(s) unused. + +POWER DATA: + +There are 56 macrocells in high performance mode (MCHP). +There are 0 macrocells in low power mode (MCLP). +There are a total of 56 macrocells used (MC). + +End of Resource Summary + *************** Summary of Required Resources ****************** + +** LOGIC ** +Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init +Name Pt Used Mode Rate # Type Use State +$OpTx$INV$22__$INT 3 5 FB3_4 STD (b) (b) +cpha 5 8 FB1_18 STD (b) (b) RESET +cpol 5 8 FB1_16 STD (b) (b) RESET +cpu_Nirq 1 1 FB3_9 STD FAST 14 I/O O +cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST 5 10 FB3_18 STD (b) (b) +cpu_d<0> 5 10 FB1_5 STD FAST 2 I/O I/O +cpu_d<1> 5 10 FB1_6 STD FAST 3 I/O I/O +cpu_d<2> 5 10 FB1_8 STD FAST 4 I/O I/O +cpu_d<3> 4 9 FB1_15 STD FAST 8 I/O I/O +cpu_d<4> 5 10 FB1_17 STD FAST 9 I/O I/O +cpu_d<5> 6 11 FB3_2 STD FAST 11 I/O I/O +cpu_d<6> 5 10 FB3_5 STD FAST 12 I/O I/O +cpu_d<7> 5 10 FB3_8 STD FAST 13 I/O I/O +diag 1 3 FB4_14 STD FAST 29 I/O O +divisor<0> 5 8 FB1_14 STD 7 GCK/I/O I RESET +divisor<1> 5 8 FB1_13 STD (b) (b) RESET +divisor<2> 5 8 FB1_12 STD (b) (b) RESET +ece 5 8 FB1_11 STD 6 GCK/I/O I RESET +frx 5 8 FB1_10 STD (b) (b) RESET +ier 5 8 FB4_16 STD (b) (b) RESET +shiftcnt<0> 3 4 FB4_3 STD (b) (b) RESET +shiftcnt<1> 4 5 FB4_10 STD (b) (b) RESET +shiftcnt<2> 4 6 FB3_17 STD 22 I/O I RESET +shiftcnt<3> 4 7 FB3_16 STD 24 I/O I RESET +shiftdone 3 6 FB3_3 STD (b) (b) RESET +shifting2 2 3 FB3_1 STD (b) (b) RESET +slaveinten<0> 5 8 FB1_9 STD 5 GCK/I/O I RESET +slaveinten<1> 5 8 FB4_15 STD 33 I/O (b) RESET +slaveinten<2> 5 8 FB4_13 STD (b) (b) RESET +slaveinten<3> 5 8 FB4_12 STD (b) (b) RESET +spi_Nsel<0> 5 8 FB4_11 STD FAST 28 I/O O RESET +spi_Nsel<1> 5 8 FB4_8 STD FAST 27 I/O O RESET +spi_Nsel<2> 5 8 FB4_5 STD FAST 26 I/O O RESET +spi_Nsel<3> 5 8 FB4_2 STD FAST 25 I/O O RESET +spi_mosi 11 16 FB2_2 STD FAST 35 I/O O RESET +spi_sclk 6 7 FB4_17 STD FAST 34 I/O O RESET +spidatain<0> 7 12 FB4_18 STD (b) (b) RESET +spidatain<1> 4 5 FB3_15 STD 20 I/O I RESET +spidatain<2> 4 5 FB3_14 STD 19 I/O I RESET +spidatain<3> 4 5 FB3_13 STD (b) (b) RESET +spidatain<4> 4 5 FB3_12 STD (b) (b) RESET +spidatain<5> 4 5 FB3_11 STD 18 I/O I RESET +spidatain<6> 4 5 FB3_10 STD (b) (b) RESET +spidatain<7> 4 5 FB3_7 STD (b) (b) RESET +spidataout<0> 4 8 FB1_4 STD (b) (b) RESET +spidataout<1> 4 8 FB1_3 STD (b) (b) RESET +spidataout<2> 4 8 FB1_2 STD 1 I/O I RESET +spidataout<3> 4 8 FB1_1 STD (b) (b) RESET +spidataout<4> 4 8 FB4_9 STD (b) (b) RESET +spidataout<5> 4 8 FB4_7 STD (b) (b) RESET +spidataout<6> 4 8 FB4_6 STD (b) (b) RESET +spidataout<7> 4 8 FB4_4 STD (b) (b) RESET +start_shifting 4 8 FB3_6 STD (b) (b) RESET +start_shifting/start_shifting_RSTF__$INT 1 2 FB2_1 STD (b) (b) +tc 3 5 FB4_1 STD (b) (b) RESET +tmo 5 8 FB1_7 STD (b) (b) RESET + +** INPUTS ** +Signal Loc Pin Pin Pin +Name # Type Use +Ncs2 FB3_11 18 I/O I +cpu_Nphi2 FB1_9 5 GCK/I/O I +cpu_Nres FB3_14 19 I/O I +cpu_a<0> FB3_17 22 I/O I +cpu_a<1> FB3_16 24 I/O I +cpu_rnw FB1_14 7 GCK/I/O I +cs1 FB3_15 20 I/O I +extclk FB1_11 6 GCK/I/O I +spi_int<0> FB2_14 42 GTS/I/O I +spi_int<1> FB2_11 40 GTS/I/O I +spi_int<2> FB2_9 39 GSR/I/O I +spi_int<3> FB1_2 1 I/O I +spi_miso<0> FB2_17 44 I/O I +spi_miso<1> FB2_15 43 I/O I +spi_miso<2> FB2_8 38 I/O I +spi_miso<3> FB2_6 37 I/O I + +End of Resources + + *********************Function Block Resource Summary*********************** +Function # of FB Inputs Signals Total O/IO IO +Block Macrocells Used Used Pt Used Req Avail +FB1 18 35 35 85 0/5 9 +FB2 2 16 16 12 1/0 9 +FB3 18 38 38 70 1/3 9 +FB4 18 38 38 80 6/0 7 + ---- ----- ----- ----- + 56 247 8/8 34 + *********************************** FB1 *********************************** +Number of function block inputs used/remaining: 35/19 +Number of signals used by logic mapping into function block: 35 +Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin +Name Pt Pt Pt Pt Mode # Type Use +spidataout<3> 4 0 0 1 FB1_1 STD (b) (b) +spidataout<2> 4 0 0 1 FB1_2 STD 1 I/O I +spidataout<1> 4 0 0 1 FB1_3 STD (b) (b) +spidataout<0> 4 0 0 1 FB1_4 STD (b) (b) +cpu_d<0> 5 0 0 0 FB1_5 STD 2 I/O I/O +cpu_d<1> 5 0 0 0 FB1_6 STD 3 I/O I/O +tmo 5 0 0 0 FB1_7 STD (b) (b) +cpu_d<2> 5 0 0 0 FB1_8 STD 4 I/O I/O +slaveinten<0> 5 0 0 0 FB1_9 STD 5 GCK/I/O I +frx 5 0 0 0 FB1_10 STD (b) (b) +ece 5 0 0 0 FB1_11 STD 6 GCK/I/O I +divisor<2> 5 0 0 0 FB1_12 STD (b) (b) +divisor<1> 5 0 0 0 FB1_13 STD (b) (b) +divisor<0> 5 0 0 0 FB1_14 STD 7 GCK/I/O I +cpu_d<3> 4 0 0 1 FB1_15 STD 8 I/O I/O +cpol 5 0 0 0 FB1_16 STD (b) (b) +cpu_d<4> 5 0 0 0 FB1_17 STD 9 I/O I/O +cpha 5 0 0 0 FB1_18 STD (b) (b) + +Signals Used by Logic in Function Block + 1: cpu_d<0>.PIN 13: cpu_rnw 25: spi_int<0> + 2: cpu_d<1>.PIN 14: cs1 26: spidatain<0> + 3: cpu_d<2>.PIN 15: divisor<0> 27: spidatain<1> + 4: cpu_d<3>.PIN 16: divisor<1> 28: spidatain<2> + 5: cpu_d<4>.PIN 17: divisor<2> 29: spidatain<3> + 6: Ncs2 18: ece 30: spidatain<4> + 7: cpha 19: frx 31: spidataout<0> + 8: cpol 20: slaveinten<0> 32: spidataout<1> + 9: cpu_Nphi2 21: spi_Nsel<0> 33: spidataout<2> + 10: cpu_Nres 22: spi_Nsel<1> 34: spidataout<3> + 11: cpu_a<0> 23: spi_Nsel<2> 35: tmo + 12: cpu_a<1> 24: spi_Nsel<3> + +Signal 1 2 3 4 Signals FB +Name 0----+----0----+----0----+----0----+----0 Used Inputs +spidataout<3> ...X.X...XXXXX...................X...... 8 8 +spidataout<2> ..X..X...XXXXX..................X....... 8 8 +spidataout<1> .X...X...XXXXX.................X........ 8 8 +spidataout<0> X....X...XXXXX................X......... 8 8 +cpu_d<0> .....XX.X.XXXXX.....X....X.............. 10 10 +cpu_d<1> .....X.XX.XXXX.X.....X....X............. 10 10 +tmo ...X.X...XXXXX....................X..... 8 8 +cpu_d<2> .....X..X.XXXX..XX....X....X............ 10 10 +slaveinten<0> ....XX...XXXXX.....X.................... 8 8 +frx ....XX...XXXXX....X..................... 8 8 +ece ..X..X...XXXXX...X...................... 8 8 +divisor<2> ..X..X...XXXXX..X....................... 8 8 +divisor<1> .X...X...XXXXX.X........................ 8 8 +divisor<0> X....X...XXXXXX......................... 8 8 +cpu_d<3> .....X..X.XXXX.........X....X.....X..... 9 9 +cpol .X...X.X.XXXXX.......................... 8 8 +cpu_d<4> .....X..X.XXXX....XX....X....X.......... 10 10 +cpha X....XX..XXXXX.......................... 8 8 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 +Legend: +Total Pt - Total product terms used by the macrocell signal +Imp Pt - Product terms imported from other macrocells +Exp Pt - Product terms exported to other macrocells + in direction shown +Unused Pt - Unused local product terms remaining in macrocell +Loc - Location where logic was mapped in device +Pwr Mode - Macrocell power mode +Pin Type/Use - I - Input GCK - Global Clock + O - Output GTS - Global Output Enable + (b) - Buried macrocell GSR - Global Set/Reset +X(@) - Signal used as input (wire-AND input) to the macrocell logic. + The number of Signals Used may exceed the number of FB Inputs Used due + to wire-ANDing in the switch matrix. + *********************************** FB2 *********************************** +Number of function block inputs used/remaining: 16/38 +Number of signals used by logic mapping into function block: 16 +Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin +Name Pt Pt Pt Pt Mode # Type Use +start_shifting/start_shifting_RSTF__$INT + 1 0 \/2 2 FB2_1 STD (b) (b) +spi_mosi 11 6<- 0 0 FB2_2 STD 35 I/O O +(unused) 0 0 /\4 1 FB2_3 (b) (b) +(unused) 0 0 0 5 FB2_4 (b) +(unused) 0 0 0 5 FB2_5 36 I/O +(unused) 0 0 0 5 FB2_6 37 I/O I +(unused) 0 0 0 5 FB2_7 (b) +(unused) 0 0 0 5 FB2_8 38 I/O I +(unused) 0 0 0 5 FB2_9 39 GSR/I/O I +(unused) 0 0 0 5 FB2_10 (b) +(unused) 0 0 0 5 FB2_11 40 GTS/I/O I +(unused) 0 0 0 5 FB2_12 (b) +(unused) 0 0 0 5 FB2_13 (b) +(unused) 0 0 0 5 FB2_14 42 GTS/I/O I +(unused) 0 0 0 5 FB2_15 43 I/O I +(unused) 0 0 0 5 FB2_16 (b) +(unused) 0 0 0 5 FB2_17 44 I/O I +(unused) 0 0 0 5 FB2_18 (b) + +Signals Used by Logic in Function Block + 1: $OpTx$INV$22__$INT + 7: shifting2 12: spidataout<4> + 2: cpu_Nres 8: spidataout<0> 13: spidataout<5> + 3: shiftcnt<1> 9: spidataout<1> 14: spidataout<6> + 4: shiftcnt<2> 10: spidataout<2> 15: spidataout<7> + 5: shiftcnt<3> 11: spidataout<3> 16: tmo + 6: shiftdone + +Signal 1 2 3 4 Signals FB +Name 0----+----0----+----0----+----0----+----0 Used Inputs +start_shifting/start_shifting_RSTF__$INT + .X...X.................................. 2 2 +spi_mosi XXXXXXXXXXXXXXXX........................ 16 16 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 +Legend: +Total Pt - Total product terms used by the macrocell signal +Imp Pt - Product terms imported from other macrocells +Exp Pt - Product terms exported to other macrocells + in direction shown +Unused Pt - Unused local product terms remaining in macrocell +Loc - Location where logic was mapped in device +Pwr Mode - Macrocell power mode +Pin Type/Use - I - Input GCK - Global Clock + O - Output GTS - Global Output Enable + (b) - Buried macrocell GSR - Global Set/Reset +X(@) - Signal used as input (wire-AND input) to the macrocell logic. + The number of Signals Used may exceed the number of FB Inputs Used due + to wire-ANDing in the switch matrix. + *********************************** FB3 *********************************** +Number of function block inputs used/remaining: 38/16 +Number of signals used by logic mapping into function block: 38 +Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin +Name Pt Pt Pt Pt Mode # Type Use +shifting2 2 0 \/1 2 FB3_1 STD (b) (b) +cpu_d<5> 6 1<- 0 0 FB3_2 STD 11 I/O I/O +shiftdone 3 0 0 2 FB3_3 STD (b) (b) +$OpTx$INV$22__$INT 3 0 0 2 FB3_4 STD (b) (b) +cpu_d<6> 5 0 0 0 FB3_5 STD 12 I/O I/O +start_shifting 4 0 0 1 FB3_6 STD (b) (b) +spidatain<7> 4 0 0 1 FB3_7 STD (b) (b) +cpu_d<7> 5 0 0 0 FB3_8 STD 13 I/O I/O +cpu_Nirq 1 0 0 4 FB3_9 STD 14 I/O O +spidatain<6> 4 0 0 1 FB3_10 STD (b) (b) +spidatain<5> 4 0 0 1 FB3_11 STD 18 I/O I +spidatain<4> 4 0 0 1 FB3_12 STD (b) (b) +spidatain<3> 4 0 0 1 FB3_13 STD (b) (b) +spidatain<2> 4 0 0 1 FB3_14 STD 19 I/O I +spidatain<1> 4 0 0 1 FB3_15 STD 20 I/O I +shiftcnt<3> 4 0 0 1 FB3_16 STD 24 I/O I +shiftcnt<2> 4 0 0 1 FB3_17 STD 22 I/O I +cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST + 5 0 0 0 FB3_18 STD (b) (b) + +Signals Used by Logic in Function Block + 1: $OpTx$INV$22__$INT + 14: shiftcnt<0> 27: spi_int<3> + 2: Ncs2 15: shiftcnt<1> 28: spidatain<0> + 3: cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST + 16: shiftcnt<2> 29: spidatain<1> + 4: cpu_Nphi2 17: shiftcnt<3> 30: spidatain<2> + 5: cpu_Nres 18: shiftdone 31: spidatain<3> + 6: cpu_a<0> 19: shifting2 32: spidatain<4> + 7: cpu_a<1> 20: slaveinten<0> 33: spidatain<5> + 8: cpu_rnw 21: slaveinten<1> 34: spidatain<6> + 9: cs1 22: slaveinten<2> 35: spidatain<7> + 10: ece 23: slaveinten<3> 36: start_shifting + 11: extclk 24: spi_int<0> 37: start_shifting/start_shifting_RSTF__$INT + 12: frx 25: spi_int<1> 38: tc + 13: ier 26: spi_int<2> + +Signal 1 2 3 4 Signals FB +Name 0----+----0----+----0----+----0----+----0 Used Inputs +shifting2 X................X.................X.... 3 3 +cpu_d<5> .X.X.XXXX.........X.X...X.......X..X.... 11 11 +shiftdone X...X........XXXX....................... 6 6 +$OpTx$INV$22__$INT ...X.....XX.......X................X.... 5 5 +cpu_d<6> .X.X.XXXX...X........X...X.......X...... 10 10 +start_shifting .X...XXXX..X.......................XX... 8 8 +spidatain<7> X...X........X....X..............X...... 5 5 +cpu_d<7> .X.X.XXXX.............X...X.......X..X.. 10 10 +cpu_Nirq ..X..................................... 1 1 +spidatain<6> X...X........X....X.............X....... 5 5 +spidatain<5> X...X........X....X............X........ 5 5 +spidatain<4> X...X........X....X...........X......... 5 5 +spidatain<3> X...X........X....X..........X.......... 5 5 +spidatain<2> X...X........X....X.........X........... 5 5 +spidatain<1> X...X........X....X........X............ 5 5 +shiftcnt<3> X...X........XXXX.X..................... 7 7 +shiftcnt<2> X...X........XXX..X..................... 6 6 +cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST + ............X......XXXXXXXX..........X.. 10 10 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 +Legend: +Total Pt - Total product terms used by the macrocell signal +Imp Pt - Product terms imported from other macrocells +Exp Pt - Product terms exported to other macrocells + in direction shown +Unused Pt - Unused local product terms remaining in macrocell +Loc - Location where logic was mapped in device +Pwr Mode - Macrocell power mode +Pin Type/Use - I - Input GCK - Global Clock + O - Output GTS - Global Output Enable + (b) - Buried macrocell GSR - Global Set/Reset +X(@) - Signal used as input (wire-AND input) to the macrocell logic. + The number of Signals Used may exceed the number of FB Inputs Used due + to wire-ANDing in the switch matrix. + *********************************** FB4 *********************************** +Number of function block inputs used/remaining: 38/16 +Number of signals used by logic mapping into function block: 38 +Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin +Name Pt Pt Pt Pt Mode # Type Use +tc 3 0 /\2 0 FB4_1 STD (b) (b) +spi_Nsel<3> 5 0 0 0 FB4_2 STD 25 I/O O +shiftcnt<0> 3 0 0 2 FB4_3 STD (b) (b) +spidataout<7> 4 0 0 1 FB4_4 STD (b) (b) +spi_Nsel<2> 5 0 0 0 FB4_5 STD 26 I/O O +spidataout<6> 4 0 0 1 FB4_6 STD (b) (b) +spidataout<5> 4 0 0 1 FB4_7 STD (b) (b) +spi_Nsel<1> 5 0 0 0 FB4_8 STD 27 I/O O +spidataout<4> 4 0 0 1 FB4_9 STD (b) (b) +shiftcnt<1> 4 0 0 1 FB4_10 STD (b) (b) +spi_Nsel<0> 5 0 0 0 FB4_11 STD 28 I/O O +slaveinten<3> 5 0 0 0 FB4_12 STD (b) (b) +slaveinten<2> 5 0 0 0 FB4_13 STD (b) (b) +diag 1 0 \/1 3 FB4_14 STD 29 I/O O +slaveinten<1> 5 1<- \/1 0 FB4_15 STD 33 I/O (b) +ier 5 1<- \/1 0 FB4_16 STD (b) (b) +spi_sclk 6 1<- 0 0 FB4_17 STD 34 I/O O +spidatain<0> 7 2<- 0 0 FB4_18 STD (b) (b) + +Signals Used by Logic in Function Block + 1: $OpTx$INV$22__$INT + 14: cpu_a<0> 27: spi_Nsel<1> + 2: cpu_d<0>.PIN 15: cpu_a<1> 28: spi_Nsel<2> + 3: cpu_d<1>.PIN 16: cpu_rnw 29: spi_Nsel<3> + 4: cpu_d<2>.PIN 17: cs1 30: spi_miso<0> + 5: cpu_d<3>.PIN 18: ier 31: spi_miso<1> + 6: cpu_d<4>.PIN 19: shiftcnt<0> 32: spi_miso<2> + 7: cpu_d<5>.PIN 20: shiftcnt<1> 33: spi_miso<3> + 8: cpu_d<6>.PIN 21: shiftdone 34: spidataout<4> + 9: cpu_d<7>.PIN 22: shifting2 35: spidataout<5> + 10: Ncs2 23: slaveinten<1> 36: spidataout<6> + 11: cpha 24: slaveinten<2> 37: spidataout<7> + 12: cpol 25: slaveinten<3> 38: start_shifting + 13: cpu_Nres 26: spi_Nsel<0> + +Signal 1 2 3 4 Signals FB +Name 0----+----0----+----0----+----0----+----0 Used Inputs +tc .........X...XX.X...X................... 5 5 +spi_Nsel<3> ....X....X..XXXXX...........X........... 8 8 +shiftcnt<0> X...........X.....X..X.................. 4 4 +spidataout<7> ........XX..XXXXX...................X... 8 8 +spi_Nsel<2> ...X.....X..XXXXX..........X............ 8 8 +spidataout<6> .......X.X..XXXXX..................X.... 8 8 +spidataout<5> ......X..X..XXXXX.................X..... 8 8 +spi_Nsel<1> ..X......X..XXXXX.........X............. 8 8 +spidataout<4> .....X...X..XXXXX................X...... 8 8 +shiftcnt<1> X...........X.....XX.X.................. 5 5 +spi_Nsel<0> .X.......X..XXXXX........X.............. 8 8 +slaveinten<3> ........XX..XXXXX.......X............... 8 8 +slaveinten<2> .......X.X..XXXXX......X................ 8 8 +diag .....................X...X...........X.. 3 3 +slaveinten<1> ......X..X..XXXXX.....X................. 8 8 +ier .......X.X..XXXXXX...................... 8 8 +spi_sclk X.........XXX.....X.XX.................. 7 7 +spidatain<0> X...........X.....X..X...XXXXXXXX....... 12 12 + 0----+----1----+----2----+----3----+----4 + 0 0 0 0 +Legend: +Total Pt - Total product terms used by the macrocell signal +Imp Pt - Product terms imported from other macrocells +Exp Pt - Product terms exported to other macrocells + in direction shown +Unused Pt - Unused local product terms remaining in macrocell +Loc - Location where logic was mapped in device +Pwr Mode - Macrocell power mode +Pin Type/Use - I - Input GCK - Global Clock + O - Output GTS - Global Output Enable + (b) - Buried macrocell GSR - Global Set/Reset +X(@) - Signal used as input (wire-AND input) to the macrocell logic. + The number of Signals Used may exceed the number of FB Inputs Used due + to wire-ANDing in the switch matrix. + ;;-----------------------------------------------------------------;; +; Implemented Equations. + + +$OpTx$INV$22__$INT <= ((ece AND NOT extclk) + OR (NOT ece AND NOT cpu_Nphi2) + OR (NOT start_shifting AND NOT shifting2)); + + + +FTCPE_cpha: FTCPE port map (cpha,cpha_T,cpha_C,NOT cpu_Nres,'0',NOT cpu_rnw); +cpha_T <= ((cpha AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(0).PIN) + OR (NOT cpha AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(0).PIN)); +cpha_C <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_cpol: FTCPE port map (cpol,cpol_T,cpol_C,NOT cpu_Nres,'0',NOT cpu_rnw); +cpol_T <= ((cpol AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(1).PIN) + OR (NOT cpol AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(1).PIN)); +cpol_C <= NOT ((cs1 AND NOT Ncs2)); + + +cpu_Nirq_I <= '0'; +cpu_Nirq <= cpu_Nirq_I when cpu_Nirq_OE = '1' else 'Z'; +cpu_Nirq_OE <= cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST; + + +cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST <= ((ier AND tc) + OR (slaveinten(0) AND NOT spi_int(0)) + OR (slaveinten(1) AND NOT spi_int(1)) + OR (slaveinten(2) AND NOT spi_int(2)) + OR (slaveinten(3) AND NOT spi_int(3))); + + +diag <= (spi_Nsel(0) AND NOT start_shifting AND NOT shifting2); + +FTCPE_divisor0: FTCPE port map (divisor(0),divisor_T(0),divisor_C(0),NOT cpu_Nres,'0',NOT cpu_rnw); +divisor_T(0) <= ((divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(0).PIN) + OR (NOT divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(0).PIN)); +divisor_C(0) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_divisor1: FTCPE port map (divisor(1),divisor_T(1),divisor_C(1),NOT cpu_Nres,'0',NOT cpu_rnw); +divisor_T(1) <= ((divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(1).PIN) + OR (NOT divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(1).PIN)); +divisor_C(1) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_divisor2: FTCPE port map (divisor(2),divisor_T(2),divisor_C(2),NOT cpu_Nres,'0',NOT cpu_rnw); +divisor_T(2) <= ((divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND NOT cpu_d(2).PIN) + OR (NOT divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND cpu_d(2).PIN)); +divisor_C(2) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_ece: FTCPE port map (ece,ece_T,ece_C,NOT cpu_Nres,'0',NOT cpu_rnw); +ece_T <= ((ece AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(2).PIN) + OR (NOT ece AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(2).PIN)); +ece_C <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_frx: FTCPE port map (frx,frx_T,frx_C,NOT cpu_Nres,'0',NOT cpu_rnw); +frx_T <= ((frx AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(4).PIN) + OR (NOT frx AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(4).PIN)); +frx_C <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_ier: FTCPE port map (ier,ier_T,ier_C,NOT cpu_Nres,'0',NOT cpu_rnw); +ier_T <= ((slaveinten(1).EXP) + OR (NOT ier AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(6).PIN)); +ier_C <= NOT ((cs1 AND NOT Ncs2)); + + +cpu_d_I(0) <= ((cpu_rnw AND spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND cpha AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND divisor(0) AND cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2)); +cpu_d(0) <= cpu_d_I(0) when cpu_d_OE(0) = '1' else 'Z'; +cpu_d_OE(0) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(1) <= ((cpu_rnw AND spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND cpol AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND divisor(1) AND cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2)); +cpu_d(1) <= cpu_d_I(1) when cpu_d_OE(1) = '1' else 'Z'; +cpu_d_OE(1) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(2) <= ((cpu_rnw AND spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND ece AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND divisor(2) AND cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2)); +cpu_d(2) <= cpu_d_I(2) when cpu_d_OE(2) = '1' else 'Z'; +cpu_d_OE(2) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(3) <= ((cpu_rnw AND spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND tmo AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2)); +cpu_d(3) <= cpu_d_I(3) when cpu_d_OE(3) = '1' else 'Z'; +cpu_d_OE(3) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(4) <= ((cpu_rnw AND frx AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND + NOT spi_int(0) AND cpu_Nphi2)); +cpu_d(4) <= cpu_d_I(4) when cpu_d_OE(4) = '1' else 'Z'; +cpu_d_OE(4) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(5) <= ((shifting2.EXP) + OR (cpu_rnw AND slaveinten(1) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND start_shifting AND NOT cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND NOT Ncs2 AND + shifting2 AND cpu_Nphi2)); +cpu_d(5) <= cpu_d_I(5) when cpu_d_OE(5) = '1' else 'Z'; +cpu_d_OE(5) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(6) <= ((cpu_rnw AND ier AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND + NOT spi_int(2) AND cpu_Nphi2)); +cpu_d(6) <= cpu_d_I(6) when cpu_d_OE(6) = '1' else 'Z'; +cpu_d_OE(6) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + + +cpu_d_I(7) <= ((cpu_rnw AND slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND spidatain(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cs1 AND NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND tc AND NOT cpu_a(1) AND cpu_a(0) AND cs1 AND + NOT Ncs2 AND cpu_Nphi2) + OR (cpu_rnw AND cpu_a(1) AND NOT cpu_a(0) AND cs1 AND NOT Ncs2 AND + NOT spi_int(3) AND cpu_Nphi2)); +cpu_d(7) <= cpu_d_I(7) when cpu_d_OE(7) = '1' else 'Z'; +cpu_d_OE(7) <= (cpu_rnw AND cs1 AND NOT Ncs2 AND cpu_Nphi2); + +FDCPE_spi_mosi: FDCPE port map (spi_mosi_I,spi_mosi,NOT $OpTx$INV$22__$INT,'0',NOT cpu_Nres); +spi_mosi <= ((start_shifting/start_shifting_RSTF__$INT.EXP) + OR (EXP6_.EXP) + OR (shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND + NOT shiftdone AND NOT spidataout(1) AND shifting2) + OR (NOT shiftcnt(3) AND shiftcnt(2) AND NOT shiftcnt(1) AND + NOT shiftdone AND NOT spidataout(5) AND shifting2)); +spi_mosi <= spi_mosi_I when spi_mosi_OE = '1' else 'Z'; +spi_mosi_OE <= NOT tmo; + +FDCPE_spi_sclk: FDCPE port map (spi_sclk,spi_sclk_D,NOT $OpTx$INV$22__$INT,spi_sclk_CLR,spi_sclk_PRE); +spi_sclk_D <= cpol + XOR +spi_sclk_D <= ((ier.EXP) + OR (cpu_Nres AND NOT cpha AND shiftcnt(0) AND NOT shiftdone AND + shifting2)); +spi_sclk_CLR <= (NOT cpu_Nres AND NOT cpol); +spi_sclk_PRE <= (NOT cpu_Nres AND cpol); + +FDCPE_shiftcnt0: FDCPE port map (shiftcnt(0),shiftcnt_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0'); +shiftcnt_D(0) <= (NOT shiftcnt(0) AND shifting2); + +FDCPE_shiftcnt1: FDCPE port map (shiftcnt(1),shiftcnt_D(1),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0'); +shiftcnt_D(1) <= ((shiftcnt(0) AND NOT shiftcnt(1) AND shifting2) + OR (NOT shiftcnt(0) AND shiftcnt(1) AND shifting2)); + +FTCPE_shiftcnt2: FTCPE port map (shiftcnt(2),shiftcnt_T(2),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0'); +shiftcnt_T(2) <= ((shiftcnt(2) AND NOT shifting2) + OR (shiftcnt(0) AND shiftcnt(1) AND shifting2)); + +FTCPE_shiftcnt3: FTCPE port map (shiftcnt(3),shiftcnt_T(3),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0'); +shiftcnt_T(3) <= ((shiftcnt(3) AND NOT shifting2) + OR (shiftcnt(2) AND shiftcnt(0) AND shiftcnt(1) AND + shifting2)); + +FDCPE_shiftdone: FDCPE port map (shiftdone,shiftdone_D,NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0'); +shiftdone_D <= (shiftcnt(3) AND shiftcnt(2) AND shiftcnt(0) AND + shiftcnt(1)); + +FDCPE_shifting2: FDCPE port map (shifting2,shifting2_D,NOT $OpTx$INV$22__$INT,'0','0'); +shifting2_D <= (NOT shiftdone AND start_shifting); + +FTCPE_slaveinten0: FTCPE port map (slaveinten(0),slaveinten_T(0),slaveinten_C(0),NOT cpu_Nres,'0',NOT cpu_rnw); +slaveinten_T(0) <= ((slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(4).PIN) + OR (NOT slaveinten(0) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(4).PIN)); +slaveinten_C(0) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_slaveinten1: FTCPE port map (slaveinten(1),slaveinten_T(1),slaveinten_C(1),NOT cpu_Nres,'0',NOT cpu_rnw); +slaveinten_T(1) <= ((diag_OBUF.EXP) + OR (NOT slaveinten(1) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(5).PIN)); +slaveinten_C(1) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_slaveinten2: FTCPE port map (slaveinten(2),slaveinten_T(2),slaveinten_C(2),NOT cpu_Nres,'0',NOT cpu_rnw); +slaveinten_T(2) <= ((slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(6).PIN) + OR (NOT slaveinten(2) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(6).PIN)); +slaveinten_C(2) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_slaveinten3: FTCPE port map (slaveinten(3),slaveinten_T(3),slaveinten_C(3),NOT cpu_Nres,'0',NOT cpu_rnw); +slaveinten_T(3) <= ((slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(7).PIN) + OR (NOT slaveinten(3) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(7).PIN)); +slaveinten_C(3) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_spi_Nsel0: FTCPE port map (spi_Nsel(0),spi_Nsel_T(0),spi_Nsel_C(0),'0',NOT cpu_Nres,NOT cpu_rnw); +spi_Nsel_T(0) <= ((spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(0).PIN) + OR (NOT spi_Nsel(0) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(0).PIN)); +spi_Nsel_C(0) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_spi_Nsel1: FTCPE port map (spi_Nsel(1),spi_Nsel_T(1),spi_Nsel_C(1),'0',NOT cpu_Nres,NOT cpu_rnw); +spi_Nsel_T(1) <= ((spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(1).PIN) + OR (NOT spi_Nsel(1) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(1).PIN)); +spi_Nsel_C(1) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_spi_Nsel2: FTCPE port map (spi_Nsel(2),spi_Nsel_T(2),spi_Nsel_C(2),'0',NOT cpu_Nres,NOT cpu_rnw); +spi_Nsel_T(2) <= ((spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(2).PIN) + OR (NOT spi_Nsel(2) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(2).PIN)); +spi_Nsel_C(2) <= NOT ((cs1 AND NOT Ncs2)); + +FTCPE_spi_Nsel3: FTCPE port map (spi_Nsel(3),spi_Nsel_T(3),spi_Nsel_C(3),'0',NOT cpu_Nres,NOT cpu_rnw); +spi_Nsel_T(3) <= ((spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND + NOT cpu_d(3).PIN) + OR (NOT spi_Nsel(3) AND cpu_a(1) AND cpu_a(0) AND + cpu_d(3).PIN)); +spi_Nsel_C(3) <= NOT ((cs1 AND NOT Ncs2)); + +FDCPE_spidatain0: FDCPE port map (spidatain(0),spidatain_D(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(0)); +spidatain_D(0) <= ((tc.EXP) + OR (NOT spi_Nsel(2) AND spi_miso(2)) + OR (NOT spi_Nsel(3) AND spi_miso(3))); +spidatain_CE(0) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain1: FDCPE port map (spidatain(1),spidatain(0),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(1)); +spidatain_CE(1) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain2: FDCPE port map (spidatain(2),spidatain(1),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(2)); +spidatain_CE(2) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain3: FDCPE port map (spidatain(3),spidatain(2),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(3)); +spidatain_CE(3) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain4: FDCPE port map (spidatain(4),spidatain(3),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(4)); +spidatain_CE(4) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain5: FDCPE port map (spidatain(5),spidatain(4),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(5)); +spidatain_CE(5) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain6: FDCPE port map (spidatain(6),spidatain(5),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(6)); +spidatain_CE(6) <= (shiftcnt(0) AND shifting2); + +FDCPE_spidatain7: FDCPE port map (spidatain(7),spidatain(6),NOT $OpTx$INV$22__$INT,NOT cpu_Nres,'0',spidatain_CE(7)); +spidatain_CE(7) <= (shiftcnt(0) AND shifting2); + +FTCPE_spidataout0: FTCPE port map (spidataout(0),spidataout_T(0),spidataout_C(0),'0','0',spidataout_CE(0)); +spidataout_T(0) <= ((spidataout(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(0).PIN) + OR (NOT spidataout(0) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(0).PIN)); +spidataout_C(0) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(0) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout1: FTCPE port map (spidataout(1),spidataout_T(1),spidataout_C(1),'0','0',spidataout_CE(1)); +spidataout_T(1) <= ((spidataout(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(1).PIN) + OR (NOT spidataout(1) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(1).PIN)); +spidataout_C(1) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(1) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout2: FTCPE port map (spidataout(2),spidataout_T(2),spidataout_C(2),'0','0',spidataout_CE(2)); +spidataout_T(2) <= ((spidataout(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(2).PIN) + OR (NOT spidataout(2) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(2).PIN)); +spidataout_C(2) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(2) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout3: FTCPE port map (spidataout(3),spidataout_T(3),spidataout_C(3),'0','0',spidataout_CE(3)); +spidataout_T(3) <= ((spidataout(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(3).PIN) + OR (NOT spidataout(3) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(3).PIN)); +spidataout_C(3) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(3) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout4: FTCPE port map (spidataout(4),spidataout_T(4),spidataout_C(4),'0','0',spidataout_CE(4)); +spidataout_T(4) <= ((spidataout(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(4).PIN) + OR (NOT spidataout(4) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(4).PIN)); +spidataout_C(4) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(4) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout5: FTCPE port map (spidataout(5),spidataout_T(5),spidataout_C(5),'0','0',spidataout_CE(5)); +spidataout_T(5) <= ((spidataout(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(5).PIN) + OR (NOT spidataout(5) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(5).PIN)); +spidataout_C(5) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(5) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout6: FTCPE port map (spidataout(6),spidataout_T(6),spidataout_C(6),'0','0',spidataout_CE(6)); +spidataout_T(6) <= ((spidataout(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(6).PIN) + OR (NOT spidataout(6) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(6).PIN)); +spidataout_C(6) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(6) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_spidataout7: FTCPE port map (spidataout(7),spidataout_T(7),spidataout_C(7),'0','0',spidataout_CE(7)); +spidataout_T(7) <= ((spidataout(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + NOT cpu_d(7).PIN) + OR (NOT spidataout(7) AND NOT cpu_a(1) AND NOT cpu_a(0) AND + cpu_d(7).PIN)); +spidataout_C(7) <= NOT ((cs1 AND NOT Ncs2)); +spidataout_CE(7) <= (cpu_Nres AND NOT cpu_rnw); + +FTCPE_start_shifting: FTCPE port map (start_shifting,start_shifting_T,start_shifting_C,NOT start_shifting/start_shifting_RSTF__$INT,'0'); +start_shifting_T <= ((NOT cpu_rnw AND NOT start_shifting AND NOT cpu_a(1) AND NOT cpu_a(0)) + OR (frx AND NOT start_shifting AND NOT cpu_a(1) AND NOT cpu_a(0))); +start_shifting_C <= NOT ((cs1 AND NOT Ncs2)); + + +start_shifting/start_shifting_RSTF__$INT <= (cpu_Nres AND NOT shiftdone); + +FDCPE_tc: FDCPE port map (tc,'0',tc_C,'0',shiftdone,tc_CE); +tc_C <= NOT ((cs1 AND NOT Ncs2)); +tc_CE <= (NOT cpu_a(1) AND NOT cpu_a(0)); + +FTCPE_tmo: FTCPE port map (tmo,tmo_T,tmo_C,NOT cpu_Nres,'0',NOT cpu_rnw); +tmo_T <= ((tmo AND NOT cpu_a(1) AND cpu_a(0) AND NOT cpu_d(3).PIN) + OR (NOT tmo AND NOT cpu_a(1) AND cpu_a(0) AND cpu_d(3).PIN)); +tmo_C <= NOT ((cs1 AND NOT Ncs2)); + +Register Legend: + FDCPE (Q,D,C,CLR,PRE,CE); + FTCPE (Q,D,C,CLR,PRE,CE); + LDCP (Q,D,G,CLR,PRE); + + **************************** Device Pin Out **************************** + +Device : XC9572XL-10-PC44 + + + -------------------------------- + /6 5 4 3 2 1 44 43 42 41 40 \ + | 7 39 | + | 8 38 | + | 9 37 | + | 10 36 | + | 11 XC9572XL-10-PC44 35 | + | 12 34 | + | 13 33 | + | 14 32 | + | 15 31 | + | 16 30 | + | 17 29 | + \ 18 19 20 21 22 23 24 25 26 27 28 / + -------------------------------- + + +Pin Signal Pin Signal +No. Name No. Name + 1 spi_int<3> 23 GND + 2 cpu_d<0> 24 cpu_a<1> + 3 cpu_d<1> 25 spi_Nsel<3> + 4 cpu_d<2> 26 spi_Nsel<2> + 5 cpu_Nphi2 27 spi_Nsel<1> + 6 extclk 28 spi_Nsel<0> + 7 cpu_rnw 29 diag + 8 cpu_d<3> 30 TDO + 9 cpu_d<4> 31 GND + 10 GND 32 VCC + 11 cpu_d<5> 33 TIE + 12 cpu_d<6> 34 spi_sclk + 13 cpu_d<7> 35 spi_mosi + 14 cpu_Nirq 36 TIE + 15 TDI 37 spi_miso<3> + 16 TMS 38 spi_miso<2> + 17 TCK 39 spi_int<2> + 18 Ncs2 40 spi_int<1> + 19 cpu_Nres 41 VCC + 20 cs1 42 spi_int<0> + 21 VCC 43 spi_miso<1> + 22 cpu_a<0> 44 spi_miso<0> + + +Legend : NC = Not Connected, unbonded pin + PGND = Unused I/O configured as additional Ground pin + TIE = Unused I/O floating -- must tie to VCC, GND or other signal + VCC = Dedicated Power Pin + GND = Dedicated Ground Pin + TDI = Test Data In, JTAG pin + TDO = Test Data Out, JTAG pin + TCK = Test Clock, JTAG pin + TMS = Test Mode Select, JTAG pin + PE = Port Enable pin + PROHIBITED = User reserved pin + **************************** Compiler Options **************************** + +Following is a list of all global compiler options used by the fitter run. + +Device(s) Specified : xc9572xl-10-PC44 +Optimization Method : SPEED +Multi-Level Logic Optimization : ON +Ignore Timing Specifications : OFF +Default Register Power Up Value : LOW +Keep User Location Constraints : ON +What-You-See-Is-What-You-Get : OFF +Exhaustive Fitting : OFF +Keep Unused Inputs : OFF +Slew Rate : FAST +Power Mode : STD +Set Unused I/O Pin Termination : FLOAT +Set I/O Pin Termination : KEEPER +Global Clock Optimization : ON +Global Set/Reset Optimization : ON +Global Ouput Enable Optimization : ON +Input Limit : 54 +Pterm Limit : 25 diff --git a/spi6502b.syr b/spi6502b.syr new file mode 100644 index 0000000..10de977 --- /dev/null +++ b/spi6502b.syr @@ -0,0 +1,215 @@ +Release 6.3.03i - xst G.38 +Copyright (c) 1995-2004 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to __projnav +CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s + +--> Parameter xsthdpdir set to ./xst +CPU : 0.00 / 0.28 s | Elapsed : 0.00 / 0.00 s + +--> Reading design: spi6502b.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) HDL Analysis + 4) HDL Synthesis + 5) Advanced HDL Synthesis + 5.1) HDL Synthesis Report + 6) Low Level Synthesis + 7) Final Report + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : spi6502b.prj +Input Format : mixed +Ignore Synthesis Constraint File : NO +Verilog Include Directory : + +---- Target Parameters +Output File Name : spi6502b +Output Format : NGC +Target Device : xc9500xl + +---- Source Options +Top Module Name : spi6502b +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Mux Extraction : YES +Resource Sharing : YES + +---- Target Options +Add IO Buffers : YES +Equivalent register Removal : YES +MACRO Preserve : YES +XOR Preserve : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : YES +RTL Output : Yes +Hierarchy Separator : _ +Bus Delimiter : <> +Case Specifier : maintain + +---- Other Options +lso : spi6502b.lso +verilog2001 : YES +Clock Enable : YES +wysiwyg : NO + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file C:/sources/AppleIISd/SPI6502B1.1.vhd in Library work. +Architecture behavioral of Entity spi6502b is up to date. + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity (Architecture ). +INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 203: Mux is complete : default of case is discarded +INFO:Xst:1561 - C:/sources/AppleIISd/SPI6502B1.1.vhd line 320: Mux is complete : default of case is discarded +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Synthesizing Unit . + Related source file is C:/sources/AppleIISd/SPI6502B1.1.vhd. + Found 8-bit tristate buffer for signal . + Found 1-bit tristate buffer for signal . + Found 1-bit tristate buffer for signal . + Found 1-bit xor3 for signal <$n0040> created at line 206. + Found 4-bit adder for signal <$n0047> created at line 160. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 3-bit down counter for signal . + Found 3-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 4-bit register for signal . + Found 4-bit register for signal . + Found 8-bit register for signal . + Found 8-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 30 1-bit 2-to-1 multiplexers. + Summary: + inferred 1 Counter(s). + inferred 18 D-type flip-flop(s). + inferred 1 Adder/Subtracter(s). + inferred 10 Tristate(s). +Unit synthesized. + + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + +Advanced RAM inference ... +Advanced multiplier inference ... +Advanced Registered AddSub inference ... +Dynamic shift register inference ... + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 1 + 4-bit adder : 1 +# Registers : 25 + 1-bit register : 20 + 8-bit register : 1 + 3-bit register : 1 + 4-bit register : 3 +# Multiplexers : 12 + 2-to-1 multiplexer : 12 +# Tristates : 3 + 1-bit tristate buffer : 2 + 8-bit tristate buffer : 1 +# Xors : 1 + 1-bit xor3 : 1 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : spi6502b.ngr +Top Level Output File Name : spi6502b +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : YES +Target Technology : xc9500xl +Macro Preserve : YES +XOR Preserve : YES +Clock Enable : YES +wysiwyg : NO + +Design Statistics +# IOs : 32 + +Macro Statistics : +# Registers : 74 +# 1-bit register : 74 +# Tristates : 3 +# 1-bit tristate buffer : 2 +# 8-bit tristate buffer : 1 +# Xors : 5 +# 1-bit xor2 : 5 + +Cell Usage : +# BELS : 320 +# AND2 : 156 +# AND3 : 2 +# AND4 : 1 +# GND : 1 +# INV : 95 +# OR2 : 56 +# OR3 : 1 +# OR4 : 1 +# OR5 : 1 +# VCC : 1 +# XOR2 : 5 +# FlipFlops/Latches : 43 +# FD : 1 +# FDC : 5 +# FDCE : 30 +# FDCP : 1 +# FDP : 1 +# FDPE : 5 +# IO Buffers : 32 +# IBUF : 16 +# IOBUFE : 8 +# OBUF : 6 +# OBUFE : 2 +========================================================================= +CPU : 0.67 / 1.11 s | Elapsed : 1.00 / 1.00 s + +--> + +Total memory usage is 68952 kilobytes + + diff --git a/spi6502b.vm6 b/spi6502b.vm6 new file mode 100644 index 0000000..dcde2e5 --- /dev/null +++ b/spi6502b.vm6 @@ -0,0 +1,4095 @@ +NDS Database: version G.38 + +NDS_INFO | xc9500xl | 9572XL44PC | XC9572XL-10-PC44 + +DEVICE | 9572XL | 9572XL44PC | + +NETWORK | spi6502b | 0 | 0 | 16391 + +INPUT_INSTANCE | 0 | 0 | NULL | cpu_Nres_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_Nres | 5046 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | Inv+PrldLow+PinTrst+OptxMapped | int_mosi | spi6502b_COPY_0_COPY_0 | 2155889920 | 12 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<5> | 4982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<1> | 4978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting/start_shifting_RSTF__$INT.EXP | 5420 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.EXP | start_shifting/start_shifting_RSTF__$INT | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP6_.EXP | 5421 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_mosi | 4937 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_mosi$OE | 4938 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_mosi.SI | int_mosi | 0 | 12 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<5> | 4982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<1> | 4978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting/start_shifting_RSTF__$INT.EXP | 5420 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.EXP | start_shifting/start_shifting_RSTF__$INT | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | EXP6_.EXP | 5421 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_mosi.D1 | 5063 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_mosi.D2 | 5064 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | start_shifting/start_shifting_RSTF__$INT.EXP +SPPTERM | 1 | IV_TRUE | EXP6_.EXP +SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<1> | IV_TRUE | shifting2 +SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<5> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | int_mosi.CLKF | 5065 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | int_mosi.SETF | 5066 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_mosi.TRST | 5068 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 1 | IV_FALSE | tmo + +SRFF_INSTANCE | int_mosi.REG | int_mosi | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_mosi.D | 5062 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | int_mosi.CLKF | 5065 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | int_mosi.SETF | 5066 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_mosi.Q | 5069 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_mosi.BUFOE | int_mosi | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_mosi.TRST | 5068 | ? | 0 | 4096 | int_mosi | NULL | NULL | int_mosi.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 1 | IV_FALSE | tmo +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_mosi.BUFOE.OUT | 5067 | ? | 0 | 0 | int_mosi | NULL | NULL | int_mosi.BUFOE | 0 | 10 | BUF_OUT + +INPUT_INSTANCE | 0 | 0 | NULL | cpu_rnw_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_rnw | 5047 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | Ncs2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | Ncs2 | 5051 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | cs1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cs1 | 5050 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | N3455 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<0> | 5033 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | cpu_a_1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_a<1> | 5048 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | cpu_a_0_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_a<0> | 5049 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slavesel<0> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | slavesel<0>$Q | 4940 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slavesel<0>.SI | slavesel<0> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slavesel<0>.D1 | 5071 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slavesel<0>.D2 | 5072 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slavesel<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3455 +SPPTERM | 4 | IV_FALSE | slavesel<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3455 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slavesel<0>.CLKF | 5073 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | slavesel<0>.SETF | 5074 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slavesel<0>.CE | 5075 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slavesel<0>.REG | slavesel<0> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slavesel<0>.D | 5070 | ? | 0 | 0 | slavesel<0> | NULL | NULL | slavesel<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slavesel<0>.CLKF | 5073 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | slavesel<0>.SETF | 5074 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slavesel<0>.CE | 5075 | ? | 0 | 4096 | slavesel<0> | NULL | NULL | slavesel<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slavesel<0>.Q | 5076 | ? | 0 | 0 | slavesel<0> | NULL | NULL | slavesel<0>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3457 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<1> | 5034 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slavesel<1> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | slavesel<1>$Q | 4942 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slavesel<1>.SI | slavesel<1> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slavesel<1>.D1 | 5078 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slavesel<1>.D2 | 5079 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slavesel<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3457 +SPPTERM | 4 | IV_FALSE | slavesel<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3457 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slavesel<1>.CLKF | 5080 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | slavesel<1>.SETF | 5081 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slavesel<1>.CE | 5082 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slavesel<1>.REG | slavesel<1> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slavesel<1>.D | 5077 | ? | 0 | 0 | slavesel<1> | NULL | NULL | slavesel<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slavesel<1>.CLKF | 5080 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | slavesel<1>.SETF | 5081 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slavesel<1>.CE | 5082 | ? | 0 | 4096 | slavesel<1> | NULL | NULL | slavesel<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slavesel<1>.Q | 5083 | ? | 0 | 0 | slavesel<1> | NULL | NULL | slavesel<1>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3459 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<2> | 5035 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slavesel<2> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | slavesel<2>$Q | 4944 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slavesel<2>.SI | slavesel<2> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slavesel<2>.D1 | 5085 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slavesel<2>.D2 | 5086 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slavesel<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3459 +SPPTERM | 4 | IV_FALSE | slavesel<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3459 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slavesel<2>.CLKF | 5087 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | slavesel<2>.SETF | 5088 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slavesel<2>.CE | 5089 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slavesel<2>.REG | slavesel<2> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slavesel<2>.D | 5084 | ? | 0 | 0 | slavesel<2> | NULL | NULL | slavesel<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slavesel<2>.CLKF | 5087 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | slavesel<2>.SETF | 5088 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slavesel<2>.CE | 5089 | ? | 0 | 4096 | slavesel<2> | NULL | NULL | slavesel<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slavesel<2>.Q | 5090 | ? | 0 | 0 | slavesel<2> | NULL | NULL | slavesel<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3461 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<3> | 5036 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slavesel<3> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | slavesel<3>$Q | 4946 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slavesel<3>.SI | slavesel<3> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slavesel<3>.D1 | 5092 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slavesel<3>.D2 | 5093 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slavesel<3> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3461 +SPPTERM | 4 | IV_FALSE | slavesel<3> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3461 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slavesel<3>.CLKF | 5094 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | slavesel<3>.SETF | 5095 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slavesel<3>.CE | 5096 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slavesel<3>.REG | slavesel<3> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slavesel<3>.D | 5091 | ? | 0 | 0 | slavesel<3> | NULL | NULL | slavesel<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slavesel<3>.CLKF | 5094 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | slavesel<3>.SETF | 5095 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slavesel<3>.CE | 5096 | ? | 0 | 4096 | slavesel<3> | NULL | NULL | slavesel<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slavesel<3>.Q | 5097 | ? | 0 | 0 | slavesel<3> | NULL | NULL | slavesel<3>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | cpol | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | cpol.SI | cpol | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | cpol.D1 | 5099 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | cpol.D2 | 5100 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3457 +SPPTERM | 4 | IV_FALSE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3457 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | cpol.CLKF | 5101 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | cpol.RSTF | 5102 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | cpol.CE | 5103 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | cpol.REG | cpol | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | cpol.D | 5098 | ? | 0 | 0 | cpol | NULL | NULL | cpol.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | cpol.CLKF | 5101 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | cpol.RSTF | 5102 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | cpol.CE | 5103 | ? | 0 | 4096 | cpol | NULL | NULL | cpol.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | cpol.Q | 5104 | ? | 0 | 0 | cpol | NULL | NULL | cpol.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | ece | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | ece.SI | ece | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ece.D1 | 5106 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ece.D2 | 5107 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3459 +SPPTERM | 4 | IV_FALSE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3459 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | ece.CLKF | 5108 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | ece.RSTF | 5109 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | ece.CE | 5110 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | ece.REG | ece | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ece.D | 5105 | ? | 0 | 0 | ece | NULL | NULL | ece.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | ece.CLKF | 5108 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | ece.RSTF | 5109 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | ece.CE | 5110 | ? | 0 | 4096 | ece | NULL | NULL | ece.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ece.Q | 5111 | ? | 0 | 0 | ece | NULL | NULL | ece.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | cpha | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | cpha.SI | cpha | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | cpha.D1 | 5113 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | cpha.D2 | 5114 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3455 +SPPTERM | 4 | IV_FALSE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3455 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | cpha.CLKF | 5115 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | cpha.RSTF | 5116 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | cpha.CE | 5117 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | cpha.REG | cpha | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | cpha.D | 5112 | ? | 0 | 0 | cpha | NULL | NULL | cpha.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | cpha.CLKF | 5115 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | cpha.RSTF | 5116 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | cpha.CE | 5117 | ? | 0 | 4096 | cpha | NULL | NULL | cpha.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | cpha.Q | 5118 | ? | 0 | 0 | cpha | NULL | NULL | cpha.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3463 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<4> | 5037 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | frx | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | frx.SI | frx | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | frx.D1 | 5120 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | frx.D2 | 5121 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3463 +SPPTERM | 4 | IV_FALSE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3463 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | frx.CLKF | 5122 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | frx.RSTF | 5123 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | frx.CE | 5124 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | frx.REG | frx | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | frx.D | 5119 | ? | 0 | 0 | frx | NULL | NULL | frx.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | frx.CLKF | 5122 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | frx.RSTF | 5123 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | frx.CE | 5124 | ? | 0 | 4096 | frx | NULL | NULL | frx.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | frx.Q | 5125 | ? | 0 | 0 | frx | NULL | NULL | frx.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3467 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<6> | 5039 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | ier | spi6502b_COPY_0_COPY_0 | 2424312832 | 13 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1>.EXP | 5430 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.EXP | slaveinten<1> | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | ier.EXP | 5431 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.EXP | ier | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | ier.SI | ier | 0 | 13 | 6 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1>.EXP | 5430 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.EXP | slaveinten<1> | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | ier.D1 | 5127 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | ier.D2 | 5128 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | slaveinten<1>.EXP +SPPTERM | 4 | IV_FALSE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3467 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | ier.CLKF | 5129 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | ier.RSTF | 5130 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | ier.EXP | 5427 | ? | 0 | 0 | ier | NULL | NULL | ier.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_TRUE | cpha | IV_FALSE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | ier.CE | 5131 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | ier.REG | ier | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | ier.D | 5126 | ? | 0 | 0 | ier | NULL | NULL | ier.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | ier.CLKF | 5129 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | ier.RSTF | 5130 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | ier.CE | 5131 | ? | 0 | 4096 | ier | NULL | NULL | ier.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | ier.Q | 5132 | ? | 0 | 0 | ier | NULL | NULL | ier.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slaveinten<0> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slaveinten<0>.SI | slaveinten<0> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slaveinten<0>.D1 | 5134 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slaveinten<0>.D2 | 5135 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slaveinten<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3463 +SPPTERM | 4 | IV_FALSE | slaveinten<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3463 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slaveinten<0>.CLKF | 5136 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | slaveinten<0>.RSTF | 5137 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slaveinten<0>.CE | 5138 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slaveinten<0>.REG | slaveinten<0> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slaveinten<0>.D | 5133 | ? | 0 | 0 | slaveinten<0> | NULL | NULL | slaveinten<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slaveinten<0>.CLKF | 5136 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | slaveinten<0>.RSTF | 5137 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slaveinten<0>.CE | 5138 | ? | 0 | 4096 | slaveinten<0> | NULL | NULL | slaveinten<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slaveinten<0>.Q | 5139 | ? | 0 | 0 | slaveinten<0> | NULL | NULL | slaveinten<0>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3465 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<5> | 5038 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slaveinten<1> | spi6502b_COPY_0_COPY_0 | 2424312832 | 11 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | diag_OBUF.EXP | 5429 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | diag_OBUF.EXP | diag_OBUF | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | slaveinten<1>.EXP | 5430 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.EXP | slaveinten<1> | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | slaveinten<1>.SI | slaveinten<1> | 0 | 11 | 6 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | diag_OBUF.EXP | 5429 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | diag_OBUF.EXP | diag_OBUF | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slaveinten<1>.D1 | 5141 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slaveinten<1>.D2 | 5142 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | diag_OBUF.EXP +SPPTERM | 4 | IV_FALSE | slaveinten<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3465 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slaveinten<1>.CLKF | 5143 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | slaveinten<1>.RSTF | 5144 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | slaveinten<1>.EXP | 5426 | ? | 0 | 0 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 4 | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3467 +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slaveinten<1>.CE | 5145 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slaveinten<1>.REG | slaveinten<1> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slaveinten<1>.D | 5140 | ? | 0 | 0 | slaveinten<1> | NULL | NULL | slaveinten<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slaveinten<1>.CLKF | 5143 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | slaveinten<1>.RSTF | 5144 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slaveinten<1>.CE | 5145 | ? | 0 | 4096 | slaveinten<1> | NULL | NULL | slaveinten<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slaveinten<1>.Q | 5146 | ? | 0 | 0 | slaveinten<1> | NULL | NULL | slaveinten<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slaveinten<2> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slaveinten<2>.SI | slaveinten<2> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slaveinten<2>.D1 | 5148 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slaveinten<2>.D2 | 5149 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slaveinten<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3467 +SPPTERM | 4 | IV_FALSE | slaveinten<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3467 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slaveinten<2>.CLKF | 5150 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | slaveinten<2>.RSTF | 5151 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slaveinten<2>.CE | 5152 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slaveinten<2>.REG | slaveinten<2> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slaveinten<2>.D | 5147 | ? | 0 | 0 | slaveinten<2> | NULL | NULL | slaveinten<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slaveinten<2>.CLKF | 5150 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | slaveinten<2>.RSTF | 5151 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slaveinten<2>.CE | 5152 | ? | 0 | 4096 | slaveinten<2> | NULL | NULL | slaveinten<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slaveinten<2>.Q | 5153 | ? | 0 | 0 | slaveinten<2> | NULL | NULL | slaveinten<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | N3469 | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_d<7> | 5040 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | N3469 | 5012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3469 | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | slaveinten<3> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3469 | 5012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3469 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | slaveinten<3>.SI | slaveinten<3> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3469 | 5012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3469 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | slaveinten<3>.D1 | 5155 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | slaveinten<3>.D2 | 5156 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | slaveinten<3> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3469 +SPPTERM | 4 | IV_FALSE | slaveinten<3> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3469 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | slaveinten<3>.CLKF | 5157 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | slaveinten<3>.RSTF | 5158 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | slaveinten<3>.CE | 5159 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | slaveinten<3>.REG | slaveinten<3> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | slaveinten<3>.D | 5154 | ? | 0 | 0 | slaveinten<3> | NULL | NULL | slaveinten<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | slaveinten<3>.CLKF | 5157 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | slaveinten<3>.RSTF | 5158 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | slaveinten<3>.CE | 5159 | ? | 0 | 4096 | slaveinten<3> | NULL | NULL | slaveinten<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | slaveinten<3>.Q | 5160 | ? | 0 | 0 | slaveinten<3> | NULL | NULL | slaveinten<3>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | tmo | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | tmo.SI | tmo | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | tmo.D1 | 5162 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | tmo.D2 | 5163 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3461 +SPPTERM | 4 | IV_FALSE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | N3461 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | tmo.CLKF | 5164 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | tmo.RSTF | 5165 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | tmo.CE | 5166 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | tmo.REG | tmo | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | tmo.D | 5161 | ? | 0 | 0 | tmo | NULL | NULL | tmo.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | tmo.CLKF | 5164 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | tmo.RSTF | 5165 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | tmo.CE | 5166 | ? | 0 | 4096 | tmo | NULL | NULL | tmo.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | tmo.Q | 5167 | ? | 0 | 0 | tmo | NULL | NULL | tmo.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | divisor<0> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<0> | 4958 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | divisor<0> | 4958 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | divisor<0>.SI | divisor<0> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<0> | 4958 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | divisor<0>.D1 | 5169 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | divisor<0>.D2 | 5170 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3455 +SPPTERM | 4 | IV_FALSE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3455 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | divisor<0>.CLKF | 5171 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | divisor<0>.RSTF | 5172 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | divisor<0>.CE | 5173 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | divisor<0>.REG | divisor<0> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | divisor<0>.D | 5168 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | divisor<0>.CLKF | 5171 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | divisor<0>.RSTF | 5172 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | divisor<0>.CE | 5173 | ? | 0 | 4096 | divisor<0> | NULL | NULL | divisor<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | divisor<0>.Q | 5174 | ? | 0 | 0 | divisor<0> | NULL | NULL | divisor<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | divisor<1> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<1> | 4959 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | divisor<1> | 4959 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | divisor<1>.SI | divisor<1> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<1> | 4959 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | divisor<1>.D1 | 5176 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | divisor<1>.D2 | 5177 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3457 +SPPTERM | 4 | IV_FALSE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3457 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | divisor<1>.CLKF | 5178 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | divisor<1>.RSTF | 5179 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | divisor<1>.CE | 5180 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | divisor<1>.REG | divisor<1> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | divisor<1>.D | 5175 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | divisor<1>.CLKF | 5178 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | divisor<1>.RSTF | 5179 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | divisor<1>.CE | 5180 | ? | 0 | 4096 | divisor<1> | NULL | NULL | divisor<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | divisor<1>.Q | 5181 | ? | 0 | 0 | divisor<1> | NULL | NULL | divisor<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | divisor<2> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<2> | 4960 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | divisor<2> | 4960 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | divisor<2>.SI | divisor<2> | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<2> | 4960 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | divisor<2>.D1 | 5183 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | divisor<2>.D2 | 5184 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3459 +SPPTERM | 4 | IV_FALSE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3459 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | divisor<2>.CLKF | 5185 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | divisor<2>.RSTF | 5186 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | divisor<2>.CE | 5187 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | divisor<2>.REG | divisor<2> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | divisor<2>.D | 5182 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | divisor<2>.CLKF | 5185 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | divisor<2>.RSTF | 5186 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | divisor<2>.CE | 5187 | ? | 0 | 4096 | divisor<2> | NULL | NULL | divisor<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 1 | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | divisor<2>.Q | 5188 | ? | 0 | 0 | divisor<2> | NULL | NULL | divisor<2>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | spi_miso_3_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_miso<3> | 5058 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_miso_3_IBUF | 5020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_3_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | spi_miso_2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_miso<2> | 5057 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_miso_2_IBUF | 5019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_2_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | spi_miso_1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_miso<1> | 5056 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_miso_1_IBUF | 5018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_1_IBUF | 0 | 5 | II_IMUX + +INPUT_INSTANCE | 0 | 0 | NULL | spi_miso_0_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_miso<0> | 5059 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_miso_0_IBUF | 5021 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_0_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<0> | spi6502b_COPY_0_COPY_0 | 2155873280 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_3_IBUF | 5020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_2_IBUF | 5019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tc.EXP | 5428 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.EXP | tc | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<0> | 4961 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<0>.SI | spidatain<0> | 0 | 9 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_3_IBUF | 5020 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_2_IBUF | 5019 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tc.EXP | 5428 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.EXP | tc | 4 | 0 | MC_EXPORT +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<0>.D1 | 5190 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<0>.D2 | 5191 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | tc.EXP +SPPTERM | 2 | IV_FALSE | slavesel<2> | IV_TRUE | spi_miso_2_IBUF +SPPTERM | 2 | IV_FALSE | slavesel<3> | IV_TRUE | spi_miso_3_IBUF +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<0>.CLKF | 5192 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<0>.RSTF | 5193 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<0>.CE | 5194 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<0>.REG | spidatain<0> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<0>.D | 5189 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<0>.CLKF | 5192 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<0>.RSTF | 5193 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<0>.CE | 5194 | ? | 0 | 4096 | spidatain<0> | NULL | NULL | spidatain<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<0>.Q | 5195 | ? | 0 | 0 | spidatain<0> | NULL | NULL | spidatain<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<0> | 4961 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<1> | 4962 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<1>.SI | spidatain<1> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<0> | 4961 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<1>.D1 | 5197 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<1>.D2 | 5198 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<0> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<1>.CLKF | 5199 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<1>.RSTF | 5200 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<1>.CE | 5201 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<1>.REG | spidatain<1> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<1>.D | 5196 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<1>.CLKF | 5199 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<1>.RSTF | 5200 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<1>.CE | 5201 | ? | 0 | 4096 | spidatain<1> | NULL | NULL | spidatain<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<1>.Q | 5202 | ? | 0 | 0 | spidatain<1> | NULL | NULL | spidatain<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<2> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<1> | 4962 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<2> | 4963 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<2>.SI | spidatain<2> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<1> | 4962 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<2>.D1 | 5204 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<2>.D2 | 5205 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<1> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<2>.CLKF | 5206 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<2>.RSTF | 5207 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<2>.CE | 5208 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<2>.REG | spidatain<2> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<2>.D | 5203 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<2>.CLKF | 5206 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<2>.RSTF | 5207 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<2>.CE | 5208 | ? | 0 | 4096 | spidatain<2> | NULL | NULL | spidatain<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<2>.Q | 5209 | ? | 0 | 0 | spidatain<2> | NULL | NULL | spidatain<2>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<3> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<2> | 4963 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<3> | 4964 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<3>.SI | spidatain<3> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<2> | 4963 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<3>.D1 | 5211 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<3>.D2 | 5212 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<2> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<3>.CLKF | 5213 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<3>.RSTF | 5214 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<3>.CE | 5215 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<3>.REG | spidatain<3> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<3>.D | 5210 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<3>.CLKF | 5213 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<3>.RSTF | 5214 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<3>.CE | 5215 | ? | 0 | 4096 | spidatain<3> | NULL | NULL | spidatain<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<3>.Q | 5216 | ? | 0 | 0 | spidatain<3> | NULL | NULL | spidatain<3>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<4> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<3> | 4964 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<4> | 4965 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<4>.SI | spidatain<4> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<3> | 4964 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<4>.D1 | 5218 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<4>.D2 | 5219 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<3> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<4>.CLKF | 5220 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<4>.RSTF | 5221 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<4>.CE | 5222 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<4>.REG | spidatain<4> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<4>.D | 5217 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<4>.CLKF | 5220 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<4>.RSTF | 5221 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<4>.CE | 5222 | ? | 0 | 4096 | spidatain<4> | NULL | NULL | spidatain<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<4>.Q | 5223 | ? | 0 | 0 | spidatain<4> | NULL | NULL | spidatain<4>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<5> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<4> | 4965 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<5> | 4966 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<5>.SI | spidatain<5> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<4> | 4965 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<5>.D1 | 5225 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<5>.D2 | 5226 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<4> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<5>.CLKF | 5227 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<5>.RSTF | 5228 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<5>.CE | 5229 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<5>.REG | spidatain<5> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<5>.D | 5224 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<5>.CLKF | 5227 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<5>.RSTF | 5228 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<5>.CE | 5229 | ? | 0 | 4096 | spidatain<5> | NULL | NULL | spidatain<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<5>.Q | 5230 | ? | 0 | 0 | spidatain<5> | NULL | NULL | spidatain<5>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<6> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<5> | 4966 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<6> | 4967 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<6>.SI | spidatain<6> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<5> | 4966 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<6>.D1 | 5232 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<6>.D2 | 5233 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<5> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<6>.CLKF | 5234 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<6>.RSTF | 5235 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<6>.CE | 5236 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<6>.REG | spidatain<6> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<6>.D | 5231 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<6>.CLKF | 5234 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<6>.RSTF | 5235 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<6>.CE | 5236 | ? | 0 | 4096 | spidatain<6> | NULL | NULL | spidatain<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<6>.Q | 5237 | ? | 0 | 0 | spidatain<6> | NULL | NULL | spidatain<6>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | spidatain<7> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<6> | 4967 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidatain<7> | 4968 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidatain<7>.SI | spidatain<7> | 0 | 5 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<6> | 4967 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidatain<7>.D1 | 5239 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidatain<7>.D2 | 5240 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | spidatain<6> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidatain<7>.CLKF | 5241 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | spidatain<7>.RSTF | 5242 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidatain<7>.CE | 5243 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 + +SRFF_INSTANCE | spidatain<7>.REG | spidatain<7> | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidatain<7>.D | 5238 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidatain<7>.CLKF | 5241 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | spidatain<7>.RSTF | 5242 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidatain<7>.CE | 5243 | ? | 0 | 4096 | spidatain<7> | NULL | NULL | spidatain<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidatain<7>.Q | 5244 | ? | 0 | 0 | spidatain<7> | NULL | NULL | spidatain<7>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | int_sclk | spi6502b_COPY_0_COPY_0 | 2155873280 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier.EXP | 5431 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.EXP | ier | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_sclk | 4969 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q + +SIGNAL_INSTANCE | int_sclk.SI | int_sclk | 0 | 8 | 5 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier.EXP | 5431 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.EXP | ier | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_sclk.D1 | 5246 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 1 | IV_TRUE | cpol +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_sclk.D2 | 5247 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | ier.EXP +SPPTERM | 5 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpha | IV_TRUE | shiftcnt<0> | IV_FALSE | shiftdone | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | int_sclk.CLKF | 5248 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | int_sclk.SETF | 5249 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_TRUE | cpol +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | int_sclk.RSTF | 5250 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_FALSE | cpol + +SRFF_INSTANCE | int_sclk.REG | int_sclk | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_sclk.D | 5245 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | int_sclk.CLKF | 5248 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | int_sclk.SETF | 5249 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_TRUE | cpol +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | int_sclk.RSTF | 5250 | ? | 0 | 4096 | int_sclk | NULL | NULL | int_sclk.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 2 | IV_FALSE | cpu_Nres_IBUF | IV_FALSE | cpol +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_sclk.Q | 5251 | ? | 0 | 0 | int_sclk | NULL | NULL | int_sclk.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | shiftcnt<3> | spi6502b_COPY_0_COPY_0 | 2155877376 | 7 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | shiftcnt<3>.SI | shiftcnt<3> | 0 | 7 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | shiftcnt<3>.D1 | 5253 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | shiftcnt<3>.D2 | 5254 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | shiftcnt<3> | IV_FALSE | shifting2 +SPPTERM | 4 | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | shiftcnt<3>.CLKF | 5255 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | shiftcnt<3>.RSTF | 5256 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF + +SRFF_INSTANCE | shiftcnt<3>.REG | shiftcnt<3> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | shiftcnt<3>.D | 5252 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | shiftcnt<3>.CLKF | 5255 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | shiftcnt<3>.RSTF | 5256 | ? | 0 | 4096 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | shiftcnt<3>.Q | 5257 | ? | 0 | 0 | shiftcnt<3> | NULL | NULL | shiftcnt<3>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped | shiftcnt<2> | spi6502b_COPY_0_COPY_0 | 2155877376 | 6 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | shiftcnt<2>.SI | shiftcnt<2> | 0 | 6 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | shiftcnt<2>.D1 | 5259 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | shiftcnt<2>.D2 | 5260 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | shiftcnt<2> | IV_FALSE | shifting2 +SPPTERM | 3 | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | shiftcnt<2>.CLKF | 5261 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | shiftcnt<2>.RSTF | 5262 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF + +SRFF_INSTANCE | shiftcnt<2>.REG | shiftcnt<2> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | shiftcnt<2>.D | 5258 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | shiftcnt<2>.CLKF | 5261 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | shiftcnt<2>.RSTF | 5262 | ? | 0 | 4096 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | shiftcnt<2>.Q | 5263 | ? | 0 | 0 | shiftcnt<2> | NULL | NULL | shiftcnt<2>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<0> | spi6502b_COPY_0_COPY_0 | 2155873280 | 4 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | shiftcnt<0>.SI | shiftcnt<0> | 0 | 4 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | shiftcnt<0>.D1 | 5265 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | shiftcnt<0>.D2 | 5266 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | shiftcnt<0> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | shiftcnt<0>.CLKF | 5267 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | shiftcnt<0>.RSTF | 5268 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF + +SRFF_INSTANCE | shiftcnt<0>.REG | shiftcnt<0> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | shiftcnt<0>.D | 5264 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | shiftcnt<0>.CLKF | 5267 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | shiftcnt<0>.RSTF | 5268 | ? | 0 | 4096 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | shiftcnt<0>.Q | 5269 | ? | 0 | 0 | shiftcnt<0> | NULL | NULL | shiftcnt<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftcnt<1> | spi6502b_COPY_0_COPY_0 | 2155873280 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | shiftcnt<1>.SI | shiftcnt<1> | 0 | 5 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | shiftcnt<1>.D1 | 5271 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | shiftcnt<1>.D2 | 5272 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 3 | IV_TRUE | shiftcnt<0> | IV_FALSE | shiftcnt<1> | IV_TRUE | shifting2 +SPPTERM | 3 | IV_FALSE | shiftcnt<0> | IV_TRUE | shiftcnt<1> | IV_TRUE | shifting2 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | shiftcnt<1>.CLKF | 5273 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | shiftcnt<1>.RSTF | 5274 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF + +SRFF_INSTANCE | shiftcnt<1>.REG | shiftcnt<1> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | shiftcnt<1>.D | 5270 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | shiftcnt<1>.CLKF | 5273 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | shiftcnt<1>.RSTF | 5274 | ? | 0 | 4096 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | shiftcnt<1>.Q | 5275 | ? | 0 | 0 | shiftcnt<1> | NULL | NULL | shiftcnt<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped | shiftdone | spi6502b_COPY_0_COPY_0 | 2155873280 | 6 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | shiftdone.SI | shiftdone | 0 | 6 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<0> | 4972 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<0>.Q | shiftcnt<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | shiftdone.D1 | 5277 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | shiftdone.D2 | 5278 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<0> | IV_TRUE | shiftcnt<1> +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | shiftdone.CLKF | 5279 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | shiftdone.RSTF | 5280 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF + +SRFF_INSTANCE | shiftdone.REG | shiftdone | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | shiftdone.D | 5276 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | shiftdone.CLKF | 5279 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | shiftdone.RSTF | 5280 | ? | 0 | 4096 | shiftdone | NULL | NULL | shiftdone.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | cpu_Nres_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | shiftdone.Q | 5281 | ? | 0 | 0 | shiftdone | NULL | NULL | shiftdone.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | start_shifting | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 5044 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | start_shifting.SI | start_shifting | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 5044 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | start_shifting.D1 | 5283 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | start_shifting.D2 | 5284 | ? | 0 | 6144 | start_shifting | NULL | NULL | start_shifting.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_FALSE | cpu_rnw_IBUF | IV_FALSE | start_shifting | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF +SPPTERM | 4 | IV_TRUE | frx | IV_FALSE | start_shifting | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | start_shifting.CLKF | 5285 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 6 | 9 | MC_SI_RSTF +SIGNAL | NODE | start_shifting.RSTF | 5286 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | start_shifting/start_shifting_RSTF__$INT.UIM + +SRFF_INSTANCE | start_shifting.REG | start_shifting | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | start_shifting.D | 5282 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | start_shifting.CLKF | 5285 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 3 | 8 | SRFF_R +SIGNAL | NODE | start_shifting.RSTF | 5286 | ? | 0 | 4096 | start_shifting | NULL | NULL | start_shifting.SI | 6 | 9 | MC_SI_RSTF +SPPTERM | 1 | IV_FALSE | start_shifting/start_shifting_RSTF__$INT.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | start_shifting.Q | 5287 | ? | 0 | 0 | start_shifting | NULL | NULL | start_shifting.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+OptxMapped+Ce | tc | spi6502b_COPY_0_COPY_0 | 2424308736 | 9 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_0_IBUF | 5021 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_1_IBUF | 5018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | tc | 4976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | tc.EXP | 5428 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.EXP | tc | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | tc.SI | tc | 0 | 9 | 6 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_0_IBUF | 5021 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_miso_1_IBUF | 5018 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_miso_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | tc.D1 | 5289 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | tc.D2 | 5290 | ? | 0 | 6144 | tc | NULL | NULL | tc.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | tc.CLKF | 5291 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 5 | 9 | MC_SI_SETF +SIGNAL | NODE | tc.SETF | 5292 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_TRUE | shiftdone +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | tc.EXP | 5424 | ? | 0 | 0 | tc | NULL | NULL | tc.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 2 | IV_FALSE | slavesel<0> | IV_TRUE | spi_miso_0_IBUF +SPPTERM | 2 | IV_FALSE | slavesel<1> | IV_TRUE | spi_miso_1_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | tc.CE | 5293 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF + +SRFF_INSTANCE | tc.REG | tc | 0 | 4 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | tc.D | 5288 | ? | 0 | 0 | tc | NULL | NULL | tc.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | tc.CLKF | 5291 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 2 | 8 | SRFF_S +SIGNAL | NODE | tc.SETF | 5292 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 5 | 9 | MC_SI_SETF +SPPTERM | 1 | IV_TRUE | shiftdone +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | tc.CE | 5293 | ? | 0 | 4096 | tc | NULL | NULL | tc.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | tc.Q | 5294 | ? | 0 | 0 | tc | NULL | NULL | tc.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<0> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<0> | 4977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<0> | 4977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<0>.SI | spidataout<0> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<0> | 4977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3455 | 5006 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3455 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<0>.D1 | 5296 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<0>.D2 | 5297 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<0> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3455 +SPPTERM | 4 | IV_FALSE | spidataout<0> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3455 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<0>.CLKF | 5298 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<0>.CE | 5299 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<0>.REG | spidataout<0> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<0>.D | 5295 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<0>.CLKF | 5298 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<0>.CE | 5299 | ? | 0 | 4096 | spidataout<0> | NULL | NULL | spidataout<0>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<0>.Q | 5300 | ? | 0 | 0 | spidataout<0> | NULL | NULL | spidataout<0>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<1> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<1> | 4978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<1> | 4978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<1>.SI | spidataout<1> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<1> | 4978 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<1>.Q | spidataout<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3457 | 5007 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3457 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<1>.D1 | 5302 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<1>.D2 | 5303 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<1> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3457 +SPPTERM | 4 | IV_FALSE | spidataout<1> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3457 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<1>.CLKF | 5304 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<1>.CE | 5305 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<1>.REG | spidataout<1> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<1>.D | 5301 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<1>.CLKF | 5304 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<1>.CE | 5305 | ? | 0 | 4096 | spidataout<1> | NULL | NULL | spidataout<1>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<1>.Q | 5306 | ? | 0 | 0 | spidataout<1> | NULL | NULL | spidataout<1>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<2> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<2> | 4979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<2> | 4979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<2>.SI | spidataout<2> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<2> | 4979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3459 | 5008 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3459 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<2>.D1 | 5308 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<2>.D2 | 5309 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<2> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3459 +SPPTERM | 4 | IV_FALSE | spidataout<2> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3459 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<2>.CLKF | 5310 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<2>.CE | 5311 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<2>.REG | spidataout<2> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<2>.D | 5307 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<2>.CLKF | 5310 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<2>.CE | 5311 | ? | 0 | 4096 | spidataout<2> | NULL | NULL | spidataout<2>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<2>.Q | 5312 | ? | 0 | 0 | spidataout<2> | NULL | NULL | spidataout<2>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<3> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<3> | 4980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<3> | 4980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<3>.SI | spidataout<3> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<3> | 4980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3461 | 5009 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3461 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<3>.D1 | 5314 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<3>.D2 | 5315 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<3> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3461 +SPPTERM | 4 | IV_FALSE | spidataout<3> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3461 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<3>.CLKF | 5316 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<3>.CE | 5317 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<3>.REG | spidataout<3> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<3>.D | 5313 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<3>.CLKF | 5316 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<3>.CE | 5317 | ? | 0 | 4096 | spidataout<3> | NULL | NULL | spidataout<3>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<3>.Q | 5318 | ? | 0 | 0 | spidataout<3> | NULL | NULL | spidataout<3>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<4> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<4> | 4981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<4> | 4981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<4>.SI | spidataout<4> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<4> | 4981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3463 | 5010 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3463 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<4>.D1 | 5320 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<4>.D2 | 5321 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<4> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3463 +SPPTERM | 4 | IV_FALSE | spidataout<4> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3463 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<4>.CLKF | 5322 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<4>.CE | 5323 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<4>.REG | spidataout<4> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<4>.D | 5319 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<4>.CLKF | 5322 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<4>.CE | 5323 | ? | 0 | 4096 | spidataout<4> | NULL | NULL | spidataout<4>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<4>.Q | 5324 | ? | 0 | 0 | spidataout<4> | NULL | NULL | spidataout<4>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<5> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<5> | 4982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<5> | 4982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<5>.SI | spidataout<5> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<5> | 4982 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<5>.Q | spidataout<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<5>.D1 | 5326 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<5>.D2 | 5327 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<5> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3465 +SPPTERM | 4 | IV_FALSE | spidataout<5> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3465 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<5>.CLKF | 5328 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<5>.CE | 5329 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<5>.REG | spidataout<5> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<5>.D | 5325 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<5>.CLKF | 5328 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<5>.CE | 5329 | ? | 0 | 4096 | spidataout<5> | NULL | NULL | spidataout<5>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<5>.Q | 5330 | ? | 0 | 0 | spidataout<5> | NULL | NULL | spidataout<5>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<6> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<6> | 4983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<6> | 4983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<6>.SI | spidataout<6> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<6> | 4983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3467 | 5011 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3467 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<6>.D1 | 5332 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<6>.D2 | 5333 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<6> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3467 +SPPTERM | 4 | IV_FALSE | spidataout<6> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3467 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<6>.CLKF | 5334 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<6>.CE | 5335 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<6>.REG | spidataout<6> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<6>.D | 5331 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<6>.CLKF | 5334 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<6>.CE | 5335 | ? | 0 | 4096 | spidataout<6> | NULL | NULL | spidataout<6>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<6>.Q | 5336 | ? | 0 | 0 | spidataout<6> | NULL | NULL | spidataout<6>.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | PrldLow+Tff+OptxMapped+Ce | spidataout<7> | spi6502b_COPY_0_COPY_0 | 2424312832 | 8 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<7> | 4984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3469 | 5012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3469 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | spidataout<7> | 4984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | spidataout<7>.SI | spidataout<7> | 0 | 8 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<7> | 4984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3469 | 5012 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3469 | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | spidataout<7>.D1 | 5338 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | spidataout<7>.D2 | 5339 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 4 | IV_TRUE | spidataout<7> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_FALSE | N3469 +SPPTERM | 4 | IV_FALSE | spidataout<7> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | N3469 +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | spidataout<7>.CLKF | 5340 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +OUTPUT_NODE_TYPE | 10 | 9 | MC_SI_CE +SIGNAL | NODE | spidataout<7>.CE | 5341 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF + +SRFF_INSTANCE | spidataout<7>.REG | spidataout<7> | 0 | 3 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | spidataout<7>.D | 5337 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | spidataout<7>.CLKF | 5340 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 2 | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF +INPUT_NODE_TYPE | 4 | 8 | SRFF_CE +SIGNAL | NODE | spidataout<7>.CE | 5341 | ? | 0 | 4096 | spidataout<7> | NULL | NULL | spidataout<7>.SI | 10 | 9 | MC_SI_CE +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | cpu_rnw_IBUF +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | spidataout<7>.Q | 5342 | ? | 0 | 0 | spidataout<7> | NULL | NULL | spidataout<7>.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | cpu_Nphi2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | cpu_Nphi2 | 5060 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<0> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<0> | 4961 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<0> | 4958 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<0> | 4987 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<0>$OE | 4988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<0>.SI | int_dout<0> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<0> | 4961 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<0>.Q | spidatain<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<0> | 4958 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<0>.Q | divisor<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpha | 4950 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpha.Q | cpha | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<0>.D1 | 5344 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<0>.D2 | 5345 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpha | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<0> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<0> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<0>.TRST | 5347 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<0>.REG | int_dout<0> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<0>.D | 5343 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<0>.Q | 5348 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<0>.BUFOE | int_dout<0> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<0>.TRST | 5347 | ? | 0 | 4096 | int_dout<0> | NULL | NULL | int_dout<0>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<0>.BUFOE.OUT | 5346 | ? | 0 | 0 | int_dout<0> | NULL | NULL | int_dout<0>.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<1> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<1> | 4962 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<1> | 4959 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<1> | 4989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<1>$OE | 4990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<1>.SI | int_dout<1> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<1> | 4962 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<1>.Q | spidatain<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<1> | 4959 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<1>.Q | divisor<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpol | 4948 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpol.Q | cpol | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<1> | 4943 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<1>.D1 | 5350 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<1>.D2 | 5351 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpol | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<1> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<1> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<1>.TRST | 5353 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<1>.REG | int_dout<1> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<1>.D | 5349 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<1>.Q | 5354 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<1>.BUFOE | int_dout<1> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<1>.TRST | 5353 | ? | 0 | 4096 | int_dout<1> | NULL | NULL | int_dout<1>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<1>.BUFOE.OUT | 5352 | ? | 0 | 0 | int_dout<1> | NULL | NULL | int_dout<1>.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<2> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<2> | 4963 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<2> | 4960 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<2> | 4991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<2>$OE | 4992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<2>.SI | int_dout<2> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<2> | 4963 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<2>.Q | spidatain<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | divisor<2> | 4960 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | divisor<2>.Q | divisor<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<2> | 4945 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<2>.D1 | 5356 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<2>.D2 | 5357 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ece | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | divisor<2> | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<2> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<2>.TRST | 5359 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<2>.REG | int_dout<2> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<2>.D | 5355 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<2>.Q | 5360 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<2>.BUFOE | int_dout<2> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<2>.TRST | 5359 | ? | 0 | 4096 | int_dout<2> | NULL | NULL | int_dout<2>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<2>.BUFOE.OUT | 5358 | ? | 0 | 0 | int_dout<2> | NULL | NULL | int_dout<2>.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<3> | spi6502b_COPY_0_COPY_0 | 2155888640 | 9 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<3> | 4964 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<3> | 4993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<3>$OE | 4994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<3>.SI | int_dout<3> | 0 | 9 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<3> | 4964 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<3>.Q | spidatain<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tmo | 4957 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tmo.Q | tmo | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<3> | 4947 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<3>.D1 | 5362 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<3>.D2 | 5363 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slavesel<3> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | tmo | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<3> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<3>.TRST | 5365 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<3>.REG | int_dout<3> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<3>.D | 5361 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<3>.Q | 5366 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<3>.BUFOE | int_dout<3> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<3>.TRST | 5365 | ? | 0 | 4096 | int_dout<3> | NULL | NULL | int_dout<3>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<3>.BUFOE.OUT | 5364 | ? | 0 | 0 | int_dout<3> | NULL | NULL | int_dout<3>.BUFOE | 0 | 10 | BUF_OUT + +INPUT_INSTANCE | 0 | 0 | NULL | spi_int_0_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_int<0> | 5055 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_int_0_IBUF | 5017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_0_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<4> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<4> | 4965 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_0_IBUF | 5017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<4> | 4995 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<4>$OE | 4996 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<4>.SI | int_dout<4> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<4> | 4965 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<4>.Q | spidatain<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_0_IBUF | 5017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | frx | 4951 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | frx.Q | frx | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<4>.D1 | 5368 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<4>.D2 | 5369 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | frx | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten<0> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<4> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | spi_int_0_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<4>.TRST | 5371 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<4>.REG | int_dout<4> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<4>.D | 5367 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<4>.Q | 5372 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<4>.BUFOE | int_dout<4> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<4>.TRST | 5371 | ? | 0 | 4096 | int_dout<4> | NULL | NULL | int_dout<4>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<4>.BUFOE.OUT | 5370 | ? | 0 | 0 | int_dout<4> | NULL | NULL | int_dout<4>.BUFOE | 0 | 10 | BUF_OUT + +INPUT_INSTANCE | 0 | 0 | NULL | spi_int_1_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_int<1> | 5054 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_int_1_IBUF | 5016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_1_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<5> | spi6502b_COPY_0_COPY_0 | 2155888640 | 11 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<5> | 4966 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2.EXP | 5423 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<5> | 4997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<5>$OE | 4998 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<5>.SI | int_dout<5> | 0 | 11 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<5> | 4966 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<5>.Q | spidatain<5> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2.EXP | 5423 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<5>.D1 | 5374 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<5>.D2 | 5375 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 1 | IV_TRUE | shifting2.EXP +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<5> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | start_shifting | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | shifting2 | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<5>.TRST | 5377 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<5>.REG | int_dout<5> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<5>.D | 5373 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<5>.Q | 5378 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<5>.BUFOE | int_dout<5> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<5>.TRST | 5377 | ? | 0 | 4096 | int_dout<5> | NULL | NULL | int_dout<5>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<5>.BUFOE.OUT | 5376 | ? | 0 | 0 | int_dout<5> | NULL | NULL | int_dout<5>.BUFOE | 0 | 10 | BUF_OUT + +INPUT_INSTANCE | 0 | 0 | NULL | spi_int_2_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_int<2> | 5053 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_int_2_IBUF | 5015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_2_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<6> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<6> | 4967 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_2_IBUF | 5015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<6> | 4999 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<6>$OE | 5000 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<6>.SI | int_dout<6> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<6> | 4967 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<6>.Q | spidatain<6> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_2_IBUF | 5015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<6>.D1 | 5380 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<6>.D2 | 5381 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | ier | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten<2> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<6> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | spi_int_2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<6>.TRST | 5383 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<6>.REG | int_dout<6> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<6>.D | 5379 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<6>.Q | 5384 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<6>.BUFOE | int_dout<6> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<6>.TRST | 5383 | ? | 0 | 4096 | int_dout<6> | NULL | NULL | int_dout<6>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<6>.BUFOE.OUT | 5382 | ? | 0 | 0 | int_dout<6> | NULL | NULL | int_dout<6>.BUFOE | 0 | 10 | BUF_OUT + +INPUT_INSTANCE | 0 | 0 | NULL | spi_int_3_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | spi_int<3> | 5052 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | spi_int_3_IBUF | 5014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_3_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | PinTrst+OptxMapped | int_dout<7> | spi6502b_COPY_0_COPY_0 | 2155888640 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<7> | 4968 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_3_IBUF | 5014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tc | 4976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | int_dout<7> | 5001 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | int_dout<7>$OE | 5002 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | int_dout<7>.SI | int_dout<7> | 0 | 10 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidatain<7> | 4968 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidatain<7>.Q | spidatain<7> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_3_IBUF | 5014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tc | 4976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | int_dout<7>.D1 | 5386 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | int_dout<7>.D2 | 5387 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | slaveinten<3> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | spidatain<7> | IV_FALSE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | tc | IV_FALSE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | spi_int_3_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | int_dout<7>.TRST | 5389 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | int_dout<7>.REG | int_dout<7> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | int_dout<7>.D | 5385 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | int_dout<7>.Q | 5390 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | int_dout<7>.BUFOE | int_dout<7> | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | int_dout<7>.TRST | 5389 | ? | 0 | 4096 | int_dout<7> | NULL | NULL | int_dout<7>.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 4 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_TRUE | cpu_Nphi2_IBUF +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | int_dout<7>.BUFOE.OUT | 5388 | ? | 0 | 0 | int_dout<7> | NULL | NULL | int_dout<7>.BUFOE | 0 | 10 | BUF_OUT + +MACROCELL_INSTANCE | PrldLow+OptxMapped | shifting2 | spi6502b_COPY_0_COPY_0 | 2155873280 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_1_IBUF | 5016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | shifting2.EXP | 5423 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.EXP | shifting2 | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | shifting2.SI | shifting2 | 0 | 10 | 4 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_rnw_IBUF | 4939 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_rnw_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cs1_IBUF | 5003 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cs1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | Ncs2_IBUF | 5004 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | Ncs2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_1_IBUF | 5016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | shifting2.D1 | 5392 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | shifting2.D2 | 5393 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_FALSE | shiftdone | IV_TRUE | start_shifting +OUTPUT_NODE_TYPE | 3 | 9 | MC_SI_CLKF +SIGNAL | NODE | shifting2.CLKF | 5394 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | shifting2.EXP | 5422 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 7 | IV_TRUE | cpu_rnw_IBUF | IV_TRUE | cpu_a_1_IBUF | IV_FALSE | cpu_a_0_IBUF | IV_TRUE | cs1_IBUF | IV_FALSE | Ncs2_IBUF | IV_FALSE | spi_int_1_IBUF | IV_TRUE | cpu_Nphi2_IBUF + +SRFF_INSTANCE | shifting2.REG | shifting2 | 0 | 2 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | shifting2.D | 5391 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.XOR | 0 | 7 | ALU_F +INPUT_NODE_TYPE | 1 | 8 | SRFF_C +SIGNAL | NODE | shifting2.CLKF | 5394 | ? | 0 | 4096 | shifting2 | NULL | NULL | shifting2.SI | 3 | 9 | MC_SI_CLKF +SPPTERM | 1 | IV_FALSE | $OpTx$INV$22__$INT.UIM +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | shifting2.Q | 5395 | ? | 0 | 0 | shifting2 | NULL | NULL | shifting2.REG | 0 | 8 | SRFF_Q + +INPUT_INSTANCE | 0 | 0 | NULL | extclk_IBUF | spi6502b_COPY_0_COPY_0 | 16 | 1 | 1 +INPUT_NODE_TYPE | 0 | 5 | II_IN +NODE | extclk | 5061 | PI | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | NULL | 0 | 100 | NOTYPE +OUTPUT_NODE_TYPE | 0 | 5 | II_IMUX +NODE | extclk_IBUF | 5023 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX + +MACROCELL_INSTANCE | OptxMapped | diag_OBUF | spi6502b_COPY_0_COPY_0 | 2155872256 | 7 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | diag_OBUF | 5024 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | diag_OBUF.Q | diag_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | diag_OBUF.EXP | 5429 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | diag_OBUF.EXP | diag_OBUF | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | diag_OBUF.SI | diag_OBUF | 0 | 7 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slavesel<0> | 4941 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_1_IBUF | 4985 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_1_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_a_0_IBUF | 4986 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_a_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | N3465 | 5013 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | N3465 | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | diag_OBUF.D1 | 5397 | ? | 0 | 4096 | diag_OBUF | NULL | NULL | diag_OBUF.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | diag_OBUF.D2 | 5398 | ? | 0 | 4096 | diag_OBUF | NULL | NULL | diag_OBUF.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 3 | IV_TRUE | slavesel<0> | IV_FALSE | start_shifting | IV_FALSE | shifting2 +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | diag_OBUF.EXP | 5425 | ? | 0 | 0 | diag_OBUF | NULL | NULL | diag_OBUF.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 4 | IV_TRUE | slaveinten<1> | IV_TRUE | cpu_a_1_IBUF | IV_TRUE | cpu_a_0_IBUF | IV_FALSE | N3465 + +SRFF_INSTANCE | diag_OBUF.REG | diag_OBUF | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | diag_OBUF.D | 5396 | ? | 0 | 0 | diag_OBUF | NULL | NULL | diag_OBUF.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | diag_OBUF.Q | 5399 | ? | 0 | 0 | diag_OBUF | NULL | NULL | diag_OBUF.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | FbkInv+PinTrst+Merge+OptxMapped | cpu_Nirq_OBUFE | spi6502b_COPY_0_COPY_0 | 2155923456 | 1 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 5045 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 0 | 0 | MC_Q +NODE | cpu_Nirq_OBUFE$Q | 5025 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 2 | 0 | MC_OE +NODE | cpu_Nirq_OBUFE$OE | 5026 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE + +SIGNAL_INSTANCE | cpu_Nirq_OBUFE.SI | cpu_Nirq_OBUFE | 0 | 1 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 5045 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | cpu_Nirq_OBUFE.D1 | 5401 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | cpu_Nirq_OBUFE.D2 | 5402 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 4 | 9 | MC_SI_TRST +SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 5404 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 1 | IV_TRUE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM + +SRFF_INSTANCE | cpu_Nirq_OBUFE.REG | cpu_Nirq_OBUFE | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | cpu_Nirq_OBUFE.D | 5400 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | cpu_Nirq_OBUFE.Q | 5405 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.REG | 0 | 8 | SRFF_Q + +BUF_INSTANCE | cpu_Nirq_OBUFE.BUFOE | cpu_Nirq_OBUFE | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 10 | CTOR_UNKNOWN +SIGNAL | NODE | cpu_Nirq_OBUFE.TRST | 5404 | ? | 0 | 4096 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.SI | 4 | 9 | MC_SI_TRST +SPPTERM | 1 | IV_TRUE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM +OUTPUT_NODE_TYPE | 0 | 10 | BUF_OUT +NODE | cpu_Nirq_OBUFE.BUFOE.OUT | 5403 | ? | 0 | 0 | cpu_Nirq_OBUFE | NULL | NULL | cpu_Nirq_OBUFE.BUFOE | 0 | 10 | BUF_OUT + +OUTPUT_INSTANCE | 0 | spi_mosi | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_mosi | 4937 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.Q | int_mosi | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_mosi$OE | 4938 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_mosi.BUFOE.OUT | int_mosi | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | spi_mosi | 5027 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_mosi | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | spi_Nsel<0> | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | slavesel<0>$Q | 4940 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<0>.Q | slavesel<0> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | spi_Nsel<0> | 5028 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel<0> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | spi_Nsel<1> | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | slavesel<1>$Q | 4942 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<1>.Q | slavesel<1> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | spi_Nsel<1> | 5029 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel<1> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | spi_Nsel<2> | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | slavesel<2>$Q | 4944 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<2>.Q | slavesel<2> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | spi_Nsel<2> | 5030 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel<2> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | spi_Nsel<3> | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | slavesel<3>$Q | 4946 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slavesel<3>.Q | slavesel<3> | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | spi_Nsel<3> | 5031 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_Nsel<3> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | spi_sclk | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_sclk | 4969 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_sclk.Q | int_sclk | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | spi_sclk | 5032 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_sclk | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<0> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<0> | 4987 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.Q | int_dout<0> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<0>$OE | 4988 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<0>.BUFOE.OUT | int_dout<0> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<0> | 5033 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<0> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<1> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<1> | 4989 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.Q | int_dout<1> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<1>$OE | 4990 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<1>.BUFOE.OUT | int_dout<1> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<1> | 5034 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<1> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<2> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<2> | 4991 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.Q | int_dout<2> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<2>$OE | 4992 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<2>.BUFOE.OUT | int_dout<2> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<2> | 5035 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<2> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<3> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<3> | 4993 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.Q | int_dout<3> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<3>$OE | 4994 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<3>.BUFOE.OUT | int_dout<3> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<3> | 5036 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<3> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<4> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<4> | 4995 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.Q | int_dout<4> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<4>$OE | 4996 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<4>.BUFOE.OUT | int_dout<4> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<4> | 5037 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<4> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<5> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<5> | 4997 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.Q | int_dout<5> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<5>$OE | 4998 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<5>.BUFOE.OUT | int_dout<5> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<5> | 5038 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<5> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<6> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<6> | 4999 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.Q | int_dout<6> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<6>$OE | 5000 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<6>.BUFOE.OUT | int_dout<6> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<6> | 5039 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<6> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_d<7> | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | int_dout<7> | 5001 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.Q | int_dout<7> | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | int_dout<7>$OE | 5002 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | int_dout<7>.BUFOE.OUT | int_dout<7> | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_d<7> | 5040 | PIPO | 0 | 64 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_d<7> | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | diag | spi6502b_COPY_0_COPY_0 | 7 | 1 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | diag_OBUF | 5024 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | diag_OBUF.Q | diag_OBUF | 0 | 0 | MC_Q +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | diag | 5041 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | diag | 0 | 6 | OI_OUT + +OUTPUT_INSTANCE | 0 | cpu_Nirq | spi6502b_COPY_0_COPY_0 | 7 | 2 | 1 +INPUT_NODE_TYPE | 0 | 6 | OI_IN +NODE | cpu_Nirq_OBUFE$Q | 5025 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.Q | cpu_Nirq_OBUFE | 0 | 0 | MC_Q +INPUT_NODE_TYPE | 2 | 6 | OI_OE +NODE | cpu_Nirq_OBUFE$OE | 5026 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE.BUFOE.OUT | cpu_Nirq_OBUFE | 2 | 0 | MC_OE +OUTPUT_NODE_TYPE | 0 | 6 | OI_OUT +NODE | cpu_Nirq | 5042 | PO | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nirq | 0 | 6 | OI_OUT + +MACROCELL_INSTANCE | SoftPfbk | $OpTx$INV$22__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 5 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | extclk_IBUF | 5023 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | $OpTx$INV$22__$INT.UIM | 5043 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | $OpTx$INV$22__$INT.Q | $OpTx$INV$22__$INT | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | $OpTx$INV$22__$INT.SI | $OpTx$INV$22__$INT | 0 | 5 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ece | 4949 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ece.Q | ece | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nphi2_IBUF | 5022 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nphi2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | extclk_IBUF | 5023 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | extclk_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | start_shifting | 4975 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting.Q | start_shifting | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | $OpTx$INV$22__$INT.D1 | 5407 | ? | 0 | 4096 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | $OpTx$INV$22__$INT.D2 | 5408 | ? | 0 | 4096 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | ece | IV_FALSE | extclk_IBUF +SPPTERM | 2 | IV_FALSE | ece | IV_FALSE | cpu_Nphi2_IBUF +SPPTERM | 2 | IV_FALSE | start_shifting | IV_FALSE | shifting2 + +SRFF_INSTANCE | $OpTx$INV$22__$INT.REG | $OpTx$INV$22__$INT | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | $OpTx$INV$22__$INT.D | 5406 | ? | 0 | 0 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | $OpTx$INV$22__$INT.Q | 5409 | ? | 0 | 0 | $OpTx$INV$22__$INT | NULL | NULL | $OpTx$INV$22__$INT.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | SoftPfbk | start_shifting/start_shifting_RSTF__$INT | spi6502b_COPY_0_COPY_0 | 2181038080 | 8 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<3> | 4980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<7> | 4984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | start_shifting/start_shifting_RSTF__$INT.UIM | 5044 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.Q | start_shifting/start_shifting_RSTF__$INT | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | start_shifting/start_shifting_RSTF__$INT.EXP | 5420 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | start_shifting/start_shifting_RSTF__$INT.EXP | start_shifting/start_shifting_RSTF__$INT | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | start_shifting/start_shifting_RSTF__$INT.SI | start_shifting/start_shifting_RSTF__$INT | 0 | 8 | 3 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | cpu_Nres_IBUF | 4936 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | cpu_Nres_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<3> | 4980 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<3>.Q | spidataout<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<7> | 4984 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<7>.Q | spidataout<7> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D1 | 5411 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.D2 | 5412 | ? | 0 | 4096 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | cpu_Nres_IBUF | IV_FALSE | shiftdone +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | start_shifting/start_shifting_RSTF__$INT.EXP | 5418 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<3> | IV_TRUE | shifting2 +SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_FALSE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<7> | IV_TRUE | shifting2 + +SRFF_INSTANCE | start_shifting/start_shifting_RSTF__$INT.REG | start_shifting/start_shifting_RSTF__$INT | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | start_shifting/start_shifting_RSTF__$INT.D | 5410 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | start_shifting/start_shifting_RSTF__$INT.Q | 5413 | ? | 0 | 0 | start_shifting/start_shifting_RSTF__$INT | NULL | NULL | start_shifting/start_shifting_RSTF__$INT.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | SoftPfbk | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | spi6502b_COPY_0_COPY_0 | 2181038080 | 10 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tc | 4976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_3_IBUF | 5014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_2_IBUF | 5015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_0_IBUF | 5017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_1_IBUF | 5016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 0 | MC_UIM +NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | 5045 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | 0 | MC_UIM + +SIGNAL_INSTANCE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 0 | 10 | 2 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | ier | 4952 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | ier.Q | ier | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | tc | 4976 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | tc.Q | tc | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<3> | 4956 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<3>.Q | slaveinten<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_3_IBUF | 5014 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_3_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<2> | 4955 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<2>.Q | slaveinten<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_2_IBUF | 5015 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_2_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<0> | 4953 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<0>.Q | slaveinten<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_0_IBUF | 5017 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_0_IBUF | 0 | 5 | II_IMUX +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | slaveinten<1> | 4954 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | slaveinten<1>.Q | slaveinten<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spi_int_1_IBUF | 5016 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | NULL | spi_int_1_IBUF | 0 | 5 | II_IMUX +OUTPUT_NODE_TYPE | 1 | 9 | MC_SI_D1 +SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D1 | 5415 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 1 | 9 | MC_SI_D1 +SPPTERM | 0 | IV_ZERO +OUTPUT_NODE_TYPE | 2 | 9 | MC_SI_D2 +SIGNAL | NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D2 | 5416 | ? | 0 | 4096 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.SI | 2 | 9 | MC_SI_D2 +SPPTERM | 2 | IV_TRUE | ier | IV_TRUE | tc +SPPTERM | 2 | IV_TRUE | slaveinten<0> | IV_FALSE | spi_int_0_IBUF +SPPTERM | 2 | IV_TRUE | slaveinten<1> | IV_FALSE | spi_int_1_IBUF +SPPTERM | 2 | IV_TRUE | slaveinten<2> | IV_FALSE | spi_int_2_IBUF +SPPTERM | 2 | IV_TRUE | slaveinten<3> | IV_FALSE | spi_int_3_IBUF + +SRFF_INSTANCE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 0 | 1 | 1 +INPUT_NODE_TYPE | 0 | 8 | SRFF_D +NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.D | 5414 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.XOR | 0 | 7 | ALU_F +OUTPUT_NODE_TYPE | 0 | 8 | SRFF_Q +NODE | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.Q | 5417 | ? | 0 | 0 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | NULL | NULL | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.REG | 0 | 8 | SRFF_Q + +MACROCELL_INSTANCE | NULL | EXP6_ | spi6502b_COPY_0_COPY_0 | 2147483648 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<0> | 4977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<2> | 4979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<4> | 4981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<6> | 4983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 4 | 0 | MC_EXPORT +NODE | EXP6_.EXP | 5421 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | EXP6_.EXP | EXP6_ | 4 | 0 | MC_EXPORT + +SIGNAL_INSTANCE | EXP6_.SI | EXP6_ | 0 | 9 | 1 +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<3> | 4970 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<3>.Q | shiftcnt<3> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<2> | 4971 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<2>.Q | shiftcnt<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftcnt<1> | 4973 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftcnt<1>.Q | shiftcnt<1> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shiftdone | 4974 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shiftdone.Q | shiftdone | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<0> | 4977 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<0>.Q | spidataout<0> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | shifting2 | 5005 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | shifting2.Q | shifting2 | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<2> | 4979 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<2>.Q | spidataout<2> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<4> | 4981 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<4>.Q | spidataout<4> | 1 | 0 | MC_UIM +INPUT_NODE_TYPE | 1 | 100 | NOTYPE +NODE | spidataout<6> | 4983 | ? | 0 | 0 | spi6502b_COPY_0_COPY_0 | NULL | spidataout<6>.Q | spidataout<6> | 1 | 0 | MC_UIM +OUTPUT_NODE_TYPE | 7 | 9 | MC_SI_EXPORT +SIGNAL | NODE | EXP6_.EXP | 5419 | ? | 0 | 0 | EXP6_ | NULL | NULL | EXP6_.SI | 7 | 9 | MC_SI_EXPORT +SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<0> | IV_TRUE | shifting2 +SPPTERM | 6 | IV_TRUE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<2> | IV_TRUE | shifting2 +SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_TRUE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<4> | IV_TRUE | shifting2 +SPPTERM | 6 | IV_FALSE | shiftcnt<3> | IV_FALSE | shiftcnt<2> | IV_TRUE | shiftcnt<1> | IV_FALSE | shiftdone | IV_FALSE | spidataout<6> | IV_TRUE | shifting2 + +FB_INSTANCE | FOOBAR1_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | spidataout<3> | 1 | NULL | 0 | NULL | 0 +FBPIN | 2 | spidataout<2> | 1 | spi_int_3_IBUF | 0 | NULL | 0 | 1 | 49152 +FBPIN | 3 | spidataout<1> | 1 | NULL | 0 | NULL | 0 +FBPIN | 4 | spidataout<0> | 1 | NULL | 0 | NULL | 0 +FBPIN | 5 | int_dout<0> | 1 | N3455 | 1 | cpu_d<0> | 1 | 2 | 49152 +FBPIN | 6 | int_dout<1> | 1 | N3457 | 1 | cpu_d<1> | 1 | 3 | 49152 +FBPIN | 7 | tmo | 1 | NULL | 0 | NULL | 0 +FBPIN | 8 | int_dout<2> | 1 | N3459 | 1 | cpu_d<2> | 1 | 4 | 49152 +FBPIN | 9 | slaveinten<0> | 1 | cpu_Nphi2_IBUF | 0 | NULL | 0 | 5 | 57344 +FBPIN | 10 | frx | 1 | NULL | 0 | NULL | 0 +FBPIN | 11 | ece | 1 | extclk_IBUF | 0 | NULL | 0 | 6 | 57344 +FBPIN | 12 | divisor<2> | 1 | NULL | 0 | NULL | 0 +FBPIN | 13 | divisor<1> | 1 | NULL | 0 | NULL | 0 +FBPIN | 14 | divisor<0> | 1 | cpu_rnw_IBUF | 0 | NULL | 0 | 7 | 57344 +FBPIN | 15 | int_dout<3> | 1 | N3461 | 1 | cpu_d<3> | 1 | 8 | 49152 +FBPIN | 16 | cpol | 1 | NULL | 0 | NULL | 0 +FBPIN | 17 | int_dout<4> | 1 | N3463 | 1 | cpu_d<4> | 1 | 9 | 49152 +FBPIN | 18 | cpha | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR2_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | start_shifting/start_shifting_RSTF__$INT | 1 | NULL | 0 | NULL | 0 +FBPIN | 2 | int_mosi | 1 | NULL | 0 | spi_mosi | 1 | 35 | 49152 +FBPIN | 3 | EXP6_ | 1 | NULL | 0 | NULL | 0 +FBPIN | 6 | NULL | 0 | spi_miso_3_IBUF | 0 | NULL | 0 | 37 | 49152 +FBPIN | 8 | NULL | 0 | spi_miso_2_IBUF | 0 | NULL | 0 | 38 | 49152 +FBPIN | 9 | NULL | 0 | spi_int_2_IBUF | 0 | NULL | 0 | 39 | 51200 +FBPIN | 11 | NULL | 0 | spi_int_1_IBUF | 0 | NULL | 0 | 40 | 53248 +FBPIN | 14 | NULL | 0 | spi_int_0_IBUF | 0 | NULL | 0 | 42 | 53248 +FBPIN | 15 | NULL | 0 | spi_miso_1_IBUF | 0 | NULL | 0 | 43 | 49152 +FBPIN | 17 | NULL | 0 | spi_miso_0_IBUF | 0 | NULL | 0 | 44 | 49152 + +FB_INSTANCE | FOOBAR3_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | shifting2 | 1 | NULL | 0 | NULL | 0 +FBPIN | 2 | int_dout<5> | 1 | N3465 | 1 | cpu_d<5> | 1 | 11 | 49152 +FBPIN | 3 | shiftdone | 1 | NULL | 0 | NULL | 0 +FBPIN | 4 | $OpTx$INV$22__$INT | 1 | NULL | 0 | NULL | 0 +FBPIN | 5 | int_dout<6> | 1 | N3467 | 1 | cpu_d<6> | 1 | 12 | 49152 +FBPIN | 6 | start_shifting | 1 | NULL | 0 | NULL | 0 +FBPIN | 7 | spidatain<7> | 1 | NULL | 0 | NULL | 0 +FBPIN | 8 | int_dout<7> | 1 | N3469 | 1 | cpu_d<7> | 1 | 13 | 49152 +FBPIN | 9 | cpu_Nirq_OBUFE | 1 | NULL | 0 | cpu_Nirq | 1 | 14 | 49152 +FBPIN | 10 | spidatain<6> | 1 | NULL | 0 | NULL | 0 +FBPIN | 11 | spidatain<5> | 1 | Ncs2_IBUF | 0 | NULL | 0 | 18 | 49152 +FBPIN | 12 | spidatain<4> | 1 | NULL | 0 | NULL | 0 +FBPIN | 13 | spidatain<3> | 1 | NULL | 0 | NULL | 0 +FBPIN | 14 | spidatain<2> | 1 | cpu_Nres_IBUF | 0 | NULL | 0 | 19 | 49152 +FBPIN | 15 | spidatain<1> | 1 | cs1_IBUF | 0 | NULL | 0 | 20 | 49152 +FBPIN | 16 | shiftcnt<3> | 1 | cpu_a_1_IBUF | 0 | NULL | 0 | 24 | 49152 +FBPIN | 17 | shiftcnt<2> | 1 | cpu_a_0_IBUF | 0 | NULL | 0 | 22 | 49152 +FBPIN | 18 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | FOOBAR4_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 +FBPIN | 1 | tc | 1 | NULL | 0 | NULL | 0 +FBPIN | 2 | slavesel<3> | 1 | NULL | 0 | spi_Nsel<3> | 1 | 25 | 49152 +FBPIN | 3 | shiftcnt<0> | 1 | NULL | 0 | NULL | 0 +FBPIN | 4 | spidataout<7> | 1 | NULL | 0 | NULL | 0 +FBPIN | 5 | slavesel<2> | 1 | NULL | 0 | spi_Nsel<2> | 1 | 26 | 49152 +FBPIN | 6 | spidataout<6> | 1 | NULL | 0 | NULL | 0 +FBPIN | 7 | spidataout<5> | 1 | NULL | 0 | NULL | 0 +FBPIN | 8 | slavesel<1> | 1 | NULL | 0 | spi_Nsel<1> | 1 | 27 | 49152 +FBPIN | 9 | spidataout<4> | 1 | NULL | 0 | NULL | 0 +FBPIN | 10 | shiftcnt<1> | 1 | NULL | 0 | NULL | 0 +FBPIN | 11 | slavesel<0> | 1 | NULL | 0 | spi_Nsel<0> | 1 | 28 | 49152 +FBPIN | 12 | slaveinten<3> | 1 | NULL | 0 | NULL | 0 +FBPIN | 13 | slaveinten<2> | 1 | NULL | 0 | NULL | 0 +FBPIN | 14 | diag_OBUF | 1 | NULL | 0 | diag | 1 | 29 | 49152 +FBPIN | 15 | slaveinten<1> | 1 | NULL | 0 | NULL | 0 | 33 | 49152 +FBPIN | 16 | ier | 1 | NULL | 0 | NULL | 0 +FBPIN | 17 | int_sclk | 1 | NULL | 0 | spi_sclk | 1 | 34 | 49152 +FBPIN | 18 | spidatain<0> | 1 | NULL | 0 | NULL | 0 + +FB_INSTANCE | INPUTPINS_FOOBAR5_ | spi6502b_COPY_0_COPY_0 | 0 | 0 | 0 + +BUSINFO | CPU_A<1:0> | 2 | 0 | 0 | cpu_a<0> | 1 | cpu_a<1> | 0 +BUSINFO | CPU_D<7:0> | 8 | 0 | 2 | cpu_d<0> | 7 | cpu_d<1> | 6 | cpu_d<2> | 5 | cpu_d<3> | 4 | cpu_d<4> | 3 | cpu_d<5> | 2 | cpu_d<6> | 1 | cpu_d<7> | 0 +BUSINFO | SPI_INT<3:0> | 4 | 0 | 0 | spi_int<0> | 3 | spi_int<1> | 2 | spi_int<2> | 1 | spi_int<3> | 0 +BUSINFO | SPI_MISO<3:0> | 4 | 0 | 0 | spi_miso<0> | 3 | spi_miso<1> | 2 | spi_miso<2> | 1 | spi_miso<3> | 0 +BUSINFO | SPI_NSEL<3:0> | 4 | 0 | 1 | spi_Nsel<0> | 3 | spi_Nsel<1> | 2 | spi_Nsel<2> | 1 | spi_Nsel<3> | 0 + +FB_ORDER_OF_INPUTS | FOOBAR1_ | 0 | spidataout<3> | NULL | 1 | spidataout<2> | NULL | 2 | spidataout<1> | NULL | 3 | spidataout<0> | NULL | 4 | cpu_d<3> | 8 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 5 | Ncs2 | 18 | 6 | tmo | NULL | 8 | spi_int<0> | 42 | 10 | slavesel<0> | NULL | 11 | divisor<2> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 12 | divisor<1> | NULL | 13 | divisor<0> | NULL | 15 | cs1 | 20 | 17 | spidatain<0> | NULL | 18 | slavesel<3> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 22 | slavesel<2> | NULL | 26 | spidatain<4> | NULL | 29 | cpu_d<0> | 2 | 31 | cpu_rnw | 7 | 32 | slavesel<1> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 33 | cpu_d<1> | 3 | 36 | cpu_a<0> | 22 | 39 | cpu_a<1> | 24 | 40 | cpu_d<2> | 4 | 41 | slaveinten<0> | NULL +FB_ORDER_OF_INPUTS | FOOBAR1_ | 42 | spidatain<3> | NULL | 43 | cpha | NULL | 44 | cpu_d<4> | 9 | 45 | frx | NULL | 46 | cpu_Nres | 19 +FB_ORDER_OF_INPUTS | FOOBAR1_ | 48 | spidatain<2> | NULL | 50 | ece | NULL | 51 | spidatain<1> | NULL | 52 | cpol | NULL | 53 | cpu_Nphi2 | 5 + +FB_IMUX_INDEX | FOOBAR1_ | 0 | 1 | 2 | 3 | 130 | 131 | 6 | -1 | 98 | -1 | 64 | 11 | 12 | 13 | -1 | 123 | -1 | 71 | 55 | -1 | -1 | -1 | 58 | -1 | -1 | -1 | 47 | -1 | -1 | 108 | -1 | 126 | 61 | 110 | -1 | -1 | 121 | -1 | -1 | 111 | 114 | 8 | 48 | 17 | 132 | 9 | 125 | -1 | 49 | -1 | 10 | 50 | 15 | 120 + + +FB_ORDER_OF_INPUTS | FOOBAR2_ | 3 | $OpTx$INV$22__$INT.UIM | NULL | 8 | spidataout<4> | NULL | 16 | shiftcnt<2> | NULL | 17 | cpu_Nres | 19 | 30 | spidataout<6> | NULL +FB_ORDER_OF_INPUTS | FOOBAR2_ | 33 | spidataout<3> | NULL | 35 | shifting2 | NULL | 36 | shiftcnt<3> | NULL | 37 | spidataout<1> | NULL | 39 | tmo | NULL +FB_ORDER_OF_INPUTS | FOOBAR2_ | 44 | spidataout<2> | NULL | 45 | shiftdone | NULL | 46 | spidataout<0> | NULL | 48 | spidataout<7> | NULL | 49 | spidataout<5> | NULL +FB_ORDER_OF_INPUTS | FOOBAR2_ | 50 | shiftcnt<1> | NULL + +FB_IMUX_INDEX | FOOBAR2_ | -1 | -1 | -1 | 39 | -1 | -1 | -1 | -1 | 62 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 52 | 125 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | -1 | 59 | -1 | -1 | 0 | -1 | 36 | 51 | 2 | -1 | 6 | -1 | -1 | -1 | -1 | 1 | 38 | 3 | -1 | 57 | 60 | 63 | -1 | -1 | -1 + + +FB_ORDER_OF_INPUTS | FOOBAR3_ | 0 | start_shifting/start_shifting_RSTF__$INT.UIM | NULL | 2 | spi_int<1> | 40 | 3 | $OpTx$INV$22__$INT.UIM | NULL | 5 | start_shifting | NULL | 6 | spidatain<7> | NULL +FB_ORDER_OF_INPUTS | FOOBAR3_ | 8 | slaveinten<0> | NULL | 9 | frx | NULL | 10 | ece | NULL | 11 | spidatain<4> | NULL | 12 | cpu_Nphi2 | 5 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 13 | spidatain<2> | NULL | 14 | spidatain<1> | NULL | 15 | shiftcnt<3> | NULL | 16 | shiftcnt<2> | NULL | 17 | cpu_Nirq_OBUFE/cpu_Nirq_OBUFE_TRST.UIM | NULL +FB_ORDER_OF_INPUTS | FOOBAR3_ | 20 | shiftcnt<0> | NULL | 24 | cs1 | 20 | 26 | ier | NULL | 27 | slaveinten<1> | NULL | 30 | spi_int<3> | 1 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 31 | cpu_rnw | 7 | 34 | spidatain<3> | NULL | 35 | shifting2 | NULL | 36 | cpu_a<0> | 22 | 39 | cpu_a<1> | 24 +FB_ORDER_OF_INPUTS | FOOBAR3_ | 40 | tc | NULL | 42 | spi_int<0> | 42 | 43 | spidatain<6> | NULL | 44 | slaveinten<3> | NULL | 45 | shiftdone | NULL +FB_ORDER_OF_INPUTS | FOOBAR3_ | 46 | cpu_Nres | 19 | 47 | Ncs2 | 18 | 48 | extclk | 6 | 49 | spidatain<5> | NULL | 50 | shiftcnt<1> | NULL +FB_ORDER_OF_INPUTS | FOOBAR3_ | 51 | slaveinten<2> | NULL | 52 | spi_int<2> | 39 | 53 | spidatain<0> | NULL + +FB_IMUX_INDEX | FOOBAR3_ | 18 | -1 | 92 | 39 | -1 | 41 | 42 | -1 | 8 | 9 | 10 | 47 | 120 | 49 | 50 | 51 | 52 | 53 | -1 | -1 | 56 | -1 | -1 | -1 | 123 | -1 | 69 | 68 | -1 | -1 | 106 | 126 | -1 | -1 | 48 | 36 | 121 | -1 | -1 | 111 | 54 | -1 | 98 | 45 | 65 | 38 | 125 | 131 | 122 | 46 | 63 | 66 | 86 | 71 + + +FB_ORDER_OF_INPUTS | FOOBAR4_ | 0 | shifting2 | NULL | 1 | slavesel<3> | NULL | 2 | shiftdone | NULL | 3 | spidataout<7> | NULL | 4 | slavesel<2> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 5 | spidataout<6> | NULL | 6 | spidataout<5> | NULL | 7 | slavesel<1> | NULL | 8 | spidataout<4> | NULL | 9 | shiftcnt<1> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 10 | slavesel<0> | NULL | 11 | slaveinten<3> | NULL | 12 | slaveinten<2> | NULL | 13 | cpu_a<0> | 22 | 14 | slaveinten<1> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 15 | cpol | NULL | 16 | cpu_d<7> | 13 | 17 | cpu_Nres | 19 | 18 | cpu_a<1> | 24 | 20 | shiftcnt<0> | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 21 | cpu_d<6> | 12 | 23 | cpha | NULL | 24 | cs1 | 20 | 26 | ier | NULL | 28 | spi_miso<3> | 37 +FB_ORDER_OF_INPUTS | FOOBAR4_ | 29 | cpu_d<0> | 2 | 31 | cpu_rnw | 7 | 33 | cpu_d<1> | 3 | 35 | Ncs2 | 18 | 39 | $OpTx$INV$22__$INT.UIM | NULL +FB_ORDER_OF_INPUTS | FOOBAR4_ | 40 | cpu_d<2> | 4 | 42 | cpu_d<5> | 11 | 43 | spi_miso<2> | 38 | 44 | cpu_d<4> | 9 | 45 | spi_miso<1> | 43 +FB_ORDER_OF_INPUTS | FOOBAR4_ | 46 | start_shifting | NULL | 47 | spi_miso<0> | 44 | 53 | cpu_d<3> | 8 + +FB_IMUX_INDEX | FOOBAR4_ | 36 | 55 | 38 | 57 | 58 | 59 | 60 | 61 | 62 | 63 | 64 | 65 | 66 | 121 | 68 | 15 | 142 | 125 | 111 | -1 | 56 | 138 | -1 | 17 | 123 | -1 | 69 | -1 | 82 | 108 | -1 | 126 | -1 | 110 | -1 | 131 | -1 | -1 | -1 | 39 | 114 | -1 | 134 | 84 | 132 | 102 | 41 | 104 | -1 | -1 | -1 | -1 | -1 | 130 + diff --git a/spi6502b.xml b/spi6502b.xml new file mode 100644 index 0000000..3b47ab2 --- /dev/null +++ b/spi6502b.xml @@ -0,0 +1,3 @@ + + +spi6502b.rptC:/Xilinx/xc9500xl/data/xc9572xl.chpspi6502b.mfd
diff --git a/spi6502b_build.xml b/spi6502b_build.xml new file mode 100644 index 0000000..b0ba209 --- /dev/null +++ b/spi6502b_build.xml @@ -0,0 +1,205 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/spi6502b_pad.csv b/spi6502b_pad.csv new file mode 100644 index 0000000..99598ac --- /dev/null +++ b/spi6502b_pad.csv @@ -0,0 +1,73 @@ +Release 6.1i - Fit G.38 +Copyright(c) 1995-2003 Xilinx Inc. All rights reserved + + 5- 6-2017 5:27PM + +NOTE: This file is designed to be imported into a spreadsheet program +such as Microsoft Excel for viewing, printing and sorting. The comma ',' +character is used as the data field separator. +This file is also designed to support parsing. + +Input file: spi6502b.ngd +output file: spi6502b_pad.csv +Part type: xc9572xl +Speed grade: -10 +Package: pc44 + +Pinout by Pin Number: + +-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,{blank},Slew Rate,Termination,{blank},Voltage,Constraint, +P1,spi_int<3>,I,I/O,INPUT,,,,,,,,, +P2,cpu_d<0>,I/O,I/O,BIDIR,,,,,,,,, +P3,cpu_d<1>,I/O,I/O,BIDIR,,,,,,,,, +P4,cpu_d<2>,I/O,I/O,BIDIR,,,,,,,,, +P5,cpu_Nphi2,I,I/O/GCK1,INPUT,,,,,,,,, +P6,extclk,I,I/O/GCK2,INPUT,,,,,,,,, +P7,cpu_rnw,I,I/O/GCK3,INPUT,,,,,,,,, +P8,cpu_d<3>,I/O,I/O,BIDIR,,,,,,,,, +P9,cpu_d<4>,I/O,I/O,BIDIR,,,,,,,,, +P10,GND,,GND,,,,,,,,,, +P11,cpu_d<5>,I/O,I/O,BIDIR,,,,,,,,, +P12,cpu_d<6>,I/O,I/O,BIDIR,,,,,,,,, +P13,cpu_d<7>,I/O,I/O,BIDIR,,,,,,,,, +P14,cpu_Nirq,O,I/O,OUTPUT,,,,,,,,, +P15,TDI,,TDI,,,,,,,,,, +P16,TMS,,TMS,,,,,,,,,, +P17,TCK,,TCK,,,,,,,,,, +P18,Ncs2,I,I/O,INPUT,,,,,,,,, +P19,cpu_Nres,I,I/O,INPUT,,,,,,,,, +P20,cs1,I,I/O,INPUT,,,,,,,,, +P21,VCC,,VCCINT,,,,,,,,,, +P22,cpu_a<0>,I,I/O,INPUT,,,,,,,,, +P23,GND,,GND,,,,,,,,,, +P24,cpu_a<1>,I,I/O,INPUT,,,,,,,,, +P25,spi_Nsel<3>,O,I/O,OUTPUT,,,,,,,,, +P26,spi_Nsel<2>,O,I/O,OUTPUT,,,,,,,,, +P27,spi_Nsel<1>,O,I/O,OUTPUT,,,,,,,,, +P28,spi_Nsel<0>,O,I/O,OUTPUT,,,,,,,,, +P29,diag,O,I/O,OUTPUT,,,,,,,,, +P30,TDO,,TDO,,,,,,,,,, +P31,GND,,GND,,,,,,,,,, +P32,VCC,,VCCIO,,,,,,,,,, +P33,TIE,,I/O,,,,,,,,,, +P34,spi_sclk,O,I/O,OUTPUT,,,,,,,,, +P35,spi_mosi,O,I/O,OUTPUT,,,,,,,,, +P36,TIE,,I/O,,,,,,,,,, +P37,spi_miso<3>,I,I/O,INPUT,,,,,,,,, +P38,spi_miso<2>,I,I/O,INPUT,,,,,,,,, +P39,spi_int<2>,I,I/O/GSR,INPUT,,,,,,,,, +P40,spi_int<1>,I,I/O/GTS2,INPUT,,,,,,,,, +P41,VCC,,VCCINT,,,,,,,,,, +P42,spi_int<0>,I,I/O/GTS1,INPUT,,,,,,,,, +P43,spi_miso<1>,I,I/O,INPUT,,,,,,,,, +P44,spi_miso<0>,I,I/O,INPUT,,,,,,,,, + +To preserve the pinout above for future design iterations in +Project Navigator simply execute the (Lock Pins) process +located under the (Implement Design) process in a toolbox named +(Optional Implementation Tools) or invoke PIN2UCF from the +command line. The location constraints will be written into your +specified UCF file + + diff --git a/tmperr.err b/tmperr.err new file mode 100644 index 0000000..e69de29 diff --git a/userlang.tpl b/userlang.tpl new file mode 100644 index 0000000..7f80404 --- /dev/null +++ b/userlang.tpl @@ -0,0 +1,6 @@ +[Verilog.User Templates] +type=folder +[VHDL.User Templates] +type=folder +[ABEL.User Templates] +type=folder