forked from Apple-2-HW/AppleIISd
Test bench worst and best case timings
This commit is contained in:
parent
8a6e7e647e
commit
2e4ebd9ac0
@ -39,10 +39,10 @@ Port (
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data_in : in STD_LOGIC_VECTOR (7 downto 0);
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data_in : in STD_LOGIC_VECTOR (7 downto 0);
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data_out : out STD_LOGIC_VECTOR (7 downto 0);
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data_out : out STD_LOGIC_VECTOR (7 downto 0);
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is_read : in STD_LOGIC;
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is_read : in STD_LOGIC;
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reset : in STD_LOGIC;
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nreset : in STD_LOGIC;
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addr : in STD_LOGIC_VECTOR (1 downto 0);
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addr : in STD_LOGIC_VECTOR (1 downto 0);
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phi0 : in STD_LOGIC;
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phi0 : in STD_LOGIC;
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selected : in STD_LOGIC;
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ndev_sel : in STD_LOGIC;
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clk : in STD_LOGIC;
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clk : in STD_LOGIC;
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miso: in std_logic;
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miso: in std_logic;
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mosi : out STD_LOGIC;
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mosi : out STD_LOGIC;
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@ -105,9 +105,9 @@ begin
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end if;
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end if;
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end process;
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end process;
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process(shiftcnt, reset, shiftclk)
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process(shiftcnt, nreset, shiftclk)
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begin
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begin
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if (reset = '1') then
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if (nreset = '0') then
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shiftdone <= '0';
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shiftdone <= '0';
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elsif (rising_edge(shiftclk)) then
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elsif (rising_edge(shiftclk)) then
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if (shiftcnt = "1111") then
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if (shiftcnt = "1111") then
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@ -118,9 +118,9 @@ begin
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end if;
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end if;
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end process;
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end process;
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process(reset, shifting2, shiftcnt, shiftclk)
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process(nreset, shifting2, shiftcnt, shiftclk)
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begin
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begin
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if (reset='1') then
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if (nreset = '0') then
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shiftcnt <= (others => '0');
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shiftcnt <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1') then
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if (shifting2 = '1') then
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@ -132,9 +132,9 @@ begin
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end if;
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end if;
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end process;
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end process;
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inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, miso)
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inproc: process(nreset, shifting2, shiftcnt, shiftclk, spidatain, miso)
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begin
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begin
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if (reset='1') then
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if (nreset = '0') then
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spidatain <= (others => '0');
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spidatain <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1' and shiftcnt(0) = '1') then
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if (shifting2 = '1' and shiftcnt(0) = '1') then
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@ -145,9 +145,9 @@ begin
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end if;
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end if;
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end process;
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end process;
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outproc: process(reset, shifting2, spidataout, shiftcnt, shiftclk)
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outproc: process(nreset, shifting2, spidataout, shiftcnt, shiftclk)
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begin
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begin
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if (reset='1') then
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if (nreset = '0') then
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mosi <= '1';
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mosi <= '1';
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sclk <= '0';
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sclk <= '0';
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else
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else
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@ -177,12 +177,12 @@ begin
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-- shift operation enable
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-- shift operation enable
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shiften: process(reset, selected, is_read, addr, frx, shiftdone)
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shiften: process(nreset, ndev_sel, is_read, addr, frx, shiftdone)
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begin
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begin
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-- start shifting
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-- start shifting
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if (reset='1' or shiftdone='1') then
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if (nreset = '0' or shiftdone = '1') then
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start_shifting <= '0';
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start_shifting <= '0';
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elsif (falling_edge(selected) and addr="00" and (frx='1' or is_read='0')) then
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elsif (rising_edge(ndev_sel) and addr="00" and (frx='1' or is_read='0')) then
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-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
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-- access to register 00, either write (is_read=0) or fast receive bit set (frx)
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-- then both types of access (write but also read)
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-- then both types of access (write but also read)
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start_shifting <= '1';
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start_shifting <= '1';
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@ -198,9 +198,9 @@ begin
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--shiftclk <= clksrc when divcnt = "000000" else '0';
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--shiftclk <= clksrc when divcnt = "000000" else '0';
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shiftclk <= clksrc when bsy = '1' else '0';
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shiftclk <= clksrc when bsy = '1' else '0';
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-- clkgen: process(reset, divisor, clksrc)
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-- clkgen: process(nreset, divisor, clksrc)
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-- begin
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-- begin
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-- if (reset='1') then
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-- if (nreset = '0') then
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-- divcnt <= divisor;
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-- divcnt <= divisor;
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-- elsif (falling_edge(clksrc)) then
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-- elsif (falling_edge(clksrc)) then
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-- if (shiftclk = '1') then
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-- if (shiftclk = '1') then
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@ -219,11 +219,11 @@ begin
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-- outputs
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-- outputs
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nsel <= slavesel;
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nsel <= slavesel;
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tc_proc: process (selected, shiftdone)
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tc_proc: process (ndev_sel, shiftdone)
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begin
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begin
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if (shiftdone = '1') then
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if (shiftdone = '1') then
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tc <= '1';
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tc <= '1';
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elsif (falling_edge(selected) and addr="00") then
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elsif (rising_edge(ndev_sel) and addr="00") then
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tc <= '0';
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tc <= '0';
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end if;
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end if;
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end process;
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end process;
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@ -261,9 +261,9 @@ begin
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end process;
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end process;
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-- cpu write
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-- cpu write
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cpu_write: process(reset, selected, is_read, addr, data_in, card, inited)
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cpu_write: process(nreset, ndev_sel, is_read, addr, data_in, card, inited)
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begin
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begin
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if (reset = '1') then
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if (nreset = '0') then
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ece <= '0';
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ece <= '0';
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frx <= '0';
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frx <= '0';
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slavesel <= '1';
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slavesel <= '1';
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@ -272,7 +272,7 @@ begin
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inited <= '0';
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inited <= '0';
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elsif (card = '1') then
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elsif (card = '1') then
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inited <= '0';
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inited <= '0';
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elsif (falling_edge(selected) and is_read = '0') then
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elsif (rising_edge(ndev_sel) and is_read = '0') then
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case addr is
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case addr is
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when "00" => -- write SPI data out (see other process above)
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when "00" => -- write SPI data out (see other process above)
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spidataout <= data_in;
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spidataout <= data_in;
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@ -21,18 +21,14 @@
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</file>
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</file>
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<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
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<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</file>
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<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</file>
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<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="25"/>
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</file>
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<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="IO.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</file>
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<file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="IO_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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@ -152,8 +148,8 @@
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<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/IO_Test/uut" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.IO_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work." xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -163,7 +159,7 @@
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<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.IO_Test" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work." xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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@ -77,10 +77,10 @@ Port (
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data_in : in std_logic_vector (7 downto 0);
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data_in : in std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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data_out : out std_logic_vector (7 downto 0);
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is_read : in std_logic;
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is_read : in std_logic;
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reset : in std_logic;
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nreset : in std_logic;
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addr : in std_logic_vector (1 downto 0);
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addr : in std_logic_vector (1 downto 0);
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phi0 : in std_logic;
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phi0 : in std_logic;
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selected : in std_logic;
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ndev_sel : in std_logic;
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clk : in std_logic;
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clk : in std_logic;
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miso: in std_logic;
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miso: in std_logic;
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mosi : out std_logic;
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mosi : out std_logic;
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@ -115,10 +115,10 @@ begin
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data_in => data_in,
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data_in => data_in,
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data_out => data_out,
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data_out => data_out,
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is_read => rnw_int,
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is_read => rnw_int,
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reset => not NRESET,
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nreset => NRESET,
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addr => addr_low_int,
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addr => addr_low_int,
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phi0 => PHI0,
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phi0 => PHI0,
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selected => not ndev_sel_int,
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ndev_sel => ndev_sel_int,
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clk => CLK,
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clk => CLK,
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miso => miso_int,
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miso => miso_int,
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mosi => MOSI,
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mosi => MOSI,
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@ -104,6 +104,16 @@ ARCHITECTURE behavior OF IO_Test IS
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-- Clock period definitions
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-- Clock period definitions
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constant CLK_period : time := 142 ns;
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constant CLK_period : time := 142 ns;
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-- Bus timings
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-- worst case
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constant ADD_valid : time := 300 ns; -- II+
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constant DATA_valid : time := 200 ns; -- II+
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constant ADD_hold : time := 15 ns; -- IIgs
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--best case
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--constant ADD_valid : time := 100 ns; -- IIgs
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--constant DATA_valid : time := 30 ns; -- IIgs
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--constant ADD_hold : time := 15 ns; -- IIgs
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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@ -169,8 +179,9 @@ BEGIN
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-- read reg 0
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-- read reg 0
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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ADD_LOW <= (others => 'U');
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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wait for 300 ns;
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_LOW <= (others => '0');
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RNW <= '1';
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RNW <= '1';
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DATA <= (others => 'U');
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DATA <= (others => 'U');
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@ -179,12 +190,12 @@ BEGIN
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for 15 ns;
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_LOW <= (others => 'U');
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-- read reg 3
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-- read reg 3
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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wait for 300 ns;
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wait for ADD_valid;
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ADD_LOW <= (others => '1');
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ADD_LOW <= (others => '1');
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RNW <= '1';
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RNW <= '1';
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DATA <= (others => 'U');
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DATA <= (others => 'U');
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@ -193,23 +204,23 @@ BEGIN
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for 15 ns;
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wait for ADD_hold;
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ADD_LOW <= (others => 'U');
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ADD_LOW <= (others => 'U');
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-- send data
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-- send data
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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wait for 300 ns;
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_LOW <= (others => '0');
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RNW <= '0';
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RNW <= '0';
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DATA <= (others => 'U');
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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DATA <= (others => 'Z');
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DATA <= (others => 'Z');
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wait for 200 ns;
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wait for DATA_valid;
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DATA <= (others => '0');
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DATA <= (others => '0');
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for 15 ns;
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wait for ADD_hold;
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--wait for CLK_period;
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--wait for CLK_period;
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ADD_LOW <= (others => 'U');
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ADD_LOW <= (others => 'U');
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RNW <= '1';
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RNW <= '1';
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