forked from Apple-2-HW/AppleIISd
Fixes according to IIgs Tech Note #68
This commit is contained in:
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eeb0b14725
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723406657e
@ -31,43 +31,67 @@ use IEEE.STD_LOGIC_1164.ALL;
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entity AddressDecoder is
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entity AddressDecoder is
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Port ( A : in std_logic_vector (10 downto 8);
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Port ( A : in std_logic_vector (10 downto 8);
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B : out std_logic_vector (10 downto 8);
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B : out std_logic_vector (10 downto 8); -- to EPROM
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CLK : in std_logic;
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PHI0 : in std_logic;
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RNW : in std_logic;
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RNW : in std_logic;
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NDEV_SEL : in std_logic;
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NDEV_SEL : in std_logic; -- $C0n0 - $C0nF
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NIO_SEL : in std_logic;
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NIO_SEL : in std_logic; -- $Cs00 - $CsFF
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NIO_STB : in std_logic;
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NIO_STB : in std_logic; -- $C800 - $CFFF
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NRESET : in std_logic;
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NRESET : in std_logic;
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DATA_EN : out std_logic;
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DATA_EN : out std_logic; -- to CPLD
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NG : out std_logic;
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NG : out std_logic; -- to bus transceiver
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NOE : out std_logic);
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NOE : out std_logic); -- to EPROM
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end AddressDecoder;
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end AddressDecoder;
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architecture Behavioral of AddressDecoder is
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architecture Behavioral of AddressDecoder is
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signal cfxx : std_logic;
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signal cfxx : std_logic; -- $C800 - $CFFF disable
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signal noe_int : std_logic;
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signal noe_int : std_logic;
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signal ncs : std_logic;
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signal ndev_sel_int : std_logic;
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signal nio_sel_int : std_logic;
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signal nio_stb_int : std_logic;
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signal ncs : std_logic; -- $C800 - $CFFF enabled
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begin
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begin
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-- According to Apple IIgs Tech Note #68
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-- in order to prevent bus fights with video data,
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-- data from peripheral to CPU shall be valid on the bus
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-- only from the first rising edge of 7M when any select
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-- line is low (Phi0 high) to the falling edge of Phi0
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B <= A when (NIO_STB = '0') else (others => '0');
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B <= A when (NIO_STB = '0') else (others => '0');
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DATA_EN <= RNW and not NDEV_SEL;
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DATA_EN <= RNW and not ndev_sel_int and PHI0;
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NG <= NDEV_SEL and noe_int;
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NG <= (ndev_sel_int and noe_int) or not PHI0;
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NOE <= noe_int;
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NOE <= noe_int or not PHI0;
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noe_int <= not RNW or not NDEV_SEL
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noe_int <= not RNW or not ndev_sel_int
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or (NIO_SEL and NIO_STB)
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or (nio_sel_int and nio_stb_int)
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or (NIO_SEL and ncs);
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or (nio_sel_int and ncs);
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cfxx <= A(8) and A(9) and A(10) and not NIO_STB;
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cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
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process(NRESET, NIO_SEL, cfxx)
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process(NRESET, nio_sel_int, cfxx)
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begin
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begin
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if (NRESET = '0' or cfxx = '1') then
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if (NRESET = '0' or cfxx = '1') then
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ncs <= '1';
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ncs <= '1';
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elsif falling_edge(NIO_SEL) then
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elsif falling_edge(nio_sel_int) then
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ncs <= '0';
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ncs <= '0';
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end if;
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end if;
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end process;
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end process;
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process(NRESET, CLK)
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begin
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if(NRESET = '0') then
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ndev_sel_int <= '1';
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nio_sel_int <= '1';
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nio_stb_int <= '1';
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elsif rising_edge(CLK) then
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ndev_sel_int <= NDEV_SEL;
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nio_sel_int <= NIO_SEL;
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nio_stb_int <= NIO_STB;
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end if;
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end process;
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end Behavioral;
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end Behavioral;
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@ -43,6 +43,8 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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PORT(
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PORT(
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A : IN std_logic_vector(10 downto 8);
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A : IN std_logic_vector(10 downto 8);
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B : OUT std_logic_vector(10 downto 8);
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B : OUT std_logic_vector(10 downto 8);
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CLK : IN std_logic;
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PHI0 : IN std_logic;
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RNW : IN std_logic;
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RNW : IN std_logic;
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NDEV_SEL : IN std_logic;
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NDEV_SEL : IN std_logic;
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NIO_SEL : IN std_logic;
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NIO_SEL : IN std_logic;
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@ -62,6 +64,8 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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signal NIO_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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signal NIO_STB : std_logic := '1';
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signal NIO_STB : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal CLK : std_logic := '0';
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signal PHI0 : std_logic := '1';
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--Outputs
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--Outputs
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signal B : std_logic_vector(10 downto 8);
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signal B : std_logic_vector(10 downto 8);
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@ -69,12 +73,17 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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signal NG : std_logic;
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signal NG : std_logic;
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signal NOE : std_logic;
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signal NOE : std_logic;
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-- Clock period definitions
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constant CLK_period : time := 142 ns;
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BEGIN
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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-- Instantiate the Unit Under Test (UUT)
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uut: AddressDecoder PORT MAP (
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uut: AddressDecoder PORT MAP (
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A => A,
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A => A,
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B => B,
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B => B,
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CLK => CLK,
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PHI0 => PHI0,
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RNW => RNW,
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RNW => RNW,
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NDEV_SEL => NDEV_SEL,
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NDEV_SEL => NDEV_SEL,
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NIO_SEL => NIO_SEL,
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NIO_SEL => NIO_SEL,
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@ -85,50 +94,77 @@ BEGIN
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NOE => NOE
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NOE => NOE
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);
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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PHI0_process :process(CLK)
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variable counter : integer range 0 to 7;
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begin
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if rising_edge(CLK) or falling_edge(CLK) then
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counter := counter + 1;
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if counter = 7 then
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PHI0 <= not PHI0;
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counter := 0;
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end if;
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end if;
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end process;
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-- Stimulus process
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-- Stimulus process
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stim_proc: process
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stim_proc: process
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begin
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begin
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-- hold reset state for 100 ns.
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-- hold reset state.
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wait for 50 ns;
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wait for CLK_period * 10;
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NRESET <= '0';
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NRESET <= '0';
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wait for 50 ns;
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wait for CLK_period * 20;
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NRESET <= '1';
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NRESET <= '1';
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wait for 50 ns;
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wait for CLK_period * 10;
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-- insert stimulus here
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-- insert stimulus here
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-- CPLD access
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-- CPLD access
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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wait for 10 ns;
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for 20 ns;
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CnXX access
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-- CnXX access
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NIO_SEL <= '0';
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NIO_SEL <= '0';
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wait for 10 ns;
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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NIO_SEL <= '1';
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wait for 20 ns;
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C8xx access, selected
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-- C8xx access, selected
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NIO_STB <= '0';
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NIO_STB <= '0';
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wait for 10 ns;
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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NIO_STB <= '1';
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wait for 20 ns;
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CPLD access
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-- CPLD access
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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wait for 10 ns;
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait for 20 ns;
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CFFF access
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-- CFFF access
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A <= "111";
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A <= "111";
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NIO_STB <= '0';
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NIO_STB <= '0';
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wait for 10 ns;
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wait until falling_edge(PHI0);
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A <= "000";
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A <= "000";
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NIO_STB <= '1';
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NIO_STB <= '1';
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wait for 20 ns;
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C8xx access, unselected
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-- C8xx access, unselected
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NIO_STB <= '0';
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NIO_STB <= '0';
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wait for 10 ns;
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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NIO_STB <= '1';
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wait for 20 ns;
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait;
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wait;
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end process;
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end process;
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1110
VHDL/AppleIISd.jed
1110
VHDL/AppleIISd.jed
File diff suppressed because it is too large
Load Diff
@ -70,9 +70,7 @@ architecture Behavioral of AppleIISd is
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signal card_int : std_logic;
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signal card_int : std_logic;
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signal miso_int : std_logic;
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signal miso_int : std_logic;
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signal rnw_int : std_logic;
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signal data_en : std_logic;
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signal data_en : std_logic;
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signal ndev_sel_int : std_logic;
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component SpiController is
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component SpiController is
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Port (
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Port (
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@ -98,6 +96,8 @@ component AddressDecoder
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Port (
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Port (
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A : in std_logic_vector (10 downto 8);
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A : in std_logic_vector (10 downto 8);
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B : out std_logic_vector (10 downto 8);
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B : out std_logic_vector (10 downto 8);
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CLK : in std_logic;
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PHI0 : in std_logic;
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RNW : in std_logic;
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RNW : in std_logic;
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NDEV_SEL : in std_logic;
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NDEV_SEL : in std_logic;
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NIO_SEL : in std_logic;
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NIO_SEL : in std_logic;
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@ -113,7 +113,7 @@ begin
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spi: SpiController port map(
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spi: SpiController port map(
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data_in => data_in,
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data_in => data_in,
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data_out => data_out,
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data_out => data_out,
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is_read => rnw_int,
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is_read => RNW,
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nreset => NRESET,
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nreset => NRESET,
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addr => addr_low_int,
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addr => addr_low_int,
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phi0 => PHI0,
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phi0 => PHI0,
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@ -131,8 +131,10 @@ begin
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addDec: AddressDecoder port map(
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addDec: AddressDecoder port map(
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A => ADD_HIGH,
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A => ADD_HIGH,
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B => B,
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B => B,
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CLK => CLK,
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PHI0 => PHI0,
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RNW => RNW,
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RNW => RNW,
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NDEV_SEL => ndev_sel_int,
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NDEV_SEL => NDEV_SEL,
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NIO_SEL => NIO_SEL,
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NIO_SEL => NIO_SEL,
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NIO_STB => NIO_STB,
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NIO_STB => NIO_STB,
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NRESET => NRESET,
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NRESET => NRESET,
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@ -144,27 +146,16 @@ begin
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ctrl_latch: process(CLK, NRESET)
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ctrl_latch: process(CLK, NRESET)
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begin
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begin
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if(NRESET = '0') then
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if(NRESET = '0') then
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rnw_int <= '1';
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wp_int <= '1';
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wp_int <= '1';
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card_int <= '1';
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card_int <= '1';
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miso_int <= '1';
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miso_int <= '1';
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elsif falling_edge(CLK) then
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elsif falling_edge(CLK) then
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rnw_int <= RNW;
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wp_int <= WP;
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wp_int <= WP;
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card_int <= CARD;
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card_int <= CARD;
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miso_int <= MISO;
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miso_int <= MISO;
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end if;
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end if;
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end process;
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end process;
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process(CLK, NRESET)
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begin
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if(NRESET = '0') then
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ndev_sel_int <= '1';
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elsif rising_edge(CLK) then
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ndev_sel_int <= NDEV_SEL;
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end if;
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end process;
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DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
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DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
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-- synthesis translate_off
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-- synthesis translate_off
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@ -175,9 +166,9 @@ begin
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data_latch: process(CLK)
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data_latch: process(CLK)
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begin
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begin
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if falling_edge(CLK) then
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if falling_edge(CLK) then
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addr_low_int <= ADD_LOW;
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if (NDEV_SEL = '0') then
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if (NDEV_SEL = '0') then
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data_in <= DATA;
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data_in <= DATA;
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addr_low_int <= ADD_LOW;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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@ -76,7 +76,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
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signal NDEV_SEL : std_logic := '1';
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signal NDEV_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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signal NIO_STB : std_logic := '1';
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signal NIO_STB : std_logic := '1';
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signal PHI0 : std_logic := '0';
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signal PHI0 : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal NRESET : std_logic := '1';
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signal RNW : std_logic := '1';
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signal RNW : std_logic := '1';
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signal MISO : std_logic := '1';
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signal MISO : std_logic := '1';
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