forked from Apple-2-HW/AppleIISd
formatting
This commit is contained in:
freitz85
parent
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@ -3,401 +3,387 @@
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-- Engineer: A. Fachat
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--
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-- Create Date: 12:37:11 05/07/2011
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-- Design Name: SPI65B
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-- Design Name: SPI65B
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-- Module Name: SPI6502B - Behavioral
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-- Project Name: CS/A NETUSB 2.0
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-- Target Devices: CS/A NETUSB 2.0
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-- Tool versions:
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-- Description: An SPI interface for 6502-based computers (or compatible).
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-- modelled after the SPI65 interface by Daryl Rictor
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-- (see http://sbc.rictor.org/io/65spi.html )
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-- This implementation here, however, is a complete reimplementation
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-- as the ABEL language of the original implementation is not supported
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-- by ISE anymore.
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-- Also I added the interrupt input handling, replacing four of the
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-- original SPI select outputs with four interrupt inputs
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-- Also folded out the single MISO input into one input for each of the
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-- four supported devices, reducing external parts count again by one.
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-- Description: An SPI interface for 6502-based computers (or compatible).
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-- modelled after the SPI65 interface by Daryl Rictor
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-- (see http://sbc.rictor.org/io/65spi.html )
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-- This implementation here, however, is a complete reimplementation
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-- as the ABEL language of the original implementation is not supported
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-- by ISE anymore.
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-- Also I added the interrupt input handling, replacing four of the
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-- original SPI select outputs with four interrupt inputs
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-- Also folded out the single MISO input into one input for each of the
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-- four supported devices, reducing external parts count again by one.
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
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-- to drive up SPI clock to half of input clock (and not one fourth only as before)
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-- unfortunately that costed one divisor bit to fit into the CPLD
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-- to drive up SPI clock to half of input clock (and not one fourth only as before)
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-- unfortunately that costed one divisor bit to fit into the CPLD
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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--use AddressDecoder.ALL;
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use AddressDecoder.ALL;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity AppleIISd is
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Port ( data : inout STD_LOGIC_VECTOR (7 downto 0);
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nrw : in STD_LOGIC;
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nirq : out STD_LOGIC;
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nreset : in STD_LOGIC;
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addr : in STD_LOGIC_VECTOR (1 downto 0);
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nphi2 : in STD_LOGIC;
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ndev_sel : in STD_LOGIC;
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extclk : in STD_LOGIC;
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spi_miso: in std_logic;
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spi_mosi : out STD_LOGIC;
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spi_sclk : out STD_LOGIC;
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spi_Nsel : out STD_LOGIC;
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wp : in STD_LOGIC;
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card : in STD_LOGIC;
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led : out STD_LOGIC;
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Port (
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data : inout STD_LOGIC_VECTOR (7 downto 0);
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nrw : in STD_LOGIC;
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nirq : out STD_LOGIC;
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nreset : in STD_LOGIC;
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addr : in STD_LOGIC_VECTOR (1 downto 0);
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nphi2 : in STD_LOGIC;
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ndev_sel : in STD_LOGIC;
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extclk : in STD_LOGIC;
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spi_miso: in std_logic;
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spi_mosi : out STD_LOGIC;
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spi_sclk : out STD_LOGIC;
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spi_Nsel : out STD_LOGIC;
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wp : in STD_LOGIC;
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card : in STD_LOGIC;
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led : out STD_LOGIC;
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a8 : in std_logic;
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a9 : in std_logic;
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a10 : in std_logic;
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nio_sel : in std_logic;
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nio_stb : in std_logic;
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b8 : out std_logic;
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b9 : out std_logic;
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b10 : out std_logic;
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noe : out std_logic;
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ng : out std_logic
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);
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a8 : in std_logic;
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a9 : in std_logic;
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a10 : in std_logic;
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nio_sel : in std_logic;
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nio_stb : in std_logic;
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b8 : out std_logic;
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b9 : out std_logic;
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b10 : out std_logic;
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noe : out std_logic;
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ng : out std_logic
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);
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constant DIV_WIDTH : integer := 3;
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end AppleIISd;
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architecture Behavioral of AppleIISd is
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-- interface signals
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signal selected: std_logic;
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signal reset: std_logic;
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signal int_out: std_logic;
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signal is_read: std_logic;
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signal int_din: std_logic_vector (7 downto 0);
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signal int_dout: std_logic_vector (7 downto 0);
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signal int_mosi: std_logic;
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signal int_miso: std_logic;
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signal int_sclk: std_logic;
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--------------------------
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-- internal state
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signal spidatain: std_logic_vector (7 downto 0);
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signal spidataout: std_logic_vector (7 downto 0);
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signal spiint: std_logic; -- spi interrupt state
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-- interface signals
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signal selected: std_logic;
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signal reset: std_logic;
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signal int_out: std_logic;
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signal is_read: std_logic;
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signal int_din: std_logic_vector (7 downto 0);
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signal int_dout: std_logic_vector (7 downto 0);
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signal int_mosi: std_logic;
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signal int_miso: std_logic;
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signal int_sclk: std_logic;
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--------------------------
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-- internal state
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signal spidatain: std_logic_vector (7 downto 0);
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signal spidataout: std_logic_vector (7 downto 0);
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signal spiint: std_logic; -- spi interrupt state
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signal inited: std_logic; -- card initialized
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signal inited_int: std_logic;
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-- spi register flags
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signal tc: std_logic; -- transmission complete; cleared on spi data read
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signal ier: std_logic; -- enable general SPI interrupts
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signal bsy: std_logic; -- SPI busy
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signal frx: std_logic; -- fast receive mode
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signal tmo: std_logic; -- tri-state mosi
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signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
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signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
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signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
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signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
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signal slavesel: std_logic; -- slave select output (0=selected)
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signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
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--------------------------
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-- helper signals
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-- spi register flags
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signal tc: std_logic; -- transmission complete; cleared on spi data read
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signal ier: std_logic; -- enable general SPI interrupts
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signal bsy: std_logic; -- SPI busy
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signal frx: std_logic; -- fast receive mode
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signal tmo: std_logic; -- tri-state mosi
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signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
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signal cpol: std_logic; -- shift clock polarity; 0=rising edge, 1=falling edge
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signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
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signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
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signal slavesel: std_logic; -- slave select output (0=selected)
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signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
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--------------------------
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-- helper signals
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-- shift engine
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signal start_shifting: std_logic; -- shifting data
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signal shifting2: std_logic; -- shifting data
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signal shiftdone: std_logic; -- shifting data done
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signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
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-- spi clock
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signal clksrc: std_logic; -- clock source (phi2 or extclk)
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signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
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signal shiftclk : std_logic;
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-- shift engine
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signal start_shifting: std_logic; -- shifting data
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signal shifting2: std_logic; -- shifting data
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signal shiftdone: std_logic; -- shifting data done
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signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
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-- spi clock
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signal clksrc: std_logic; -- clock source (phi2 or extclk)
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-- TODO divcnt is not used at all??
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signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
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signal shiftclk : std_logic;
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component AddressDecoder
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port ( A8 : in std_logic;
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A9 : in std_logic;
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A10 : in std_logic;
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CLK : in std_logic;
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NDEV_SEL : in std_logic;
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NIO_SEL : in std_logic;
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NIO_STB : in std_logic;
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B8 : out std_logic;
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B9 : out std_logic;
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B10 : out std_logic;
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NOE : out std_logic);
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end component;
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component AddressDecoder
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port (
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A8 : in std_logic;
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A9 : in std_logic;
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A10 : in std_logic;
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CLK : in std_logic;
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NDEV_SEL : in std_logic;
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NIO_SEL : in std_logic;
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NIO_STB : in std_logic;
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B8 : out std_logic;
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B9 : out std_logic;
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B10 : out std_logic;
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NOE : out std_logic
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);
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end component;
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begin
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add_dec : AddressDecoder
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port map (A8=>a8,
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A9=>a9,
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A10=>a10,
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CLK=>extclk,
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NDEV_SEL=>ndev_sel,
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NIO_SEL=>nio_sel,
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NIO_STB=>nio_stb,
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B8=>b8,
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B9=>b9,
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B10=>b10,
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NOE=>noe);
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add_dec : AddressDecoder
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port map (
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A8=>a8,
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A9=>a9,
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A10=>a10,
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CLK=>extclk,
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NDEV_SEL=>ndev_sel,
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NIO_SEL=>nio_sel,
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NIO_STB=>nio_stb,
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B8=>b8,
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B9=>b9,
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B10=>b10,
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NOE=>noe
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);
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led <= not (bsy or not slavesel); --'0'; --shifting2; --shiftdone; --shiftcnt(2);
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ng <= ndev_sel and nio_sel and nio_stb;
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led <= not (bsy or not slavesel);
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ng <= ndev_sel and nio_sel and nio_stb;
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inited <= inited_int and not card;
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--------------------------
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bsy <= start_shifting or shifting2;
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process(start_shifting, shiftdone, shiftclk)
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begin
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if (rising_edge(shiftclk)) then
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if (shiftdone = '1') then
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shifting2 <= '0';
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else
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shifting2 <= start_shifting;
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end if;
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end if;
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end process;
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bsy <= start_shifting or shifting2;
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process(start_shifting, shiftdone, shiftclk)
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begin
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if (rising_edge(shiftclk)) then
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if (shiftdone = '1') then
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shifting2 <= '0';
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else
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shifting2 <= start_shifting;
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end if;
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end if;
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end process;
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process(shiftcnt, reset, shiftclk)
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begin
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if (reset = '1') then
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shiftdone <= '0';
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elsif (rising_edge(shiftclk)) then
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if (shiftcnt = "1111") then
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shiftdone <= '1';
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else
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shiftdone <= '0';
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end if;
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end if;
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end process;
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process(reset, shifting2, shiftcnt, shiftclk)
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begin
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if (reset='1') then
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shiftcnt <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1') then
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-- count phase
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shiftcnt <= shiftcnt + 1;
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else
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shiftcnt <= (others => '0');
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end if;
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end if;
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end process;
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process(shiftcnt, reset, shiftclk)
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begin
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if (reset = '1') then
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shiftdone <= '0';
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elsif (rising_edge(shiftclk)) then
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if (shiftcnt = "1111") then
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shiftdone <= '1';
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else
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shiftdone <= '0';
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end if;
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end if;
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end process;
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process(reset, shifting2, shiftcnt, shiftclk)
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begin
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if (reset='1') then
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shiftcnt <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1') then
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-- count phase
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shiftcnt <= shiftcnt + 1;
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else
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shiftcnt <= (others => '0');
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end if;
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end if;
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end process;
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inproc: process(reset, shifting2,
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shiftcnt, shiftclk, spidatain, int_miso)
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begin
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if (reset='1') then
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spidatain <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1' and shiftcnt(0) = '1') then
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-- shift in to input register
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spidatain (7 downto 1) <= spidatain (6 downto 0);
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spidatain (0) <= int_miso;
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end if;
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end if;
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end process;
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inproc: process(reset, shifting2, shiftcnt, shiftclk, spidatain, int_miso)
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begin
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if (reset='1') then
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spidatain <= (others => '0');
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elsif (rising_edge(shiftclk)) then
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if (shifting2 = '1' and shiftcnt(0) = '1') then
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-- shift in to input register
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spidatain (7 downto 1) <= spidatain (6 downto 0);
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spidatain (0) <= int_miso;
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end if;
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end if;
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end process;
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outproc: process(reset, shifting2, spidataout, cpol, cpha,
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shiftcnt, shiftclk)
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begin
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if (reset='1') then
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int_mosi <= '1';
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int_sclk <= cpol;
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else
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-- clock is sync'd
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if (rising_edge(shiftclk)) then
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if (shifting2='0' or shiftdone = '1') then
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int_mosi <= '1';
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int_sclk <= cpol;
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else
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-- output data directly from output register
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case shiftcnt(3 downto 1) is
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when "000" => int_mosi <= spidataout(7);
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when "001" => int_mosi <= spidataout(6);
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when "010" => int_mosi <= spidataout(5);
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when "011" => int_mosi <= spidataout(4);
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when "100" => int_mosi <= spidataout(3);
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when "101" => int_mosi <= spidataout(2);
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when "110" => int_mosi <= spidataout(1);
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when "111" => int_mosi <= spidataout(0);
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outproc: process(reset, shifting2, spidataout, cpol, cpha, shiftcnt, shiftclk)
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begin
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if (reset='1') then
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int_mosi <= '1';
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int_sclk <= cpol;
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else
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-- clock is sync'd
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if (rising_edge(shiftclk)) then
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if (shifting2='0' or shiftdone = '1') then
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int_mosi <= '1';
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int_sclk <= cpol;
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else
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-- output data directly from output register
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case shiftcnt(3 downto 1) is
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when "000" => int_mosi <= spidataout(7);
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when "001" => int_mosi <= spidataout(6);
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when "010" => int_mosi <= spidataout(5);
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when "011" => int_mosi <= spidataout(4);
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when "100" => int_mosi <= spidataout(3);
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when "101" => int_mosi <= spidataout(2);
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when "110" => int_mosi <= spidataout(1);
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when "111" => int_mosi <= spidataout(0);
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when others => int_mosi <= '1';
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end case;
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int_sclk <= cpol xor cpha xor shiftcnt(0);
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end if;
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end if;
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end if;
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end process;
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end case;
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int_sclk <= cpol xor cpha xor shiftcnt(0);
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end if;
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end if;
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end if;
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end process;
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-- shift operation enable
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shiften: process(reset, selected, nrw, addr, frx, shiftdone)
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begin
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-- start shifting
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if (reset='1' or shiftdone='1') then
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start_shifting <= '0';
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elsif (falling_edge(selected) and addr="00" and (frx='1' or nrw='0')) then
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-- access to register 00, either write (nrw=0) or fast receive bit set (frx)
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-- then both types of access (write but also read)
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start_shifting <= '1';
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end if;
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end process;
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-- shift operation enable
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shiften: process(reset, selected, nrw, addr, frx, shiftdone)
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begin
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-- start shifting
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if (reset='1' or shiftdone='1') then
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start_shifting <= '0';
|
||||
elsif (falling_edge(selected) and addr="00" and (frx='1' or nrw='0')) then
|
||||
-- access to register 00, either write (nrw=0) or fast receive bit set (frx)
|
||||
-- then both types of access (write but also read)
|
||||
start_shifting <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- spiclk - spi clock generation
|
||||
-- spiclk is still 2 times the freq. than sclk
|
||||
clksrc <= nphi2 when (ece = '0') else extclk;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
--shiftclk <= clksrc when divcnt = "000000" else '0';
|
||||
shiftclk <= clksrc when bsy = '1' else '0';
|
||||
|
||||
clkgen: process(reset, divisor, clksrc)
|
||||
begin
|
||||
if (reset='1') then
|
||||
divcnt <= divisor;
|
||||
--spiclk <= '0';
|
||||
elsif (falling_edge(clksrc)) then
|
||||
if (shiftclk = '1') then
|
||||
divcnt <= divisor;
|
||||
--spiclk <= not(spiclk);
|
||||
else
|
||||
divcnt <= divcnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- interrupt generation
|
||||
int_out <= spiint and slaveinten;
|
||||
--------------------------
|
||||
-- spiclk - spi clock generation
|
||||
-- spiclk is still 2 times the freq. than sclk
|
||||
clksrc <= nphi2 when (ece = '0') else extclk;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
--shiftclk <= clksrc when divcnt = "000000" else '0';
|
||||
shiftclk <= clksrc when bsy = '1' else '0';
|
||||
|
||||
clkgen: process(reset, divisor, clksrc)
|
||||
begin
|
||||
if (reset='1') then
|
||||
divcnt <= divisor;
|
||||
elsif (falling_edge(clksrc)) then
|
||||
if (shiftclk = '1') then
|
||||
divcnt <= divisor;
|
||||
else
|
||||
divcnt <= divcnt - 1;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- interrupt generation
|
||||
int_out <= spiint and slaveinten;
|
||||
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
reset <= not (nreset);
|
||||
selected <= not(ndev_sel); -- and cpu_phi2;
|
||||
is_read <= selected and nphi2 and nrw;
|
||||
int_din <= data;
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
reset <= not (nreset);
|
||||
selected <= not(ndev_sel);
|
||||
is_read <= selected and nphi2 and nrw;
|
||||
int_din <= data;
|
||||
|
||||
int_miso <= (spi_miso and not slavesel);
|
||||
|
||||
-- outputs
|
||||
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
|
||||
nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
|
||||
spi_sclk <= int_sclk;
|
||||
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
|
||||
spi_Nsel <= slavesel;
|
||||
|
||||
tc_proc: process (selected, shiftdone)
|
||||
begin
|
||||
if (shiftdone = '1') then
|
||||
tc <= '1';
|
||||
elsif (falling_edge(selected) and addr="00"
|
||||
--elsif (falling_edge(cpu_phi2) and selected='1' and addr="00"
|
||||
--and nrw='1' -- both reads _and_ writes clear the interrupt
|
||||
) then
|
||||
int_miso <= (spi_miso and not slavesel);
|
||||
|
||||
-- outputs
|
||||
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
|
||||
nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
|
||||
spi_sclk <= int_sclk;
|
||||
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
|
||||
spi_Nsel <= slavesel;
|
||||
|
||||
tc_proc: process (selected, shiftdone)
|
||||
begin
|
||||
if (shiftdone = '1') then
|
||||
tc <= '1';
|
||||
elsif (falling_edge(selected) and addr="00") then
|
||||
tc <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
spiint <= tc and ier;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
spiint <= tc and ier;
|
||||
|
||||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process (is_read, addr,
|
||||
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
|
||||
slavesel, slaveinten, wp, card, inited)
|
||||
begin
|
||||
if (is_read = '1') then
|
||||
case addr is
|
||||
when "00" => -- read SPI data in
|
||||
int_dout <= spidatain;
|
||||
when "01" => -- read status register
|
||||
int_dout(0) <= cpha;
|
||||
int_dout(1) <= cpol;
|
||||
int_dout(2) <= ece;
|
||||
int_dout(3) <= tmo;
|
||||
int_dout(4) <= frx;
|
||||
int_dout(5) <= bsy;
|
||||
int_dout(6) <= ier;
|
||||
int_dout(7) <= tc;
|
||||
when "10" => -- read sclk divisor
|
||||
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
|
||||
int_dout(7 downto 3) <= (others => '0');
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
int_dout(0) <= slavesel;
|
||||
int_dout(3 downto 1) <= (others => '0');
|
||||
int_dout(4) <= slaveinten;
|
||||
int_dout(5) <= wp;
|
||||
int_dout(6) <= card;
|
||||
int_dout(7) <= inited;
|
||||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process (is_read, addr,
|
||||
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
|
||||
slavesel, slaveinten, wp, card, inited)
|
||||
begin
|
||||
if (is_read = '1') then
|
||||
case addr is
|
||||
when "00" => -- read SPI data in
|
||||
int_dout <= spidatain;
|
||||
when "01" => -- read status register
|
||||
int_dout(0) <= cpha;
|
||||
int_dout(1) <= cpol;
|
||||
int_dout(2) <= ece;
|
||||
int_dout(3) <= tmo;
|
||||
int_dout(4) <= frx;
|
||||
int_dout(5) <= bsy;
|
||||
int_dout(6) <= ier;
|
||||
int_dout(7) <= tc;
|
||||
when "10" => -- read sclk divisor
|
||||
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
|
||||
int_dout(7 downto 3) <= (others => '0');
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
int_dout(0) <= slavesel;
|
||||
int_dout(3 downto 1) <= (others => '0');
|
||||
int_dout(4) <= slaveinten;
|
||||
int_dout(5) <= wp;
|
||||
int_dout(6) <= card;
|
||||
int_dout(7) <= inited;
|
||||
when others =>
|
||||
int_dout <= (others => '0');
|
||||
end case;
|
||||
else
|
||||
int_dout <= (others => '0');
|
||||
end if;
|
||||
end process;
|
||||
end case;
|
||||
else
|
||||
int_dout <= (others => '0');
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- cpu write
|
||||
cpu_write: process(reset, selected, nrw, addr, int_din, inited)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
cpha <= '0';
|
||||
cpol <= '0';
|
||||
ece <= '0';
|
||||
tmo <= '0';
|
||||
frx <= '0';
|
||||
ier <= '0';
|
||||
slavesel <= '1';
|
||||
slaveinten <= '0';
|
||||
-- cpu write
|
||||
cpu_write: process(reset, selected, nrw, addr, int_din, inited)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
cpha <= '0';
|
||||
cpol <= '0';
|
||||
ece <= '0';
|
||||
tmo <= '0';
|
||||
frx <= '0';
|
||||
ier <= '0';
|
||||
slavesel <= '1';
|
||||
slaveinten <= '0';
|
||||
inited_int <= '0';
|
||||
divisor <= (others => '0');
|
||||
elsif (falling_edge(selected) and nrw = '0') then
|
||||
--elsif (falling_edge(cpu_phi2) and selected='1' and nrw='0') then
|
||||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
spidataout <= int_din;
|
||||
when "01" => -- write status register
|
||||
cpha <= int_din(0);
|
||||
cpol <= int_din(1);
|
||||
ece <= int_din(2);
|
||||
tmo <= int_din(3);
|
||||
frx <= int_din(4);
|
||||
-- no bit 5
|
||||
ier <= int_din(6);
|
||||
-- no bit 7;
|
||||
when "10" => -- write divisor
|
||||
divisor <= int_din(DIV_WIDTH-1 downto 0);
|
||||
when "11" => -- write slave select / slave interrupt enable
|
||||
slavesel <= int_din(0);
|
||||
slaveinten <= int_din(4);
|
||||
divisor <= (others => '0');
|
||||
spidataout <= (others => '1');
|
||||
elsif (falling_edge(selected) and nrw = '0') then
|
||||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
spidataout <= int_din;
|
||||
when "01" => -- write status register
|
||||
cpha <= int_din(0);
|
||||
cpol <= int_din(1);
|
||||
ece <= int_din(2);
|
||||
tmo <= int_din(3);
|
||||
frx <= int_din(4);
|
||||
-- no bit 5
|
||||
ier <= int_din(6);
|
||||
-- no bit 7;
|
||||
when "10" => -- write divisor
|
||||
divisor <= int_din(DIV_WIDTH-1 downto 0);
|
||||
when "11" => -- write slave select / slave interrupt enable
|
||||
slavesel <= int_din(0);
|
||||
slaveinten <= int_din(4);
|
||||
inited_int <= int_din(7);
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user