diff --git a/VHDL/AddressDecoder.sch b/VHDL/AddressDecoder.sch
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diff --git a/VHDL/AddressDecoder.schlog b/VHDL/AddressDecoder.schlog
deleted file mode 100644
index e69de29..0000000
diff --git a/VHDL/AddressDecoder.vhd b/VHDL/AddressDecoder.vhd
new file mode 100644
index 0000000..9418c3e
--- /dev/null
+++ b/VHDL/AddressDecoder.vhd
@@ -0,0 +1,71 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 22:03:22 10/10/2017
+-- Design Name:
+-- Module Name: AddressDecoder - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity AddressDecoder is
+ Port ( A : in std_logic_vector (10 downto 8);
+ B : out std_logic_vector (10 downto 8);
+ RNW : in std_logic;
+ NDEV_SEL : in std_logic;
+ NIO_SEL : in std_logic;
+ NIO_STB : in std_logic;
+ NRESET : in std_logic;
+ DATA_EN : out std_logic;
+ NG : out std_logic;
+ NOE : out std_logic);
+end AddressDecoder;
+
+architecture Behavioral of AddressDecoder is
+
+ signal cfxx : std_logic;
+ signal noe_int : std_logic;
+ signal ncs : std_logic;
+
+begin
+
+ B <= A when (NIO_STB = '0') else (others => '0');
+ DATA_EN <= RNW and not NDEV_SEL;
+ NG <= NDEV_SEL and noe_int;
+ NOE <= noe_int;
+ noe_int <= not RNW or not NDEV_SEL or NIO_STB or ncs;
+
+ cfxx <= A(8) and A(9) and A(10) and not NIO_STB;
+
+ process(NRESET, NIO_SEL, cfxx)
+ begin
+ if (NRESET = '0' or cfxx = '1') then
+ ncs <= '1';
+ elsif falling_edge(NIO_SEL) then
+ ncs <= '0';
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/VHDL/AppleIISd.ucf b/VHDL/AppleIISd.ucf
index e3e2602..4696b8c 100644
--- a/VHDL/AppleIISd.ucf
+++ b/VHDL/AppleIISd.ucf
@@ -8,9 +8,9 @@ NET "ADD_HIGH<8>" LOC = "P36" ;
NET "ADD_HIGH<9>" LOC = "P37" ;
NET "ADD_LOW<0>" LOC = "P19" ;
NET "ADD_LOW<1>" LOC = "P18" ;
-NET "B10" LOC = "P22" ;
-NET "B8" LOC = "P26" ;
-NET "B9" LOC = "P27" ;
+NET "B<10>" LOC = "P22" ;
+NET "B<8>" LOC = "P26" ;
+NET "B<9>" LOC = "P27" ;
NET "CARD" LOC = "P33" ;
NET "DATA<0>" LOC = "P3" ;
NET "DATA<1>" LOC = "P4" ;
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index dacfaaa..73b666e 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -19,10 +19,6 @@
-
-
-
-
@@ -34,6 +30,10 @@
+
+
+
+
diff --git a/VHDL/IO.vhd b/VHDL/IO.vhd
index dc7f783..30e87fa 100644
--- a/VHDL/IO.vhd
+++ b/VHDL/IO.vhd
@@ -33,9 +33,7 @@ entity IO is
Port (
ADD_HIGH : in std_logic_vector(10 downto 8);
ADD_LOW : in std_logic_vector(1 downto 0);
- B10 : out std_logic;
- B9 : out std_logic;
- B8 : out std_logic;
+ B : out std_logic_vector(10 downto 8);
CARD : in std_logic;
DATA : inout std_logic_vector (7 downto 0);
CLK : in std_logic;
@@ -97,22 +95,19 @@ Port (
end component;
component AddressDecoder
- port (
- A8 : in std_logic;
- A9 : in std_logic;
- A10 : in std_logic;
- NDEV_SEL : in std_logic;
- NIO_SEL : in std_logic;
- NIO_STB : in std_logic;
- RNW : in std_logic;
- B8 : out std_logic;
- B9 : out std_logic;
- B10 : out std_logic;
- NOE : out std_logic;
- NG : out std_logic;
- DATA_EN : out std_logic
- );
- end component;
+Port (
+ A : in std_logic_vector (10 downto 8);
+ B : out std_logic_vector (10 downto 8);
+ RNW : in std_logic;
+ NDEV_SEL : in std_logic;
+ NIO_SEL : in std_logic;
+ NIO_STB : in std_logic;
+ NRESET : in std_logic;
+ DATA_EN : out std_logic;
+ NG : out std_logic;
+ NOE : out std_logic
+ );
+end component;
begin
spi: AppleIISd port map(
@@ -134,19 +129,16 @@ begin
);
addDec: AddressDecoder port map(
- A8 => ADD_HIGH(8),
- A9 => ADD_HIGH(9),
- A10 => ADD_HIGH(10),
+ A => ADD_HIGH,
+ B => B,
+ RNW => RNW,
NDEV_SEL => NDEV_SEL,
NIO_SEL => NIO_SEL,
NIO_STB => NIO_STB,
- RNW => RNW,
- B8 => B8,
- B9 => B9,
- B10 => B10,
+ NRESET => NRESET,
+ DATA_EN => data_en,
NOE => NOE,
- NG => NG,
- DATA_EN => data_en
+ NG => NG
);
ctrl_latch: process(CLK, NRESET)
diff --git a/VHDL/IO_Test.vhd b/VHDL/IO_Test.vhd
index 1ceb33a..8657f51 100644
--- a/VHDL/IO_Test.vhd
+++ b/VHDL/IO_Test.vhd
@@ -43,9 +43,7 @@ ARCHITECTURE behavior OF IO_Test IS
PORT(
ADD_HIGH : IN std_logic_vector(10 downto 8);
ADD_LOW : IN std_logic_vector(1 downto 0);
- B10 : OUT std_logic;
- B9 : OUT std_logic;
- B8 : OUT std_logic;
+ B : OUT std_logic_vector(10 downto 8);
CARD : IN std_logic;
DATA : INOUT std_logic_vector(7 downto 0);
CLK : IN std_logic;
@@ -88,9 +86,7 @@ ARCHITECTURE behavior OF IO_Test IS
signal DATA : std_logic_vector(7 downto 0) := (others => 'Z');
--Outputs
- signal B10 : std_logic;
- signal B9 : std_logic;
- signal B8 : std_logic;
+ signal B : std_logic_vector(10 downto 8);
signal LED : std_logic;
signal NG : std_logic;
signal NOE : std_logic;
@@ -120,9 +116,7 @@ BEGIN
uut: IO PORT MAP (
ADD_HIGH => ADD_HIGH,
ADD_LOW => ADD_LOW,
- B10 => B10,
- B9 => B9,
- B8 => B8,
+ B => B,
CARD => CARD,
DATA => DATA,
CLK => CLK,