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Fix in VQ44 pinning

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This commit is contained in:
Florian Reitz 2019-06-02 19:28:51 +02:00
parent 26909735ae
commit 93cd52b99c
7 changed files with 1110 additions and 1130 deletions
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4
.gitignore vendored
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@ -215,3 +215,7 @@ Hardware/SD_A2\.b\$1
VHDL/_pace\.ucf VHDL/_pace\.ucf
VHDL/AppleIISd\.tim
VHDL/AppleIISd\.jed

1046
VHDL/AppleIISd_PC44.jed → AppleIISd_PC44.jed
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1074
VHDL/AppleIISd_VQ44.jed → AppleIISd_VQ44.jed
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BIN
VHDL/AppleIISd.ipf
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68
VHDL/AppleIISd_VQ44.ucf Normal file → Executable file
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@ -1,40 +1,40 @@
#PACE: Start of Constraints generated by PACE #PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments #PACE: Start of PACE I/O Pin Assignments
NET "ADD_HIGH<10>" LOC = "P32" ; NET "ADD_HIGH<10>" LOC = "P32" ;
NET "ADD_HIGH<11>" LOC = "P38" ; NET "ADD_HIGH<11>" LOC = "P38" ;
NET "ADD_HIGH<8>" LOC = "P30" ; NET "ADD_HIGH<8>" LOC = "P30" ;
NET "ADD_HIGH<9>" LOC = "P31" ; NET "ADD_HIGH<9>" LOC = "P31" ;
NET "ADD_LOW<0>" LOC = "P12" ; NET "ADD_LOW<0>" LOC = "P13" ;
NET "ADD_LOW<1>" LOC = "P13" ; NET "ADD_LOW<1>" LOC = "P12" ;
NET "B<10>" LOC = "P16" ; NET "B<10>" LOC = "P16" ;
NET "B<8>" LOC = "P20" ; NET "B<8>" LOC = "P20" ;
NET "B<9>" LOC = "P21" ; NET "B<9>" LOC = "P21" ;
NET "CARD" LOC = "P27" ; NET "CARD" LOC = "P27" ;
NET "CLK" LOC = "P37" ; NET "CLK" LOC = "P37" ;
NET "DATA<0>" LOC = "P41" ; NET "DATA<0>" LOC = "P41" ;
NET "DATA<1>" LOC = "P42" ; NET "DATA<1>" LOC = "P42" ;
NET "DATA<2>" LOC = "P43" ; NET "DATA<2>" LOC = "P43" ;
NET "DATA<3>" LOC = "P44" ; NET "DATA<3>" LOC = "P44" ;
NET "DATA<4>" LOC = "P1" ; NET "DATA<4>" LOC = "P1" ;
NET "DATA<5>" LOC = "P3" ; NET "DATA<5>" LOC = "P3" ;
NET "DATA<6>" LOC = "P5" ; NET "DATA<6>" LOC = "P5" ;
NET "DATA<7>" LOC = "P7" ; NET "DATA<7>" LOC = "P7" ;
NET "LED" LOC = "P23" ; NET "LED" LOC = "P23" ;
NET "MISO" LOC = "P34" ; NET "MISO" LOC = "P34" ;
NET "MOSI" LOC = "P29" ; NET "MOSI" LOC = "P29" ;
NET "NDEV_SEL" LOC = "P18" ; NET "NDEV_SEL" LOC = "P18" ;
NET "NG" LOC = "P6" ; NET "NG" LOC = "P6" ;
NET "NIO_SEL" LOC = "P8" ; NET "NIO_SEL" LOC = "P8" ;
NET "NIO_STB" LOC = "P36" ; NET "NIO_STB" LOC = "P36" ;
NET "NOE" LOC = "P19" ; NET "NOE" LOC = "P19" ;
NET "NRESET" LOC = "P14" ; NET "NRESET" LOC = "P14" ;
NET "NSEL" LOC = "P22" ; NET "NSEL" LOC = "P22" ;
NET "NWE" LOC = "P40" ; NET "NWE" LOC = "P40" ;
NET "PHI0" LOC = "P2" ; NET "PHI0" LOC = "P2" ;
NET "RNW" LOC = "P39" ; NET "RNW" LOC = "P39" ;
NET "SCLK" LOC = "P28" ; NET "SCLK" LOC = "P28" ;
NET "WP" LOC = "P33" ; NET "WP" LOC = "P33" ;
#PACE: Start of PACE Area Constraints #PACE: Start of PACE Area Constraints

12
VHDL/AppleIISd_VQ44.xise Normal file → Executable file
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@ -105,7 +105,7 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logic Optimization" xil_pn:value="Speed" xil_pn:valueState="default"/> <property xil_pn:name="Logic Optimization" xil_pn:value="Density" xil_pn:valueState="non-default"/>
<property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Macro Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/> <property xil_pn:name="Macrocell Power Setting" xil_pn:value="Std" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
@ -114,7 +114,7 @@
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Goal" xil_pn:value="Area" xil_pn:valueState="non-default"/>
<property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other CPLD Fitter Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
@ -177,9 +177,9 @@
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Waveform Configuration File Fit" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Use FSM Explorer Data" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Clocks" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Global Clocks" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Output Enables" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Global Output Enables" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Global Set/Reset" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Global Set/Reset" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/> <property xil_pn:name="Use Location Constraints" xil_pn:value="Always" xil_pn:valueState="default"/>
<property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Multi-level Logic Optimization" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
@ -194,7 +194,7 @@
<property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/> <property xil_pn:name="WYSIWYG" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="XOR Preserve" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd.ipf" xil_pn:valueState="non-default"/> <property xil_pn:name="iMPACT Project File" xil_pn:value="AppleIISd_VQ44.ipf" xil_pn:valueState="non-default"/>
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->

36
VHDL/SpiController.vhd Normal file → Executable file
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@ -28,9 +28,6 @@ Port (
pgm_en : out STD_LOGIC; pgm_en : out STD_LOGIC;
led : out STD_LOGIC led : out STD_LOGIC
); );
constant DIV_WIDTH : integer := 3;
end SpiController; end SpiController;
architecture Behavioral of SpiController is architecture Behavioral of SpiController is
@ -49,7 +46,6 @@ architecture Behavioral of SpiController is
signal frx: std_logic; -- fast receive mode signal frx: std_logic; -- fast receive mode
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
signal slavesel: std_logic := '1'; -- slave select output (0=selected) signal slavesel: std_logic := '1'; -- slave select output (0=selected)
signal int_miso: std_logic; signal int_miso: std_logic;
-------------------------- --------------------------
@ -63,8 +59,6 @@ architecture Behavioral of SpiController is
-- spi clock -- spi clock
signal clksrc: std_logic; -- clock source (phi2 or clk_7m) signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
-- TODO divcnt is not used at all??
--signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
signal shiftclk : std_logic; signal shiftclk : std_logic;
begin begin
@ -172,22 +166,8 @@ begin
clksrc <= phi0 when (ece = '0') else clk; clksrc <= phi0 when (ece = '0') else clk;
-- is a pulse signal to allow for divisor==0 -- is a pulse signal to allow for divisor==0
--shiftclk <= clksrc when divcnt = "000000" else '0';
shiftclk <= clksrc when bsy = '1' else '0'; shiftclk <= clksrc when bsy = '1' else '0';
-- clkgen: process(nreset, divisor, clksrc)
-- begin
-- if (nreset = '0') then
-- divcnt <= divisor;
-- elsif (falling_edge(clksrc)) then
-- if (shiftclk = '1') then
-- divcnt <= divisor;
-- else
-- divcnt <= divcnt - 1;
-- end if;
-- end if;
-- end process;
-------------------------- --------------------------
-- interface section -- interface section
-- inputs -- inputs
@ -210,7 +190,7 @@ begin
-- cpu register section -- cpu register section
-- cpu read -- cpu read
cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen, cpu_read: process(addr, spidatain, tc, bsy, frx, pgmen,
ece, divisor, slavesel, wp, card, sdhc, inited) ece, slavesel, wp, card, sdhc, inited)
begin begin
case addr is case addr is
when "00" => -- read SPI data in when "00" => -- read SPI data in
@ -223,10 +203,8 @@ begin
data_out(4) <= frx; data_out(4) <= frx;
data_out(5) <= bsy; data_out(5) <= bsy;
data_out(6) <= '0'; data_out(6) <= '0';
data_out(7) <= tc; data_out(7) <= tc;
when "10" => -- read sclk divisor -- no register 2
data_out(DIV_WIDTH-1 downto 0) <= divisor;
data_out(7 downto 3) <= (others => '0');
when "11" => -- read slave select / slave interrupt state when "11" => -- read slave select / slave interrupt state
data_out(0) <= slavesel; data_out(0) <= slavesel;
data_out(3 downto 1) <= (others => '0'); data_out(3 downto 1) <= (others => '0');
@ -246,7 +224,6 @@ begin
ece <= '0'; ece <= '0';
frx <= '0'; frx <= '0';
slavesel <= '1'; slavesel <= '1';
divisor <= (others => '0');
spidataout <= (others => '1'); spidataout <= (others => '1');
sdhc <= '0'; sdhc <= '0';
inited <= '0'; inited <= '0';
@ -262,10 +239,9 @@ begin
pgmen <= data_in(0); pgmen <= data_in(0);
ece <= data_in(2); ece <= data_in(2);
frx <= data_in(4); frx <= data_in(4);
-- no bit 5 - 7 -- no bit 5 - 7
when "10" => -- write divisor -- no register 2
divisor <= data_in(DIV_WIDTH-1 downto 0); when "11" => -- write slave select
when "11" => -- write slave select / slave interrupt enable
slavesel <= data_in(0); slavesel <= data_in(0);
-- no bit 1 - 3 -- no bit 1 - 3
sdhc <= data_in(4); sdhc <= data_in(4);