SPI Mode 3

This commit is contained in:
freitz85 2017-11-01 16:50:56 +01:00
parent e9bd383d2e
commit 9aa65960c4
2 changed files with 41 additions and 66 deletions

View File

@ -1,5 +1,5 @@
Programmer Jedec Bit Map
Date Extracted: Mon Oct 23 22:04:22 2017
Date Extracted: Wed Nov 01 14:24:37 2017
QF46656*
QP44*
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@ -335,7 +335,7 @@ L0008304 00000011 00000001 00000010 00000010*
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@ -473,14 +473,14 @@ L0012288 00000000 10000000 00000000 00000000*
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CBE32*
1DE8
CBEB2*
1DF8

View File

@ -1,32 +1,7 @@
----------------------------------------------------------------------------------
-- Company: n/a
-- Engineer: A. Fachat
--
-- Create Date: 12:37:11 05/07/2011
-- Design Name: SPI65B
-- Module Name: SPI6502B - Behavioral
-- Project Name: CS/A NETUSB 2.0
-- Target Devices: CS/A NETUSB 2.0
-- Tool versions:
-- Description: An SPI interface for 6502-based computers (or compatible).
-- modelled after the SPI65 interface by Daryl Rictor
-- (see http://sbc.rictor.org/io/65spi.html )
-- This implementation here, however, is a complete reimplementation
-- as the ABEL language of the original implementation is not supported
-- by ISE anymore.
-- Also I added the interrupt input handling, replacing four of the
-- original SPI select outputs with four interrupt inputs
-- Also folded out the single MISO input into one input for each of the
-- four supported devices, reducing external parts count again by one.
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - removed spiclk and replaced with clksrc and clkcnt_is_zero combination,
-- to drive up SPI clock to half of input clock (and not one fourth only as before)
-- unfortunately that costed one divisor bit to fit into the CPLD
-- Additional Comments:
-- Spi controller for 6502 systems
-- based on a design by A. Fachat
--
----------------------------------------------------------------------------------
library IEEE;
@ -149,13 +124,13 @@ begin
begin
if (nreset = '0') then
mosi <= '1';
sclk <= '0';
sclk <= '1';
else
-- clock is sync'd
if (rising_edge(shiftclk)) then
if (shifting2='0' or shiftdone = '1') then
mosi <= '1';
sclk <= '0';
sclk <= '1';
else
-- output data directly from output register
case shiftcnt(3 downto 1) is
@ -169,7 +144,7 @@ begin
when "111" => mosi <= spidataout(0);
when others => mosi <= '1';
end case;
sclk <= '0' xor '0' xor shiftcnt(0);
sclk <= shiftcnt(0);
end if;
end if;
end if;