From 9c3b1c33fffd7686ac7fd037e428882348770c1c Mon Sep 17 00:00:00 2001
From: freitz85 <freitz85@gmail.com>
Date: Sun, 10 Sep 2017 14:07:23 +0200
Subject: [PATCH] Reset inited on card remove

---
 .gitignore           |    6 +
 VHDL/AppleIISd.jed   | 1667 ++++++++++++++++++++++++++++++++++++++++++
 VHDL/AppleIISd.tspec |  829 ---------------------
 VHDL/AppleIISd.vhd   |  158 ++--
 VHDL/AppleIISd.xise  |    9 +-
 VHDL/sr_latch.vhd    |   55 ++
 6 files changed, 1829 insertions(+), 895 deletions(-)
 create mode 100644 VHDL/AppleIISd.jed
 delete mode 100644 VHDL/AppleIISd.tspec
 create mode 100644 VHDL/sr_latch.vhd

diff --git a/.gitignore b/.gitignore
index 3ff132f..cb249ad 100644
--- a/.gitignore
+++ b/.gitignore
@@ -171,3 +171,9 @@ VHDL/*.lfp
 
 Hardware/SD_A2\.b\$1
 
+
+*.vf
+
+*.nga
+
+*.tspec
diff --git a/VHDL/AppleIISd.jed b/VHDL/AppleIISd.jed
new file mode 100644
index 0000000..234df97
--- /dev/null
+++ b/VHDL/AppleIISd.jed
@@ -0,0 +1,1667 @@
+Programmer Jedec Bit Map
+Date Extracted: Sun Sep 10 14:02:45 2017
+
+QF46656*
+QP44*
+QV0*
+F0*
+X0*
+J0 0*
+N VERSION P.20131013*
+N DEVICE XC9572XL-10-PC44*
+N PPMAP 11 1*
+N PPMAP 29 11*
+N PPMAP 31 12*
+N PPMAP 33 13*
+N PPMAP 38 14*
+N PPMAP 46 18*
+N PPMAP 49 19*
+N PPMAP 12 2*
+N PPMAP 50 20*
+N PPMAP 52 22*
+N PPMAP 59 24*
+N PPMAP 62 25*
+N PPMAP 63 26*
+N PPMAP 65 27*
+N PPMAP 68 28*
+N PPMAP 72 29*
+N PPMAP 13 3*
+N PPMAP 82 33*
+N PPMAP 83 34*
+N PPMAP 87 35*
+N PPMAP 88 36*
+N PPMAP 89 37*
+N PPMAP 90 38*
+N PPMAP 92 39*
+N PPMAP 15 4*
+N PPMAP 3 40*
+N PPMAP 7 42*
+N PPMAP 9 43*
+N PPMAP 10 44*
+N PPMAP 20 5*
+N PPMAP 21 6*
+N PPMAP 24 7*
+N PPMAP 26 8*
+N PPMAP 27 9*
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diff --git a/VHDL/AppleIISd.tspec b/VHDL/AppleIISd.tspec
deleted file mode 100644
index a47e6b8..0000000
--- a/VHDL/AppleIISd.tspec
+++ /dev/null
@@ -1,829 +0,0 @@
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-AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<0>:1
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-AUTO_TS_P2P:FROM:addr<1>:TO:data<1>:1
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-AUTO_TS_F2P:FROM:divisor<1>.Q:TO:data<1>:1
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-AUTO_TS_F2P:FROM:start_shifting.Q:TO:data<1>:1
-AUTO_TS_F2P:FROM:ece.Q:TO:data<1>:1
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-AUTO_TS_F2F:FROM:shifting2.Q:TO:spidatain<7>.CE:1
-AUTO_TS_F2F:FROM:ece.Q:TO:spidatain<7>.CE:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:spidatain<7>.CE:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:spidatain<7>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidatain<7>.CE:1
-AUTO_TS_P2F:FROM:extclk:TO:spidatain<7>.CE:1
-AUTO_TS_P2F:FROM:nphi2:TO:spidatain<7>.CE:1
-AUTO_TS_F2F:FROM:cpol.Q:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:shiftdone.Q:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:cpha.Q:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:int_sclk.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.D:1
-AUTO_TS_P2F:FROM:nreset:TO:int_sclk.D:1
-AUTO_TS_P2F:FROM:extclk:TO:int_sclk.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:int_sclk.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:int_sclk.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:int_sclk.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:int_sclk.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:int_sclk.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:int_sclk.CLKF:1
-AUTO_TS_F2F:FROM:cpol.Q:TO:int_sclk.SETF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.SETF:1
-AUTO_TS_P2F:FROM:nreset:TO:int_sclk.SETF:1
-AUTO_TS_F2F:FROM:cpol.Q:TO:int_sclk.RSTF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:int_sclk.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:int_sclk.RSTF:1
-AUTO_TS_F2F:FROM:shiftcnt<3>.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<3>.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<3>.D:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<3>.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<3>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<3>.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<3>.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<3>.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<3>.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<3>.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<3>.CLKF:1
-AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:shiftcnt<2>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<2>.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<2>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftcnt<2>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<2>.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<2>.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<2>.D:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<2>.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<2>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<2>.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<2>.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<2>.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<2>.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<2>.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<2>.CLKF:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<0>.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<0>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<0>.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<0>.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<0>.D:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<0>.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<0>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<0>.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<0>.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<0>.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<0>.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<0>.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<0>.CLKF:1
-AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftcnt<1>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<1>.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<1>.D:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftcnt<1>.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<1>.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<1>.D:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<1>.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<1>.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftcnt<1>.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftcnt<1>.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftcnt<1>.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftcnt<1>.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftcnt<1>.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftcnt<1>.CLKF:1
-AUTO_TS_F2F:FROM:shiftcnt<3>.Q:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:shiftcnt<2>.Q:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:shiftcnt<1>.Q:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:shiftcnt<0>.Q:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftdone.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftdone.D:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftdone.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftdone.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shiftdone.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shiftdone.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shiftdone.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shiftdone.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:shiftdone.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:shiftdone.CLKF:1
-AUTO_TS_F2F:FROM:shiftdone.Q:TO:shifting2.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shifting2.D:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shifting2.D:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shifting2.D:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shifting2.D:1
-AUTO_TS_P2F:FROM:extclk:TO:shifting2.D:1
-AUTO_TS_P2F:FROM:nphi2:TO:shifting2.D:1
-AUTO_TS_F2F:FROM:shifting2.Q:TO:shifting2.CLKF:1
-AUTO_TS_F2F:FROM:ece.Q:TO:shifting2.CLKF:1
-AUTO_TS_F2F:FROM:start_shifting.Q:TO:shifting2.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:shifting2.CLKF:1
-AUTO_TS_P2F:FROM:extclk:TO:shifting2.CLKF:1
-AUTO_TS_P2F:FROM:nphi2:TO:shifting2.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:int_mosi.SETF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:slavesel.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:slavesel.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:slavesel.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:slavesel.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:slavesel.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:cpol.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:cpol.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:cpol.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:cpol.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:cpol.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:ece.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:ece.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:ece.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:ece.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:ece.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:cpha.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:cpha.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:cpha.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:cpha.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:cpha.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:frx.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:frx.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:frx.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:frx.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:frx.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:ier.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:ier.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:ier.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:ier.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:ier.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:slaveinten.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:slaveinten.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:slaveinten.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:slaveinten.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:slaveinten.CE:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<0>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<1>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<2>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<3>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<4>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<5>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<6>.RSTF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:tmo.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:tmo.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:tmo.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:tmo.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:tmo.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<0>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:divisor<0>.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:divisor<0>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:divisor<0>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:divisor<0>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<1>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:divisor<1>.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:divisor<1>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:divisor<1>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:divisor<1>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:divisor<2>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:divisor<2>.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:divisor<2>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:divisor<2>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:divisor<2>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:inited_int.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:inited_int.RSTF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:inited_int.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:inited_int.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:inited_int.CE:1
-AUTO_TS_P2F:FROM:nreset:TO:spidatain<7>.RSTF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<0>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<0>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<0>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<0>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<0>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<1>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<1>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<1>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<1>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<1>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<2>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<2>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<2>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<2>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<2>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<3>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<3>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<3>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<3>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<3>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<4>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<4>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<4>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<4>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<4>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<5>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<5>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<5>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<5>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<5>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<6>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<6>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<6>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<6>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<6>.CE:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:spidataout<7>.CLKF:1
-AUTO_TS_P2F:FROM:nreset:TO:spidataout<7>.SETF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:spidataout<7>.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:spidataout<7>.CE:1
-AUTO_TS_P2F:FROM:nrw:TO:spidataout<7>.CE:1
-AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<3>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<2>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<0>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:shiftcnt<1>.RSTF:1
-AUTO_TS_P2F:FROM:nreset:TO:shiftdone.RSTF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:start_shifting.CLKF:1
-AUTO_TS_P2F:FROM:ndev_sel:TO:tc.CLKF:1
-AUTO_TS_P2F:FROM:addr<1>:TO:tc.CE:1
-AUTO_TS_P2F:FROM:addr<0>:TO:tc.CE:1
-AUTO_TS_P2F:FROM:a9:TO:add_dec/XLXN_47.D:1
-AUTO_TS_P2F:FROM:a8:TO:add_dec/XLXN_47.D:1
-AUTO_TS_P2F:FROM:a10:TO:add_dec/XLXN_47.D:1
-AUTO_TS_P2F:FROM:nio_stb:TO:add_dec/XLXN_47.D:1
-AUTO_TS_P2F:FROM:extclk:TO:add_dec/XLXN_47.CLKF:1
diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd
index 696698e..de09636 100644
--- a/VHDL/AppleIISd.vhd
+++ b/VHDL/AppleIISd.vhd
@@ -32,38 +32,37 @@
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_UNSIGNED.ALL;
---use AddressDecoder.ALL;
 
 
 entity AppleIISd is
 Port (
-		data : inout  STD_LOGIC_VECTOR (7 downto 0);
-		nrw : in  STD_LOGIC;
-		nirq : out  STD_LOGIC;
-		nreset : in  STD_LOGIC;
-		addr : in  STD_LOGIC_VECTOR (1 downto 0);
-		nphi2 : in  STD_LOGIC;
-		ndev_sel : in  STD_LOGIC;
-		extclk : in  STD_LOGIC;
-		spi_miso: in std_logic;
-		spi_mosi : out  STD_LOGIC;
-		spi_sclk : out  STD_LOGIC;
-		spi_Nsel : out  STD_LOGIC;
-		wp : in  STD_LOGIC;
-		card : in  STD_LOGIC;
-		led : out  STD_LOGIC;
+        data : inout  STD_LOGIC_VECTOR (7 downto 0);
+        nrw : in  STD_LOGIC;
+        nirq : out  STD_LOGIC;
+        nreset : in  STD_LOGIC;
+        addr : in  STD_LOGIC_VECTOR (1 downto 0);
+        nphi2 : in  STD_LOGIC;
+        ndev_sel : in  STD_LOGIC;
+        extclk : in  STD_LOGIC;
+        spi_miso: in std_logic;
+        spi_mosi : out  STD_LOGIC;
+        spi_sclk : out  STD_LOGIC;
+        spi_Nsel : out  STD_LOGIC;
+        wp : in  STD_LOGIC;
+        card : in  STD_LOGIC;
+        led : out  STD_LOGIC;
 
-		a8 : in  std_logic;
-		a9 : in  std_logic;
-		a10 : in  std_logic;
-		nio_sel : in  std_logic;
-		nio_stb : in  std_logic;
-		b8 : out  std_logic;
-		b9 : out  std_logic;
-		b10 : out  std_logic;
-		noe : out  std_logic;
-		ng : out  std_logic
-	);
+        a8 : in  std_logic;
+        a9 : in  std_logic;
+        a10 : in  std_logic;
+        nio_sel : in  std_logic;
+        nio_stb : in  std_logic;
+        b8 : out  std_logic;
+        b9 : out  std_logic;
+        b10 : out  std_logic;
+        noe : out  std_logic;
+        ng : out  std_logic
+    );
 
     constant DIV_WIDTH : integer := 3;
 
@@ -89,7 +88,10 @@ architecture Behavioral of AppleIISd is
     signal spidataout: std_logic_vector (7 downto 0);
     signal spiint: std_logic;   -- spi interrupt state
     signal inited: std_logic;   -- card initialized
+    signal inited_set: std_logic;
+    signal inited_reset: std_logic;
     signal inited_int: std_logic;
+    signal inited_intff: std_logic;
     
     -- spi register flags
     signal tc: std_logic;       -- transmission complete; cleared on spi data read
@@ -117,46 +119,62 @@ architecture Behavioral of AppleIISd is
     
     -- spi clock
     signal clksrc: std_logic;                                   -- clock source (phi2 or extclk)
-	-- TODO divcnt is not used at all??
+    -- TODO divcnt is not used at all??
     signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0);          -- divisor counter
     signal shiftclk : std_logic;
 
     component AddressDecoder
-	port ( 
-		A8     : in    std_logic; 
-		A9     : in    std_logic; 
-		A10    : in    std_logic; 
-		CLK : in    std_logic; 
-		NDEV_SEL : in std_logic;
-		NIO_SEL : in    std_logic; 
-		NIO_STB : in    std_logic; 
-		B8   : out   std_logic; 
-		B9   : out   std_logic; 
-		B10  : out   std_logic; 
-		NOE     : out   std_logic
-	);
+    port ( 
+        A8     : in    std_logic; 
+        A9     : in    std_logic; 
+        A10    : in    std_logic; 
+        CLK : in    std_logic; 
+        NDEV_SEL : in std_logic;
+        NIO_SEL : in    std_logic; 
+        NIO_STB : in    std_logic; 
+        B8   : out   std_logic; 
+        B9   : out   std_logic; 
+        B10  : out   std_logic; 
+        NOE     : out   std_logic
+    );
+    end component;
+    
+    component SR_Latch
+    port (
+        S,R : in std_logic;
+        Q, Q_n : inout std_logic;
+        Reset : in std_logic;
+        Clk : in std_logic
+    );
     end component;
     
 begin
     add_dec : AddressDecoder
-	port map (
-		A8=>a8,      
-		A9=>a9,
-		A10=>a10,
-		CLK=>extclk,
-		NDEV_SEL=>ndev_sel,
-		NIO_SEL=>nio_sel,
-		NIO_STB=>nio_stb,
-		B8=>b8,
-		B9=>b9,
-		B10=>b10,
-		NOE=>noe
-	);
+    port map (
+        A8 => a8,      
+        A9 => a9,
+        A10 => a10,
+        CLK => extclk,
+        NDEV_SEL => ndev_sel,
+        NIO_SEL => nio_sel,
+        NIO_STB => nio_stb,
+        B8 => b8,
+        B9 => b9,
+        B10 => b10,
+        NOE => noe);
+    
+    sr_inited : SR_Latch
+    port map (
+        S => inited_set,
+        R => inited_reset,
+        Q => inited,
+        Q_n => open,
+        Reset => reset,
+        Clk => extclk);
     
-	
     led <= not (bsy or not slavesel);
     ng <=  ndev_sel and nio_sel and nio_stb;
-    inited <= inited_int and not card;
+    inited_reset <= card;
     bsy <= start_shifting or shifting2;
     
     process(start_shifting, shiftdone, shiftclk)
@@ -232,7 +250,7 @@ begin
                         when "101" => int_mosi <= spidataout(2);
                         when "110" => int_mosi <= spidataout(1);
                         when "111" => int_mosi <= spidataout(0);
-						when others => int_mosi <= '1';
+                        when others => int_mosi <= '1';
                     end case;
                     int_sclk <= cpol xor cpha xor shiftcnt(0);
                 end if;
@@ -302,12 +320,27 @@ begin
         if (shiftdone = '1') then
             tc <= '1';
         elsif (falling_edge(selected) and addr="00") then
-			tc <= '0';
+            tc <= '0';
         end if;
     end process;
     
     spiint <= tc and ier;
 
+
+    -- inited_set pulse
+    process(extclk, reset)
+    begin
+        if(reset = '1') then
+            inited_set <= '0';
+        elsif falling_edge(extclk) then
+            inited_intff <= inited_int;     -- one cycle delayed version
+            inited_set <= '0';              -- default value
+            if (inited_int = '1') and (inited_intff = '0') then
+                inited_set <= '1';
+            end if;
+        end if;
+    end process;
+    
     --------------------------
     -- cpu register section
     -- cpu read
@@ -338,8 +371,8 @@ begin
                     int_dout(5) <= wp;
                     int_dout(6) <= card;
                     int_dout(7) <= inited;
-				when others => 
-					int_dout <= (others => '0');
+                when others => 
+                    int_dout <= (others => '0');
             end case;
         else
             int_dout <= (others => '0');
@@ -347,7 +380,7 @@ begin
     end process;
 
     -- cpu write 
-    cpu_write: process(reset, selected, nrw, addr, int_din, inited)
+    cpu_write: process(reset, selected, nrw, addr, int_din)
     begin
         if (reset = '1') then
             cpha <= '0';
@@ -358,7 +391,6 @@ begin
             ier <= '0';
             slavesel <= '1';
             slaveinten <= '0';
-            inited_int <= '0';
             divisor <= (others => '0');
             spidataout <= (others => '1');
         elsif (falling_edge(selected) and nrw = '0') then
@@ -380,7 +412,7 @@ begin
                     slavesel <= int_din(0);
                     slaveinten <= int_din(4);
                     inited_int <= int_din(7);
-				when others =>
+                when others =>
             end case;
         end if;
     end process;
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index 66a853e..76af624 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -17,15 +17,19 @@
   <files>
     <file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
+    <file xil_pn:name="sr_latch.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+    </file>
   </files>
 
   <properties>
@@ -55,7 +59,6 @@
     <property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/VHDL/sr_latch.vhd b/VHDL/sr_latch.vhd
new file mode 100644
index 0000000..2f87492
--- /dev/null
+++ b/VHDL/sr_latch.vhd
@@ -0,0 +1,55 @@
+----------------------------------------------------------------------------------
+-- Company: 
+-- Engineer: 
+-- 
+-- Create Date:    22:26:04 09/09/2017 
+-- Design Name: 
+-- Module Name:    sr_latch - Behavioral 
+-- Project Name: 
+-- Target Devices: 
+-- Tool versions: 
+-- Description: 
+--
+-- Dependencies: 
+--
+-- Revision: 
+-- Revision 0.01 - File Created
+-- Additional Comments: 
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+
+entity SR_Latch is  
+Port ( S,R : in STD_LOGIC;  
+       Q : inout STD_LOGIC;  
+       Q_n : inout STD_LOGIC;  
+       Reset : in STD_LOGIC;
+       Clk : in STD_LOGIC);
+end SR_Latch;  
+   
+architecture SR_Latch_arch of SR_Latch is  
+begin  
+    process (S,R,Q,Q_n, Reset, Clk)  
+    begin  
+        if(rising_edge(Clk)) then
+            if(Reset = '1') then
+                Q <= '0';
+                Q_n <= '1';
+            else
+                Q <= R NOR Q_n;  
+                Q_n <= S NOR Q; 
+            end if; 
+        end if;
+   end process;  
+end SR_Latch_arch;