diff --git a/VHDL/AddressDecoder_Test.vhd b/VHDL/AddressDecoder_Test.vhd
new file mode 100644
index 0000000..137d09c
--- /dev/null
+++ b/VHDL/AddressDecoder_Test.vhd
@@ -0,0 +1,79 @@
+-- Vhdl test bench created from schematic U:\AppleIISd\VHDL\AddressDecoder.sch - Mon Oct 09 20:12:16 2017
+--
+-- Notes:
+-- 1) This testbench template has been automatically generated using types
+-- std_logic and std_logic_vector for the ports of the unit under test.
+-- Xilinx recommends that these types always be used for the top-level
+-- I/O of a design in order to guarantee that the testbench will bind
+-- correctly to the timing (post-route) simulation model.
+-- 2) To use this template as your testbench, change the filename to any
+-- name of your choice with the extension .vhd, and use the "Source->Add"
+-- menu in Project Navigator to import the testbench. Then
+-- edit the user defined section below, adding code to generate the
+-- stimulus for your design.
+--
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+USE ieee.numeric_std.ALL;
+LIBRARY UNISIM;
+USE UNISIM.Vcomponents.ALL;
+ENTITY AddressDecoder_AddressDecoder_sch_tb IS
+END AddressDecoder_AddressDecoder_sch_tb;
+ARCHITECTURE behavioral OF AddressDecoder_AddressDecoder_sch_tb IS
+
+ COMPONENT AddressDecoder
+ PORT( A10 : IN STD_LOGIC;
+ A9 : IN STD_LOGIC;
+ A8 : IN STD_LOGIC;
+ B10 : OUT STD_LOGIC;
+ B9 : OUT STD_LOGIC;
+ B8 : OUT STD_LOGIC;
+ NIO_SEL : IN STD_LOGIC;
+ NDEV_SEL : IN STD_LOGIC;
+ NOE : OUT STD_LOGIC;
+ RNW : IN STD_LOGIC;
+ NG : OUT STD_LOGIC;
+ DATA_EN : OUT STD_LOGIC;
+ NIO_STB : IN STD_LOGIC);
+ END COMPONENT;
+
+ SIGNAL A10 : STD_LOGIC := '0';
+ SIGNAL A9 : STD_LOGIC := '0';
+ SIGNAL A8 : STD_LOGIC := '0';
+ SIGNAL B10 : STD_LOGIC;
+ SIGNAL B9 : STD_LOGIC;
+ SIGNAL B8 : STD_LOGIC;
+ SIGNAL NIO_SEL : STD_LOGIC := '1';
+ SIGNAL NDEV_SEL : STD_LOGIC := '1';
+ SIGNAL NOE : STD_LOGIC;
+ SIGNAL RNW : STD_LOGIC := '1';
+ SIGNAL NG : STD_LOGIC;
+ SIGNAL DATA_EN : STD_LOGIC;
+ SIGNAL NIO_STB : STD_LOGIC := '1';
+
+BEGIN
+
+ UUT: AddressDecoder PORT MAP(
+ A10 => A10,
+ A9 => A9,
+ A8 => A8,
+ B10 => B10,
+ B9 => B9,
+ B8 => B8,
+ NIO_SEL => NIO_SEL,
+ NDEV_SEL => NDEV_SEL,
+ NOE => NOE,
+ RNW => RNW,
+ NG => NG,
+ DATA_EN => DATA_EN,
+ NIO_STB => NIO_STB
+ );
+
+-- *** Test Bench - User Defined Section ***
+ tb : PROCESS
+ BEGIN
+ WAIT; -- will wait forever
+ END PROCESS;
+-- *** End Test Bench - User Defined Section ***
+
+END;
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index 32d3070..8d6159d 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -20,14 +20,22 @@
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diff --git a/VHDL/AppleIISd_Test.vhd b/VHDL/AppleIISd_Test.vhd
new file mode 100644
index 0000000..6a1b743
--- /dev/null
+++ b/VHDL/AppleIISd_Test.vhd
@@ -0,0 +1,137 @@
+--------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:21:20 10/09/2017
+-- Design Name:
+-- Module Name: U:/AppleIISd/VHDL/AppleIISd_Test.vhd
+-- Project Name: AppleIISd
+-- Target Device:
+-- Tool versions:
+-- Description:
+--
+-- VHDL Test Bench Created by ISE for module: AppleIISd
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+-- Notes:
+-- This testbench has been automatically generated using types std_logic and
+-- std_logic_vector for the ports of the unit under test. Xilinx recommends
+-- that these types always be used for the top-level I/O of a design in order
+-- to guarantee that the testbench will bind correctly to the post-implementation
+-- simulation model.
+--------------------------------------------------------------------------------
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+
+ENTITY AppleIISd_Test IS
+END AppleIISd_Test;
+
+ARCHITECTURE behavior OF AppleIISd_Test IS
+
+ -- Component Declaration for the Unit Under Test (UUT)
+
+ COMPONENT AppleIISd
+ PORT(
+ data_in : IN std_logic_vector(7 downto 0);
+ data_out : OUT std_logic_vector(7 downto 0);
+ is_read : IN std_logic;
+ reset : IN std_logic;
+ addr : IN std_logic_vector(1 downto 0);
+ phi0 : IN std_logic;
+ selected : IN std_logic;
+ clk : IN std_logic;
+ miso : IN std_logic;
+ mosi : OUT std_logic;
+ sclk : OUT std_logic;
+ nsel : OUT std_logic;
+ wp : IN std_logic;
+ card : IN std_logic;
+ led : OUT std_logic
+ );
+ END COMPONENT;
+
+
+ --Inputs
+ signal data_in : std_logic_vector(7 downto 0) := (others => '0');
+ signal is_read : std_logic := '0';
+ signal reset : std_logic := '0';
+ signal addr : std_logic_vector(1 downto 0) := (others => '0');
+ signal phi0 : std_logic := '1';
+ signal selected : std_logic := '0';
+ signal clk : std_logic := '0';
+ signal miso : std_logic := '0';
+ signal wp : std_logic := '0';
+ signal card : std_logic := '0';
+
+ --Outputs
+ signal data_out : std_logic_vector(7 downto 0);
+ signal mosi : std_logic;
+ signal sclk : std_logic;
+ signal nsel : std_logic;
+ signal led : std_logic;
+
+ -- Clock period definitions
+ constant clk_period : time := 142 ns; -- 7MHz
+
+BEGIN
+
+ -- Instantiate the Unit Under Test (UUT)
+ uut: AppleIISd PORT MAP (
+ data_in => data_in,
+ data_out => data_out,
+ is_read => is_read,
+ reset => reset,
+ addr => addr,
+ phi0 => phi0,
+ selected => selected,
+ clk => clk,
+ miso => miso,
+ mosi => mosi,
+ sclk => sclk,
+ nsel => nsel,
+ wp => wp,
+ card => card,
+ led => led
+ );
+
+ -- Clock process definitions
+ clk_process :process
+ begin
+ clk <= '0';
+ wait for clk_period/2;
+ clk <= '1';
+ wait for clk_period/2;
+ end process;
+
+ phi0_process :process
+ begin
+ phi0 <= '1';
+ wait for clk_period/14;
+ phi0 <= '0';
+ wait for clk_period/14;
+ end process;
+
+ -- Stimulus process
+ stim_proc: process
+ begin
+ -- hold reset state for 100 ns.
+ wait for 100 ns;
+ reset <= '1';
+ wait for 100 ns;
+ wait for clk_period*10;
+
+ -- insert stimulus here
+
+ wait;
+ end process;
+
+END;
diff --git a/VHDL/IO.vhd b/VHDL/IO.vhd
new file mode 100644
index 0000000..e2431e6
--- /dev/null
+++ b/VHDL/IO.vhd
@@ -0,0 +1,179 @@
+----------------------------------------------------------------------------------
+-- Company:
+-- Engineer:
+--
+-- Create Date: 20:44:25 10/09/2017
+-- Design Name:
+-- Module Name: IO - Behavioral
+-- Project Name:
+-- Target Devices:
+-- Tool versions:
+-- Description:
+--
+-- Dependencies:
+--
+-- Revision:
+-- Revision 0.01 - File Created
+-- Additional Comments:
+--
+----------------------------------------------------------------------------------
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--use IEEE.NUMERIC_STD.ALL;
+
+-- Uncomment the following library declaration if instantiating
+-- any Xilinx primitives in this code.
+--library UNISIM;
+--use UNISIM.VComponents.all;
+
+entity IO is
+Port (
+ ADD_HIGH : in std_logic_vector(10 downto 8);
+ ADD_LOW : in std_logic_vector(1 downto 0);
+ B10 : out std_logic;
+ B9 : out std_logic;
+ B8 : out std_logic;
+ CARD : in std_logic;
+ DATA : inout std_logic_vector (7 downto 0);
+ CLK : in std_logic;
+ LED : out std_logic;
+ NDEV_SEL : in std_logic;
+ NG : out std_logic;
+ NIO_SEL : in std_logic;
+ NIO_STB : in std_logic;
+ NOE : out std_logic;
+ PHI0 : in std_logic;
+ NRESET : in std_logic;
+ RNW : in std_logic;
+ MISO : in std_logic;
+ MOSI : out std_logic;
+ NSEL : out std_logic;
+ SCLK : out std_logic;
+ WP : in std_logic
+ );
+end IO;
+
+architecture Behavioral of IO is
+
+ signal data_in : std_logic_vector (7 downto 0);
+ signal data_out : std_logic_vector (7 downto 0);
+ signal addr_low_int : std_logic_vector (1 downto 0);
+ signal wp_int : std_logic;
+ signal card_int : std_logic;
+ signal miso_int : std_logic;
+
+ signal ndev_sel_int : std_logic;
+ signal rnw_int : std_logic;
+ signal data_en : std_logic;
+
+component AppleIISd is
+Port (
+ data_in : in std_logic_vector (7 downto 0);
+ data_out : out std_logic_vector (7 downto 0);
+ is_read : in std_logic;
+ reset : in std_logic;
+ addr : in std_logic_vector (1 downto 0);
+ phi0 : in std_logic;
+ selected : in std_logic;
+ clk : in std_logic;
+ miso: in std_logic;
+ mosi : out std_logic;
+ sclk : out std_logic;
+ nsel : out std_logic;
+ wp : in std_logic;
+ card : in std_logic;
+ led : out std_logic
+ );
+end component;
+
+component AddressDecoder
+ port (
+ A8 : in std_logic;
+ A9 : in std_logic;
+ A10 : in std_logic;
+ NDEV_SEL : in std_logic;
+ NIO_SEL : in std_logic;
+ NIO_STB : in std_logic;
+ RNW : in std_logic;
+ B8 : out std_logic;
+ B9 : out std_logic;
+ B10 : out std_logic;
+ NOE : out std_logic;
+ NG : out std_logic;
+ DATA_EN : out std_logic
+ );
+ end component;
+
+begin
+ spi: AppleIISd port map(
+ data_in => data_in,
+ data_out => data_out,
+ is_read => rnw_int,
+ reset => not NRESET,
+ addr => addr_low_int,
+ phi0 => PHI0,
+ selected => not ndev_sel_int,
+ clk => CLK,
+ miso => miso_int,
+ mosi => MOSI,
+ sclk => SCLK,
+ nsel => NSEL,
+ wp => wp_int,
+ card => card_int,
+ led => LED
+ );
+
+ addDec: AddressDecoder port map(
+ A8 => ADD_HIGH(8),
+ A9 => ADD_HIGH(9),
+ A10 => ADD_HIGH(10),
+ NDEV_SEL => NDEV_SEL,
+ NIO_SEL => NIO_SEL,
+ NIO_STB => NIO_STB,
+ RNW => RNW,
+ B8 => B8,
+ B9 => B9,
+ B10 => B10,
+ NOE => NOE,
+ NG => NG,
+ DATA_EN => data_en
+ );
+
+ ctrl_latch: process(CLK, NRESET)
+ begin
+ if(NRESET = '0') then
+ ndev_sel_int <= '1';
+ rnw_int <= '1';
+ wp_int <= '1';
+ card_int <= '1';
+ miso_int <= '1';
+ elsif rising_edge(CLK) then
+ ndev_sel_int <= NDEV_SEL;
+ rnw_int <= RNW;
+ wp_int <= WP;
+ card_int <= CARD;
+ miso_int <= MISO;
+ end if;
+ end process;
+
+ DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
+
+ data_latch: process(ndev_sel)
+ begin
+ if(rising_edge(ndev_sel) and (rnw_int = '0')) then
+ data_in <= DATA;
+ end if;
+ end process;
+
+ add_latch: process(ndev_sel)
+ begin
+ if falling_edge(ndev_sel) then
+ addr_low_int <= ADD_LOW;
+ end if;
+ end process;
+
+end Behavioral;
+
diff --git a/VHDL/io_buffers.tim b/VHDL/io_buffers.tim
deleted file mode 100644
index e69de29..0000000
diff --git a/VHDL/sch2HdlBatchFile b/VHDL/sch2HdlBatchFile
index 6e0be78..0bddd47 100644
--- a/VHDL/sch2HdlBatchFile
+++ b/VHDL/sch2HdlBatchFile
@@ -1 +1 @@
-sch2hdl,-intstyle,ise,-family,xc9500xl,-verilog,U:/AppleIISd/VHDL/io_buffers.vf,-w,U:/AppleIISd/VHDL/io_buffers.sch
+sch2hdl,-intstyle,ise,-family,xc9500xl,-flat,-suppress,-vhdl,U:/AppleIISd/VHDL/AddressDecoder.vhf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch