diff --git a/VHDL/AppleIISd.vhd b/VHDL/AppleIISd.vhd
index 6a820d3..8f120d6 100644
--- a/VHDL/AppleIISd.vhd
+++ b/VHDL/AppleIISd.vhd
@@ -72,14 +72,14 @@ architecture Behavioral of AppleIISd is
signal ece: std_logic; -- external clock enable; 0=phi2, 1=external clock
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
- signal slavesel: std_logic; -- slave select output (0=selected)
+ signal slavesel: std_logic := '1'; -- slave select output (0=selected)
signal int_miso: std_logic;
--------------------------
-- helper signals
-- shift engine
- signal start_shifting: std_logic; -- shifting data
- signal shifting2: std_logic; -- shifting data
+ signal start_shifting: std_logic := '0'; -- shifting data
+ signal shifting2: std_logic := '0'; -- shifting data
signal shiftdone: std_logic; -- shifting data done
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
diff --git a/VHDL/AppleIISd.xise b/VHDL/AppleIISd.xise
index f5a23d4..7233aaf 100644
--- a/VHDL/AppleIISd.xise
+++ b/VHDL/AppleIISd.xise
@@ -31,11 +31,11 @@
-
+
-
+
@@ -152,14 +152,14 @@
-
+
-
+
@@ -198,7 +198,7 @@
-
+
diff --git a/VHDL/AppleIISd_Test.vhd b/VHDL/AppleIISd_Test.vhd
index c9a4d47..1866a58 100644
--- a/VHDL/AppleIISd_Test.vhd
+++ b/VHDL/AppleIISd_Test.vhd
@@ -61,7 +61,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
--Inputs
- signal data_in : std_logic_vector(7 downto 0) := (others => '0');
+ signal data_in : std_logic_vector(7 downto 0) := (others => '1');
signal is_read : std_logic := '0';
signal reset : std_logic := '0';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
@@ -112,30 +112,36 @@ BEGIN
wait for clk_period/2;
end process;
- phi0_process :process
+ phi0_process :process(clk)
+ variable counter : integer range 0 to 7;
begin
- phi0 <= '1';
- wait for clk_period/14;
- phi0 <= '0';
- wait for clk_period/14;
+ if rising_edge(clk) or falling_edge(clk) then
+ counter := counter + 1;
+ if counter = 7 then
+ phi0 <= not phi0;
+ counter := 0;
+ end if;
+ end if;
end process;
-- Stimulus process
stim_proc: process
begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
+ -- hold reset state.
+ wait for clk_period * 20;
reset <= '1';
- wait for 100 ns;
+ wait for clk_period * 20;
reset <= '0';
- wait for clk_period*10;
+ wait for clk_period * 5;
+ wait until rising_edge(phi0);
-- insert stimulus here
selected <= '1';
- data_in <= (others => '1');
- wait for clk_period * 7;
+ wait for clk_period;
+ data_in <= (others => '0');
+ wait until falling_edge(phi0);
selected <= '0';
- wait for clk_period * 10;
-
+ wait for clk_period;
+ data_in <= (others => '1');
wait;
end process;
diff --git a/VHDL/sch2HdlBatchFile b/VHDL/sch2HdlBatchFile
index 0bddd47..e69de29 100644
--- a/VHDL/sch2HdlBatchFile
+++ b/VHDL/sch2HdlBatchFile
@@ -1 +0,0 @@
-sch2hdl,-intstyle,ise,-family,xc9500xl,-flat,-suppress,-vhdl,U:/AppleIISd/VHDL/AddressDecoder.vhf,-w,U:/AppleIISd/VHDL/AddressDecoder.sch