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New address decoding

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This commit is contained in:
freitz85 2017-10-16 22:53:41 +02:00
parent b37df65a45
commit c5945ff0ec
9 changed files with 606 additions and 608 deletions
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21
VHDL/AddressDecoder.vhd
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@ -30,7 +30,7 @@ use IEEE.STD_LOGIC_1164.ALL;
--use UNISIM.VComponents.all;
entity AddressDecoder is
Port ( A : in std_logic_vector (10 downto 8);
Port ( A : in std_logic_vector (11 downto 8);
B : out std_logic_vector (10 downto 8); -- to EPROM
CLK : in std_logic;
PHI0 : in std_logic;
@ -61,18 +61,15 @@ begin
-- only from the first rising edge of 7M when any select
-- line is low (Phi0 high) to the falling edge of Phi0
B <= A when (NIO_STB = '0') else (others => '0');
B(8) <= A(8) or not A(11);
B(9) <= A(9) or not A(11);
B(10) <= A(10) or not A(11);
DATA_EN <= RNW and not ndev_sel_int and PHI0;
--NG <= (ndev_sel_int and noe_int) or not PHI0;
--NOE <= noe_int or not PHI0;
--noe_int <= not RNW or not ndev_sel_int
-- or (nio_sel_int and nio_stb_int)
-- or (nio_sel_int and ncs);
NG <= (NDEV_SEL and NIO_SEL and NIO_STB)
or (ncs and NDEV_SEL and NIO_SEL);
NOE <= not RNW or not NDEV_SEL
or (not NIO_STB and ncs);
NG <= (ndev_sel_int and noe_int) or not PHI0;
NOE <= noe_int or not PHI0;
noe_int <= not RNW or not ndev_sel_int
or (nio_sel_int and nio_stb_int)
or (nio_sel_int and ncs);
cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;

36
VHDL/AddressDecoder_Test.vhd
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@ -41,7 +41,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
COMPONENT AddressDecoder
PORT(
A : IN std_logic_vector(10 downto 8);
A : IN std_logic_vector(11 downto 8);
B : OUT std_logic_vector(10 downto 8);
CLK : IN std_logic;
PHI0 : IN std_logic;
@ -58,7 +58,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
--Inputs
signal A : std_logic_vector(10 downto 8) := "101";
signal A : std_logic_vector(11 downto 8) := "0101";
signal RNW : std_logic := '1';
signal NDEV_SEL : std_logic := '1';
signal NIO_SEL : std_logic := '1';
@ -126,45 +126,61 @@ BEGIN
wait for CLK_period * 10;
-- insert stimulus here
-- CPLD access
-- C0nX access
A <= "0000"; -- must become "111"
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CnXX access
A <= "0100"; -- must become "111"
wait until rising_edge(PHI0);
NIO_SEL <= '0';
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- C8xx access, selected
A <= "1000"; -- must become "000"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
-- C9xx access, selected
A <= "1001"; -- must become "001"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
-- CPLD access
A <= "0101"; -- must become "111"
wait until rising_edge(PHI0);
NDEV_SEL <= '0';
wait until falling_edge(PHI0);
NDEV_SEL <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- CFFF access
A <= "111";
A <= "1111"; -- must become "111"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
A <= "000";
NIO_STB <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
-- C8xx access, unselected
A <= "1000"; -- must become "000"
wait until rising_edge(PHI0);
NIO_STB <= '0';
wait until falling_edge(PHI0);
NIO_STB <= '1';
wait until rising_edge(PHI0);
wait until rising_edge(PHI0);
wait;
end process;

0
VHDL/AddressDecoder_old.schlog
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1102
VHDL/AppleIISd.jed
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File diff suppressed because it is too large Load Diff

0
VHDL/AppleIISd.tim
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1
VHDL/AppleIISd.ucf
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@ -3,6 +3,7 @@ NET "DATA<2>" BUFG = DATA_GATE ;
NET "DATA<3>" BUFG = DATA_GATE ;
NET "DATA<4>" BUFG = DATA_GATE ;
#PACE: Start of PACE I/O Pin Assignments
NET "ADD_HIGH<11>" LOC = "P44" ;
NET "ADD_HIGH<10>" LOC = "P38" ;
NET "ADD_HIGH<8>" LOC = "P36" ;
NET "ADD_HIGH<9>" LOC = "P37" ;

4
VHDL/AppleIISd.vhd
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@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
entity AppleIISd is
Port (
ADD_HIGH : in std_logic_vector(10 downto 8);
ADD_HIGH : in std_logic_vector(11 downto 8);
ADD_LOW : in std_logic_vector(1 downto 0);
B : out std_logic_vector(10 downto 8);
CARD : in std_logic;
@ -95,7 +95,7 @@ end component;
component AddressDecoder
Port (
A : in std_logic_vector (10 downto 8);
A : in std_logic_vector (11 downto 8);
B : out std_logic_vector (10 downto 8);
CLK : in std_logic;
PHI0 : in std_logic;

18
VHDL/AppleIISd.xise
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@ -16,26 +16,26 @@
<files>
<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
</file>
<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
</file>
<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
@ -159,8 +159,8 @@
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
@ -170,7 +170,7 @@
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
@ -205,7 +205,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>

32
VHDL/AppleIISd_Test.vhd
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@ -41,7 +41,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
COMPONENT AppleIISd
PORT(
ADD_HIGH : IN std_logic_vector(10 downto 8);
ADD_HIGH : IN std_logic_vector(11 downto 8);
ADD_LOW : IN std_logic_vector(1 downto 0);
B : OUT std_logic_vector(10 downto 8);
CARD : IN std_logic;
@ -70,7 +70,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
--Inputs
signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U');
signal ADD_HIGH : std_logic_vector(11 downto 8) := (others => '0');
signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
signal CARD : std_logic := '0';
signal CLK : std_logic := '0';
@ -253,7 +253,7 @@ BEGIN
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
ADD_HIGH <= (others => '0');
ADD_HIGH <= "0100"; -- must become "111"
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
@ -265,27 +265,11 @@ BEGIN
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
-- read eprom low
-- read eprom high, selected
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
ADD_HIGH <= "101";
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
NIO_SEL <= '0';
DATA <= (others => 'Z');
wait until falling_edge(PHI0);
NIO_SEL <= '1';
wait for ADD_hold;
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
-- read eprom high
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
ADD_HIGH <= "101";
ADD_HIGH <= "1001"; -- must become "001"
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
@ -301,7 +285,7 @@ BEGIN
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '1');
ADD_HIGH <= (others => '1');
ADD_HIGH <= "1111";
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);
@ -313,11 +297,11 @@ BEGIN
ADD_LOW <= (others => 'U');
ADD_HIGH <= (others => 'U');
-- read eprom high
-- read eprom high, deselected
wait until falling_edge(PHI0);
wait for ADD_valid;
ADD_LOW <= (others => '0');
ADD_HIGH <= "101";
ADD_HIGH <= "1101"; -- must become "101"
RNW <= '1';
DATA <= (others => 'U');
wait until rising_edge(PHI0);