forked from Apple-2-HW/AppleIISd
New address decoding
This commit is contained in:
parent
b37df65a45
commit
c5945ff0ec
@ -30,7 +30,7 @@ use IEEE.STD_LOGIC_1164.ALL;
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--use UNISIM.VComponents.all;
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--use UNISIM.VComponents.all;
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entity AddressDecoder is
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entity AddressDecoder is
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Port ( A : in std_logic_vector (10 downto 8);
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Port ( A : in std_logic_vector (11 downto 8);
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B : out std_logic_vector (10 downto 8); -- to EPROM
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B : out std_logic_vector (10 downto 8); -- to EPROM
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CLK : in std_logic;
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CLK : in std_logic;
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PHI0 : in std_logic;
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PHI0 : in std_logic;
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@ -61,18 +61,15 @@ begin
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-- only from the first rising edge of 7M when any select
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-- only from the first rising edge of 7M when any select
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-- line is low (Phi0 high) to the falling edge of Phi0
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-- line is low (Phi0 high) to the falling edge of Phi0
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B <= A when (NIO_STB = '0') else (others => '0');
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B(8) <= A(8) or not A(11);
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B(9) <= A(9) or not A(11);
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B(10) <= A(10) or not A(11);
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DATA_EN <= RNW and not ndev_sel_int and PHI0;
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DATA_EN <= RNW and not ndev_sel_int and PHI0;
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--NG <= (ndev_sel_int and noe_int) or not PHI0;
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NG <= (ndev_sel_int and noe_int) or not PHI0;
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--NOE <= noe_int or not PHI0;
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NOE <= noe_int or not PHI0;
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--noe_int <= not RNW or not ndev_sel_int
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noe_int <= not RNW or not ndev_sel_int
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-- or (nio_sel_int and nio_stb_int)
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or (nio_sel_int and nio_stb_int)
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-- or (nio_sel_int and ncs);
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or (nio_sel_int and ncs);
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NG <= (NDEV_SEL and NIO_SEL and NIO_STB)
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or (ncs and NDEV_SEL and NIO_SEL);
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NOE <= not RNW or not NDEV_SEL
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or (not NIO_STB and ncs);
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cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
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cfxx <= A(8) and A(9) and A(10) and not nio_stb_int;
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@ -41,7 +41,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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COMPONENT AddressDecoder
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COMPONENT AddressDecoder
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PORT(
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PORT(
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A : IN std_logic_vector(10 downto 8);
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A : IN std_logic_vector(11 downto 8);
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B : OUT std_logic_vector(10 downto 8);
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B : OUT std_logic_vector(10 downto 8);
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CLK : IN std_logic;
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CLK : IN std_logic;
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PHI0 : IN std_logic;
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PHI0 : IN std_logic;
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@ -58,7 +58,7 @@ ARCHITECTURE behavior OF AddressDecoder_Test IS
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--Inputs
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--Inputs
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signal A : std_logic_vector(10 downto 8) := "101";
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signal A : std_logic_vector(11 downto 8) := "0101";
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signal RNW : std_logic := '1';
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signal RNW : std_logic := '1';
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signal NDEV_SEL : std_logic := '1';
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signal NDEV_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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signal NIO_SEL : std_logic := '1';
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@ -126,45 +126,61 @@ BEGIN
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wait for CLK_period * 10;
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wait for CLK_period * 10;
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-- insert stimulus here
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-- insert stimulus here
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-- CPLD access
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-- C0nX access
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A <= "0000"; -- must become "111"
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CnXX access
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-- CnXX access
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A <= "0100"; -- must become "111"
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wait until rising_edge(PHI0);
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NIO_SEL <= '0';
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NIO_SEL <= '0';
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NIO_SEL <= '1';
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NIO_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C8xx access, selected
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-- C8xx access, selected
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A <= "1000"; -- must become "000"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C9xx access, selected
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A <= "1001"; -- must become "001"
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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-- CPLD access
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-- CPLD access
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A <= "0101"; -- must become "111"
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wait until rising_edge(PHI0);
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NDEV_SEL <= '0';
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NDEV_SEL <= '0';
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NDEV_SEL <= '1';
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NDEV_SEL <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- CFFF access
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-- CFFF access
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A <= "111";
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A <= "1111"; -- must become "111"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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A <= "000";
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NIO_STB <= '1';
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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-- C8xx access, unselected
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-- C8xx access, unselected
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A <= "1000"; -- must become "000"
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wait until rising_edge(PHI0);
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NIO_STB <= '0';
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NIO_STB <= '0';
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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NIO_STB <= '1';
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NIO_STB <= '1';
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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wait;
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wait;
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end process;
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end process;
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1102
VHDL/AppleIISd.jed
1102
VHDL/AppleIISd.jed
File diff suppressed because it is too large
Load Diff
@ -3,6 +3,7 @@ NET "DATA<2>" BUFG = DATA_GATE ;
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NET "DATA<3>" BUFG = DATA_GATE ;
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NET "DATA<3>" BUFG = DATA_GATE ;
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NET "DATA<4>" BUFG = DATA_GATE ;
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NET "DATA<4>" BUFG = DATA_GATE ;
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#PACE: Start of PACE I/O Pin Assignments
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#PACE: Start of PACE I/O Pin Assignments
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NET "ADD_HIGH<11>" LOC = "P44" ;
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NET "ADD_HIGH<10>" LOC = "P38" ;
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NET "ADD_HIGH<10>" LOC = "P38" ;
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NET "ADD_HIGH<8>" LOC = "P36" ;
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NET "ADD_HIGH<8>" LOC = "P36" ;
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NET "ADD_HIGH<9>" LOC = "P37" ;
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NET "ADD_HIGH<9>" LOC = "P37" ;
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@ -31,7 +31,7 @@ use IEEE.STD_LOGIC_1164.ALL;
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entity AppleIISd is
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entity AppleIISd is
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Port (
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Port (
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ADD_HIGH : in std_logic_vector(10 downto 8);
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ADD_HIGH : in std_logic_vector(11 downto 8);
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ADD_LOW : in std_logic_vector(1 downto 0);
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ADD_LOW : in std_logic_vector(1 downto 0);
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B : out std_logic_vector(10 downto 8);
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B : out std_logic_vector(10 downto 8);
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CARD : in std_logic;
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CARD : in std_logic;
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@ -95,7 +95,7 @@ end component;
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component AddressDecoder
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component AddressDecoder
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Port (
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Port (
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A : in std_logic_vector (10 downto 8);
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A : in std_logic_vector (11 downto 8);
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B : out std_logic_vector (10 downto 8);
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B : out std_logic_vector (10 downto 8);
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CLK : in std_logic;
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CLK : in std_logic;
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PHI0 : in std_logic;
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PHI0 : in std_logic;
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@ -16,26 +16,26 @@
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<files>
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<files>
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<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="SpiController.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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</file>
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<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
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<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
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</file>
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</file>
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<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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</file>
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<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="AppleIISd_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="72"/>
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</file>
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</file>
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<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="AddressDecoder.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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</file>
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<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
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<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
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</file>
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</file>
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<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
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<file xil_pn:name="AddressDecoder_old.sch" xil_pn:type="FILE_SCHEMATIC">
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@ -159,8 +159,8 @@
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<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddressDecoder_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AppleIISd_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
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<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
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@ -170,7 +170,7 @@
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<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddressDecoder_Test" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AppleIISd_Test" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
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@ -205,7 +205,7 @@
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<!-- -->
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<!-- -->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- The following properties are for internal use only. These should not be modified.-->
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<!-- -->
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<!-- -->
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddressDecoder_Test|behavior" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AppleIISd_Test|behavior" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DesignName" xil_pn:value="AppleIISd" xil_pn:valueState="non-default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="xc9500xl" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
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@ -41,7 +41,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
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COMPONENT AppleIISd
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COMPONENT AppleIISd
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PORT(
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PORT(
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ADD_HIGH : IN std_logic_vector(10 downto 8);
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ADD_HIGH : IN std_logic_vector(11 downto 8);
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ADD_LOW : IN std_logic_vector(1 downto 0);
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ADD_LOW : IN std_logic_vector(1 downto 0);
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B : OUT std_logic_vector(10 downto 8);
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B : OUT std_logic_vector(10 downto 8);
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CARD : IN std_logic;
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CARD : IN std_logic;
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@ -70,7 +70,7 @@ ARCHITECTURE behavior OF AppleIISd_Test IS
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--Inputs
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--Inputs
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signal ADD_HIGH : std_logic_vector(10 downto 8) := (others => 'U');
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signal ADD_HIGH : std_logic_vector(11 downto 8) := (others => '0');
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signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
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signal ADD_LOW : std_logic_vector(1 downto 0) := (others => 'U');
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signal CARD : std_logic := '0';
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signal CARD : std_logic := '0';
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signal CLK : std_logic := '0';
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signal CLK : std_logic := '0';
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@ -253,7 +253,7 @@ BEGIN
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wait until falling_edge(PHI0);
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wait until falling_edge(PHI0);
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wait for ADD_valid;
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wait for ADD_valid;
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ADD_LOW <= (others => '0');
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ADD_LOW <= (others => '0');
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ADD_HIGH <= (others => '0');
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ADD_HIGH <= "0100"; -- must become "111"
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RNW <= '1';
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RNW <= '1';
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DATA <= (others => 'U');
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DATA <= (others => 'U');
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wait until rising_edge(PHI0);
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wait until rising_edge(PHI0);
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@ -265,27 +265,11 @@ BEGIN
|
|||||||
ADD_LOW <= (others => 'U');
|
ADD_LOW <= (others => 'U');
|
||||||
ADD_HIGH <= (others => 'U');
|
ADD_HIGH <= (others => 'U');
|
||||||
|
|
||||||
-- read eprom low
|
-- read eprom high, selected
|
||||||
wait until falling_edge(PHI0);
|
wait until falling_edge(PHI0);
|
||||||
wait for ADD_valid;
|
wait for ADD_valid;
|
||||||
ADD_LOW <= (others => '0');
|
ADD_LOW <= (others => '0');
|
||||||
ADD_HIGH <= "101";
|
ADD_HIGH <= "1001"; -- must become "001"
|
||||||
RNW <= '1';
|
|
||||||
DATA <= (others => 'U');
|
|
||||||
wait until rising_edge(PHI0);
|
|
||||||
NIO_SEL <= '0';
|
|
||||||
DATA <= (others => 'Z');
|
|
||||||
wait until falling_edge(PHI0);
|
|
||||||
NIO_SEL <= '1';
|
|
||||||
wait for ADD_hold;
|
|
||||||
ADD_LOW <= (others => 'U');
|
|
||||||
ADD_HIGH <= (others => 'U');
|
|
||||||
|
|
||||||
-- read eprom high
|
|
||||||
wait until falling_edge(PHI0);
|
|
||||||
wait for ADD_valid;
|
|
||||||
ADD_LOW <= (others => '0');
|
|
||||||
ADD_HIGH <= "101";
|
|
||||||
RNW <= '1';
|
RNW <= '1';
|
||||||
DATA <= (others => 'U');
|
DATA <= (others => 'U');
|
||||||
wait until rising_edge(PHI0);
|
wait until rising_edge(PHI0);
|
||||||
@ -301,7 +285,7 @@ BEGIN
|
|||||||
wait until falling_edge(PHI0);
|
wait until falling_edge(PHI0);
|
||||||
wait for ADD_valid;
|
wait for ADD_valid;
|
||||||
ADD_LOW <= (others => '1');
|
ADD_LOW <= (others => '1');
|
||||||
ADD_HIGH <= (others => '1');
|
ADD_HIGH <= "1111";
|
||||||
RNW <= '1';
|
RNW <= '1';
|
||||||
DATA <= (others => 'U');
|
DATA <= (others => 'U');
|
||||||
wait until rising_edge(PHI0);
|
wait until rising_edge(PHI0);
|
||||||
@ -313,11 +297,11 @@ BEGIN
|
|||||||
ADD_LOW <= (others => 'U');
|
ADD_LOW <= (others => 'U');
|
||||||
ADD_HIGH <= (others => 'U');
|
ADD_HIGH <= (others => 'U');
|
||||||
|
|
||||||
-- read eprom high
|
-- read eprom high, deselected
|
||||||
wait until falling_edge(PHI0);
|
wait until falling_edge(PHI0);
|
||||||
wait for ADD_valid;
|
wait for ADD_valid;
|
||||||
ADD_LOW <= (others => '0');
|
ADD_LOW <= (others => '0');
|
||||||
ADD_HIGH <= "101";
|
ADD_HIGH <= "1101"; -- must become "101"
|
||||||
RNW <= '1';
|
RNW <= '1';
|
||||||
DATA <= (others => 'U');
|
DATA <= (others => 'U');
|
||||||
wait until rising_edge(PHI0);
|
wait until rising_edge(PHI0);
|
||||||
|
Loading…
Reference in New Issue
Block a user