forked from Apple-2-HW/AppleIISd
several fixes tried
This commit is contained in:
Florian Reitz
parent
c438775789
commit
d0a9254893
BIN
Datasheets/65SPI-B Datasheet V1.1.docx
Normal file
BIN
Datasheets/65SPI-B Datasheet V1.1.docx
Normal file
Binary file not shown.
@ -1,244 +1,275 @@
|
||||
VERSION 6
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BEGIN SCHEMATIC
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||||
BEGIN ATTR DeviceFamilyName "xc9500xl"
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DELETE all:0
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EDITNAME all:0
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EDITTRAIT all:0
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END ATTR
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BEGIN NETLIST
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||||
SIGNAL A10
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SIGNAL A9
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SIGNAL A8
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SIGNAL XLXN_10
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SIGNAL CLK
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SIGNAL XLXN_14
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SIGNAL B10
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SIGNAL B9
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SIGNAL B8
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SIGNAL NOE
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||||
SIGNAL XLXN_29
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SIGNAL NIO_SEL
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SIGNAL NIO_STB
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SIGNAL XLXN_38
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SIGNAL XLXN_46
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SIGNAL XLXN_47
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SIGNAL NDEV_SEL
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PORT Input A10
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PORT Input A9
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PORT Input A8
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PORT Input CLK
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PORT Output B10
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PORT Output B9
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PORT Output B8
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PORT Output NOE
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PORT Input NIO_SEL
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PORT Input NIO_STB
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PORT Input NDEV_SEL
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BEGIN BLOCKDEF fdrs
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||||
TIMESTAMP 2001 3 9 11 23 0
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LINE N 0 -128 64 -128
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LINE N 0 -256 64 -256
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LINE N 384 -256 320 -256
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LINE N 0 -32 64 -32
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||||
LINE N 0 -352 64 -352
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RECTANGLE N 64 -320 320 -64
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LINE N 192 -64 192 -32
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LINE N 192 -32 64 -32
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LINE N 64 -112 80 -128
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LINE N 80 -128 64 -144
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LINE N 192 -320 192 -352
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LINE N 192 -352 64 -352
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END BLOCKDEF
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BEGIN BLOCKDEF inv
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||||
TIMESTAMP 2001 3 9 11 23 50
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LINE N 0 -32 64 -32
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LINE N 224 -32 160 -32
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LINE N 64 -64 128 -32
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LINE N 128 -32 64 0
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LINE N 64 0 64 -64
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CIRCLE N 128 -48 160 -16
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END BLOCKDEF
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BEGIN BLOCKDEF vcc
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TIMESTAMP 2001 3 9 11 23 11
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LINE N 96 -64 32 -64
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LINE N 64 0 64 -32
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LINE N 64 -32 64 -64
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END BLOCKDEF
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BEGIN BLOCKDEF and2
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TIMESTAMP 2001 5 11 10 41 37
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LINE N 0 -64 64 -64
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||||
LINE N 0 -128 64 -128
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||||
LINE N 256 -96 192 -96
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ARC N 96 -144 192 -48 144 -48 144 -144
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LINE N 144 -48 64 -48
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LINE N 64 -144 144 -144
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LINE N 64 -48 64 -144
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END BLOCKDEF
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BEGIN BLOCKDEF and4
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TIMESTAMP 2001 5 11 10 43 14
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LINE N 144 -112 64 -112
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ARC N 96 -208 192 -112 144 -112 144 -208
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LINE N 64 -208 144 -208
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LINE N 64 -64 64 -256
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||||
LINE N 256 -160 192 -160
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LINE N 0 -256 64 -256
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LINE N 0 -192 64 -192
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LINE N 0 -128 64 -128
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LINE N 0 -64 64 -64
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END BLOCKDEF
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BEGIN BLOCKDEF nand2
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TIMESTAMP 2001 3 9 11 23 50
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LINE N 0 -64 64 -64
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LINE N 0 -128 64 -128
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LINE N 256 -96 216 -96
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CIRCLE N 192 -108 216 -84
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LINE N 64 -48 64 -144
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LINE N 64 -144 144 -144
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LINE N 144 -48 64 -48
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ARC N 96 -144 192 -48 144 -48 144 -144
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END BLOCKDEF
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BEGIN BLOCK XLXI_16 fdrs
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PIN C CLK
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PIN D XLXN_14
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PIN R XLXN_10
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PIN S XLXN_46
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PIN Q XLXN_47
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END BLOCK
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BEGIN BLOCK XLXI_17 vcc
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PIN P XLXN_14
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END BLOCK
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BEGIN BLOCK XLXI_18 and2
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PIN I0 A10
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PIN I1 XLXN_38
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PIN O B10
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END BLOCK
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BEGIN BLOCK XLXI_19 and2
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PIN I0 A9
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PIN I1 XLXN_38
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PIN O B9
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END BLOCK
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BEGIN BLOCK XLXI_20 and2
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PIN I0 A8
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PIN I1 XLXN_38
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PIN O B8
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END BLOCK
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BEGIN BLOCK XLXI_22 inv
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PIN I NIO_SEL
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PIN O XLXN_46
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END BLOCK
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BEGIN BLOCK XLXI_30 and4
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PIN I0 A8
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PIN I1 A9
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PIN I2 A10
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PIN I3 XLXN_38
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PIN O XLXN_10
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END BLOCK
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BEGIN BLOCK XLXI_31 inv
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PIN I NIO_STB
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PIN O XLXN_38
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END BLOCK
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BEGIN BLOCK XLXI_32 nand2
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PIN I0 XLXN_47
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PIN I1 NDEV_SEL
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PIN O NOE
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END BLOCK
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END NETLIST
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BEGIN SHEET 1 3520 2720
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BEGIN BRANCH A10
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WIRE 320 704 592 704
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WIRE 592 704 704 704
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WIRE 592 704 592 992
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WIRE 592 992 1088 992
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END BRANCH
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BEGIN BRANCH A9
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WIRE 320 768 528 768
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WIRE 528 768 704 768
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WIRE 528 768 528 1136
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WIRE 528 1136 1088 1136
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END BRANCH
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BEGIN BRANCH A8
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WIRE 320 832 464 832
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WIRE 464 832 704 832
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WIRE 464 832 464 1280
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WIRE 464 1280 1088 1280
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END BRANCH
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IOMARKER 320 704 A10 R180 28
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IOMARKER 320 768 A9 R180 28
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IOMARKER 320 832 A8 R180 28
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BEGIN BRANCH CLK
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WIRE 320 576 912 576
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WIRE 912 576 912 640
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WIRE 912 640 992 640
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END BRANCH
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BEGIN BRANCH B10
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WIRE 1344 960 1360 960
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WIRE 1360 960 1664 960
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END BRANCH
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BEGIN BRANCH B9
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WIRE 1344 1104 1360 1104
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WIRE 1360 1104 1664 1104
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END BRANCH
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BEGIN BRANCH B8
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WIRE 1344 1248 1360 1248
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WIRE 1360 1248 1664 1248
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END BRANCH
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BEGIN BRANCH NOE
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WIRE 1680 336 1696 336
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END BRANCH
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BEGIN BRANCH NIO_SEL
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WIRE 320 368 352 368
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END BRANCH
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BEGIN BRANCH NIO_STB
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WIRE 320 640 336 640
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END BRANCH
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IOMARKER 320 368 NIO_SEL R180 28
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IOMARKER 320 640 NIO_STB R180 28
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INSTANCE XLXI_31 336 672 R0
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BEGIN BRANCH XLXN_38
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WIRE 560 640 672 640
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WIRE 672 640 704 640
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WIRE 672 640 672 928
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WIRE 672 928 1088 928
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WIRE 672 928 672 1072
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WIRE 672 1072 1088 1072
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WIRE 672 1072 672 1216
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WIRE 672 1216 1088 1216
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END BRANCH
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INSTANCE XLXI_30 704 896 R0
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BEGIN BRANCH XLXN_10
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WIRE 960 736 976 736
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WIRE 976 736 992 736
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END BRANCH
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BEGIN BRANCH XLXN_14
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WIRE 848 496 848 512
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WIRE 848 512 992 512
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END BRANCH
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IOMARKER 320 576 CLK R180 28
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INSTANCE XLXI_17 784 496 R0
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INSTANCE XLXI_22 352 400 R0
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BEGIN BRANCH XLXN_46
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WIRE 576 368 592 368
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WIRE 592 368 992 368
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WIRE 992 368 992 416
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END BRANCH
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||||
INSTANCE XLXI_16 992 768 R0
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INSTANCE XLXI_18 1088 1056 R0
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INSTANCE XLXI_19 1088 1200 R0
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INSTANCE XLXI_20 1088 1344 R0
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IOMARKER 1664 960 B10 R0 28
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IOMARKER 1664 1104 B9 R0 28
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IOMARKER 1664 1248 B8 R0 28
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INSTANCE XLXI_32 1424 432 R0
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BEGIN BRANCH XLXN_47
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WIRE 1376 512 1392 512
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WIRE 1392 368 1424 368
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WIRE 1392 368 1392 512
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END BRANCH
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IOMARKER 1696 336 NOE R0 28
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BEGIN BRANCH NDEV_SEL
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WIRE 320 304 1408 304
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WIRE 1408 304 1424 304
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END BRANCH
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IOMARKER 320 304 NDEV_SEL R180 28
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END SHEET
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END SCHEMATIC
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<?xml version="1.0" encoding="UTF-8"?>
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<drawing version="7">
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<attr value="xc9500xl" name="DeviceFamilyName">
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<trait delete="all:0" />
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||||
<trait editname="all:0" />
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<trait edittrait="all:0" />
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</attr>
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<netlist>
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<signal name="A10" />
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<signal name="A9" />
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<signal name="A8" />
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<signal name="XLXN_10" />
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<signal name="CLK" />
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<signal name="XLXN_14" />
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<signal name="B10" />
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<signal name="B9" />
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<signal name="B8" />
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<signal name="NIO_SEL" />
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<signal name="NIO_STB" />
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<signal name="XLXN_38" />
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<signal name="XLXN_46" />
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||||
<signal name="XLXN_47" />
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<signal name="NDEV_SEL" />
|
||||
<signal name="NOE" />
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||||
<signal name="XLXN_53" />
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||||
<signal name="RNW" />
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||||
<signal name="XLXN_55" />
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||||
<port polarity="Input" name="A10" />
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<port polarity="Input" name="A9" />
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||||
<port polarity="Input" name="A8" />
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<port polarity="Input" name="CLK" />
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<port polarity="Output" name="B10" />
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<port polarity="Output" name="B9" />
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||||
<port polarity="Output" name="B8" />
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||||
<port polarity="Input" name="NIO_SEL" />
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||||
<port polarity="Input" name="NIO_STB" />
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||||
<port polarity="Input" name="NDEV_SEL" />
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||||
<port polarity="Output" name="NOE" />
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||||
<port polarity="Input" name="RNW" />
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||||
<blockdef name="fdrs">
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||||
<timestamp>2001-3-9T11:23:0</timestamp>
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="64" y1="-256" y2="-256" x1="0" />
|
||||
<line x2="320" y1="-256" y2="-256" x1="384" />
|
||||
<line x2="64" y1="-32" y2="-32" x1="0" />
|
||||
<line x2="64" y1="-352" y2="-352" x1="0" />
|
||||
<rect width="256" x="64" y="-320" height="256" />
|
||||
<line x2="192" y1="-64" y2="-32" x1="192" />
|
||||
<line x2="64" y1="-32" y2="-32" x1="192" />
|
||||
<line x2="80" y1="-112" y2="-128" x1="64" />
|
||||
<line x2="64" y1="-128" y2="-144" x1="80" />
|
||||
<line x2="192" y1="-320" y2="-352" x1="192" />
|
||||
<line x2="64" y1="-352" y2="-352" x1="192" />
|
||||
</blockdef>
|
||||
<blockdef name="inv">
|
||||
<timestamp>2001-3-9T11:23:50</timestamp>
|
||||
<line x2="64" y1="-32" y2="-32" x1="0" />
|
||||
<line x2="160" y1="-32" y2="-32" x1="224" />
|
||||
<line x2="128" y1="-64" y2="-32" x1="64" />
|
||||
<line x2="64" y1="-32" y2="0" x1="128" />
|
||||
<line x2="64" y1="0" y2="-64" x1="64" />
|
||||
<circle r="16" cx="144" cy="-32" />
|
||||
</blockdef>
|
||||
<blockdef name="vcc">
|
||||
<timestamp>2001-3-9T11:23:11</timestamp>
|
||||
<line x2="32" y1="-64" y2="-64" x1="96" />
|
||||
<line x2="64" y1="0" y2="-32" x1="64" />
|
||||
<line x2="64" y1="-32" y2="-64" x1="64" />
|
||||
</blockdef>
|
||||
<blockdef name="and2">
|
||||
<timestamp>2001-5-11T10:41:37</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="192" y1="-96" y2="-96" x1="256" />
|
||||
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
|
||||
<line x2="64" y1="-48" y2="-48" x1="144" />
|
||||
<line x2="144" y1="-144" y2="-144" x1="64" />
|
||||
<line x2="64" y1="-48" y2="-144" x1="64" />
|
||||
</blockdef>
|
||||
<blockdef name="and4">
|
||||
<timestamp>2001-5-11T10:43:14</timestamp>
|
||||
<line x2="64" y1="-112" y2="-112" x1="144" />
|
||||
<arc ex="144" ey="-208" sx="144" sy="-112" r="48" cx="144" cy="-160" />
|
||||
<line x2="144" y1="-208" y2="-208" x1="64" />
|
||||
<line x2="64" y1="-64" y2="-256" x1="64" />
|
||||
<line x2="192" y1="-160" y2="-160" x1="256" />
|
||||
<line x2="64" y1="-256" y2="-256" x1="0" />
|
||||
<line x2="64" y1="-192" y2="-192" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
</blockdef>
|
||||
<blockdef name="nand2">
|
||||
<timestamp>2001-3-9T11:23:50</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="216" y1="-96" y2="-96" x1="256" />
|
||||
<circle r="12" cx="204" cy="-96" />
|
||||
<line x2="64" y1="-48" y2="-144" x1="64" />
|
||||
<line x2="144" y1="-144" y2="-144" x1="64" />
|
||||
<line x2="64" y1="-48" y2="-48" x1="144" />
|
||||
<arc ex="144" ey="-144" sx="144" sy="-48" r="48" cx="144" cy="-96" />
|
||||
</blockdef>
|
||||
<blockdef name="or2">
|
||||
<timestamp>2000-1-1T10:10:10</timestamp>
|
||||
<line x2="64" y1="-64" y2="-64" x1="0" />
|
||||
<line x2="64" y1="-128" y2="-128" x1="0" />
|
||||
<line x2="192" y1="-96" y2="-96" x1="256" />
|
||||
<arc ex="192" ey="-96" sx="112" sy="-48" r="88" cx="116" cy="-136" />
|
||||
<arc ex="48" ey="-144" sx="48" sy="-48" r="56" cx="16" cy="-96" />
|
||||
<line x2="48" y1="-144" y2="-144" x1="112" />
|
||||
<arc ex="112" ey="-144" sx="192" sy="-96" r="88" cx="116" cy="-56" />
|
||||
<line x2="48" y1="-48" y2="-48" x1="112" />
|
||||
</blockdef>
|
||||
<block symbolname="fdrs" name="XLXI_16">
|
||||
<blockpin signalname="CLK" name="C" />
|
||||
<blockpin signalname="XLXN_14" name="D" />
|
||||
<blockpin signalname="XLXN_10" name="R" />
|
||||
<blockpin signalname="XLXN_46" name="S" />
|
||||
<blockpin signalname="XLXN_47" name="Q" />
|
||||
</block>
|
||||
<block symbolname="vcc" name="XLXI_17">
|
||||
<blockpin signalname="XLXN_14" name="P" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_18">
|
||||
<blockpin signalname="A10" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B10" name="O" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_19">
|
||||
<blockpin signalname="A9" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B9" name="O" />
|
||||
</block>
|
||||
<block symbolname="and2" name="XLXI_20">
|
||||
<blockpin signalname="A8" name="I0" />
|
||||
<blockpin signalname="XLXN_38" name="I1" />
|
||||
<blockpin signalname="B8" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_22">
|
||||
<blockpin signalname="NIO_SEL" name="I" />
|
||||
<blockpin signalname="XLXN_46" name="O" />
|
||||
</block>
|
||||
<block symbolname="and4" name="XLXI_30">
|
||||
<blockpin signalname="A8" name="I0" />
|
||||
<blockpin signalname="A9" name="I1" />
|
||||
<blockpin signalname="A10" name="I2" />
|
||||
<blockpin signalname="XLXN_38" name="I3" />
|
||||
<blockpin signalname="XLXN_10" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_31">
|
||||
<blockpin signalname="NIO_STB" name="I" />
|
||||
<blockpin signalname="XLXN_38" name="O" />
|
||||
</block>
|
||||
<block symbolname="nand2" name="XLXI_32">
|
||||
<blockpin signalname="XLXN_47" name="I0" />
|
||||
<blockpin signalname="NDEV_SEL" name="I1" />
|
||||
<blockpin signalname="XLXN_55" name="O" />
|
||||
</block>
|
||||
<block symbolname="inv" name="XLXI_33">
|
||||
<blockpin signalname="RNW" name="I" />
|
||||
<blockpin signalname="XLXN_53" name="O" />
|
||||
</block>
|
||||
<block symbolname="or2" name="XLXI_34">
|
||||
<blockpin signalname="XLXN_55" name="I0" />
|
||||
<blockpin signalname="XLXN_53" name="I1" />
|
||||
<blockpin signalname="NOE" name="O" />
|
||||
</block>
|
||||
</netlist>
|
||||
<sheet sheetnum="1" width="3520" height="2720">
|
||||
<branch name="A10">
|
||||
<wire x2="592" y1="704" y2="704" x1="320" />
|
||||
<wire x2="704" y1="704" y2="704" x1="592" />
|
||||
<wire x2="592" y1="704" y2="992" x1="592" />
|
||||
<wire x2="1088" y1="992" y2="992" x1="592" />
|
||||
</branch>
|
||||
<branch name="A9">
|
||||
<wire x2="528" y1="768" y2="768" x1="320" />
|
||||
<wire x2="704" y1="768" y2="768" x1="528" />
|
||||
<wire x2="528" y1="768" y2="1136" x1="528" />
|
||||
<wire x2="1088" y1="1136" y2="1136" x1="528" />
|
||||
</branch>
|
||||
<branch name="A8">
|
||||
<wire x2="464" y1="832" y2="832" x1="320" />
|
||||
<wire x2="704" y1="832" y2="832" x1="464" />
|
||||
<wire x2="464" y1="832" y2="1280" x1="464" />
|
||||
<wire x2="1088" y1="1280" y2="1280" x1="464" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="704" name="A10" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="768" name="A9" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="832" name="A8" orien="R180" />
|
||||
<branch name="CLK">
|
||||
<wire x2="912" y1="576" y2="576" x1="320" />
|
||||
<wire x2="912" y1="576" y2="640" x1="912" />
|
||||
<wire x2="992" y1="640" y2="640" x1="912" />
|
||||
</branch>
|
||||
<branch name="B10">
|
||||
<wire x2="1664" y1="960" y2="960" x1="1344" />
|
||||
</branch>
|
||||
<branch name="B9">
|
||||
<wire x2="1664" y1="1104" y2="1104" x1="1344" />
|
||||
</branch>
|
||||
<branch name="B8">
|
||||
<wire x2="1664" y1="1248" y2="1248" x1="1344" />
|
||||
</branch>
|
||||
<branch name="NIO_SEL">
|
||||
<wire x2="352" y1="368" y2="368" x1="320" />
|
||||
</branch>
|
||||
<branch name="NIO_STB">
|
||||
<wire x2="336" y1="640" y2="640" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="368" name="NIO_SEL" orien="R180" />
|
||||
<iomarker fontsize="28" x="320" y="640" name="NIO_STB" orien="R180" />
|
||||
<instance x="336" y="672" name="XLXI_31" orien="R0" />
|
||||
<branch name="XLXN_38">
|
||||
<wire x2="672" y1="640" y2="640" x1="560" />
|
||||
<wire x2="704" y1="640" y2="640" x1="672" />
|
||||
<wire x2="672" y1="640" y2="928" x1="672" />
|
||||
<wire x2="1088" y1="928" y2="928" x1="672" />
|
||||
<wire x2="672" y1="928" y2="1072" x1="672" />
|
||||
<wire x2="1088" y1="1072" y2="1072" x1="672" />
|
||||
<wire x2="672" y1="1072" y2="1216" x1="672" />
|
||||
<wire x2="1088" y1="1216" y2="1216" x1="672" />
|
||||
</branch>
|
||||
<instance x="704" y="896" name="XLXI_30" orien="R0" />
|
||||
<branch name="XLXN_10">
|
||||
<wire x2="992" y1="736" y2="736" x1="960" />
|
||||
</branch>
|
||||
<branch name="XLXN_14">
|
||||
<wire x2="848" y1="496" y2="512" x1="848" />
|
||||
<wire x2="992" y1="512" y2="512" x1="848" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="576" name="CLK" orien="R180" />
|
||||
<instance x="784" y="496" name="XLXI_17" orien="R0" />
|
||||
<instance x="352" y="400" name="XLXI_22" orien="R0" />
|
||||
<branch name="XLXN_46">
|
||||
<wire x2="992" y1="368" y2="368" x1="576" />
|
||||
<wire x2="992" y1="368" y2="416" x1="992" />
|
||||
</branch>
|
||||
<instance x="992" y="768" name="XLXI_16" orien="R0" />
|
||||
<instance x="1088" y="1056" name="XLXI_18" orien="R0" />
|
||||
<instance x="1088" y="1200" name="XLXI_19" orien="R0" />
|
||||
<instance x="1088" y="1344" name="XLXI_20" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="960" name="B10" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="1104" name="B9" orien="R0" />
|
||||
<iomarker fontsize="28" x="1664" y="1248" name="B8" orien="R0" />
|
||||
<instance x="1424" y="432" name="XLXI_32" orien="R0" />
|
||||
<branch name="XLXN_47">
|
||||
<wire x2="1392" y1="512" y2="512" x1="1376" />
|
||||
<wire x2="1424" y1="368" y2="368" x1="1392" />
|
||||
<wire x2="1392" y1="368" y2="512" x1="1392" />
|
||||
</branch>
|
||||
<branch name="NDEV_SEL">
|
||||
<wire x2="1424" y1="304" y2="304" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="304" name="NDEV_SEL" orien="R180" />
|
||||
<instance x="352" y="272" name="XLXI_33" orien="R0" />
|
||||
<branch name="NOE">
|
||||
<wire x2="2016" y1="272" y2="272" x1="2000" />
|
||||
</branch>
|
||||
<branch name="XLXN_53">
|
||||
<wire x2="1744" y1="240" y2="240" x1="576" />
|
||||
</branch>
|
||||
<branch name="RNW">
|
||||
<wire x2="352" y1="240" y2="240" x1="320" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="320" y="240" name="RNW" orien="R180" />
|
||||
<instance x="1744" y="368" name="XLXI_34" orien="R0" />
|
||||
<branch name="XLXN_55">
|
||||
<wire x2="1696" y1="336" y2="336" x1="1680" />
|
||||
<wire x2="1744" y1="304" y2="304" x1="1696" />
|
||||
<wire x2="1696" y1="304" y2="336" x1="1696" />
|
||||
</branch>
|
||||
<iomarker fontsize="28" x="2016" y="272" name="NOE" orien="R0" />
|
||||
</sheet>
|
||||
</drawing>
|
||||
1012
VHDL/AppleIISd.jed
1012
VHDL/AppleIISd.jed
File diff suppressed because it is too large
Load Diff
@ -18,14 +18,14 @@ NET "data<4>" LOC = "P7" ;
|
||||
NET "data<5>" LOC = "P9" ;
|
||||
NET "data<6>" LOC = "P11" ;
|
||||
NET "data<7>" LOC = "P13" ;
|
||||
NET "extclk" LOC = "P43" ;
|
||||
NET "clk_7m" LOC = "P43" ;
|
||||
NET "led" LOC = "P29" ;
|
||||
NET "ndev_sel" LOC = "P24" ;
|
||||
NET "ng" LOC = "P12" ;
|
||||
NET "nio_sel" LOC = "P14" ;
|
||||
NET "nio_stb" LOC = "P42" ;
|
||||
NET "noe" LOC = "P25" ;
|
||||
NET "nphi2" LOC = "P8" ;
|
||||
NET "clk_phi0" LOC = "P8" ;
|
||||
NET "nreset" LOC = "P20" ;
|
||||
NET "nrw" LOC = "P1" ;
|
||||
NET "spi_miso" LOC = "P40" ;
|
||||
|
||||
@ -38,12 +38,11 @@ entity AppleIISd is
|
||||
Port (
|
||||
data : inout STD_LOGIC_VECTOR (7 downto 0);
|
||||
nrw : in STD_LOGIC;
|
||||
nirq : out STD_LOGIC;
|
||||
nreset : in STD_LOGIC;
|
||||
addr : in STD_LOGIC_VECTOR (1 downto 0);
|
||||
nphi2 : in STD_LOGIC;
|
||||
clk_phi0 : in STD_LOGIC;
|
||||
ndev_sel : in STD_LOGIC;
|
||||
extclk : in STD_LOGIC;
|
||||
clk_7m : in STD_LOGIC;
|
||||
spi_miso: in std_logic;
|
||||
spi_mosi : out STD_LOGIC;
|
||||
spi_sclk : out STD_LOGIC;
|
||||
@ -73,7 +72,6 @@ architecture Behavioral of AppleIISd is
|
||||
-- interface signals
|
||||
signal selected: std_logic;
|
||||
signal reset: std_logic;
|
||||
signal int_out: std_logic;
|
||||
signal is_read: std_logic;
|
||||
signal int_din: std_logic_vector (7 downto 0);
|
||||
signal int_dout: std_logic_vector (7 downto 0);
|
||||
@ -86,16 +84,11 @@ architecture Behavioral of AppleIISd is
|
||||
-- internal state
|
||||
signal spidatain: std_logic_vector (7 downto 0);
|
||||
signal spidataout: std_logic_vector (7 downto 0);
|
||||
signal spiint: std_logic; -- spi interrupt state
|
||||
signal inited: std_logic; -- card initialized
|
||||
signal inited_set: std_logic;
|
||||
signal inited_reset: std_logic;
|
||||
signal inited_int: std_logic;
|
||||
signal inited_intff: std_logic;
|
||||
|
||||
-- spi register flags
|
||||
signal tc: std_logic; -- transmission complete; cleared on spi data read
|
||||
signal ier: std_logic; -- enable general SPI interrupts
|
||||
signal bsy: std_logic; -- SPI busy
|
||||
signal frx: std_logic; -- fast receive mode
|
||||
signal tmo: std_logic; -- tri-state mosi
|
||||
@ -104,9 +97,7 @@ architecture Behavioral of AppleIISd is
|
||||
signal cpha: std_logic; -- shift clock phase; 0=leading edge, 1=rising edge
|
||||
|
||||
signal divisor: std_logic_vector(DIV_WIDTH-1 downto 0);
|
||||
|
||||
signal slavesel: std_logic; -- slave select output (0=selected)
|
||||
signal slaveinten: std_logic; -- slave interrupt enable (1=enabled)
|
||||
|
||||
--------------------------
|
||||
-- helper signals
|
||||
@ -118,7 +109,7 @@ architecture Behavioral of AppleIISd is
|
||||
signal shiftcnt: std_logic_vector(3 downto 0); -- shift counter (5 bit)
|
||||
|
||||
-- spi clock
|
||||
signal clksrc: std_logic; -- clock source (phi2 or extclk)
|
||||
signal clksrc: std_logic; -- clock source (phi2 or clk_7m)
|
||||
-- TODO divcnt is not used at all??
|
||||
signal divcnt: std_logic_vector(DIV_WIDTH-1 downto 0); -- divisor counter
|
||||
signal shiftclk : std_logic;
|
||||
@ -132,6 +123,7 @@ architecture Behavioral of AppleIISd is
|
||||
NDEV_SEL : in std_logic;
|
||||
NIO_SEL : in std_logic;
|
||||
NIO_STB : in std_logic;
|
||||
RNW : in std_logic;
|
||||
B8 : out std_logic;
|
||||
B9 : out std_logic;
|
||||
B10 : out std_logic;
|
||||
@ -139,44 +131,36 @@ architecture Behavioral of AppleIISd is
|
||||
);
|
||||
end component;
|
||||
|
||||
component SR_Latch
|
||||
port (
|
||||
S,R : in std_logic;
|
||||
Q, Q_n : inout std_logic;
|
||||
Reset : in std_logic;
|
||||
Clk : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
begin
|
||||
add_dec : AddressDecoder
|
||||
port map (
|
||||
A8 => a8,
|
||||
A9 => a9,
|
||||
A10 => a10,
|
||||
CLK => extclk,
|
||||
CLK => clk_7m,
|
||||
NDEV_SEL => ndev_sel,
|
||||
NIO_SEL => nio_sel,
|
||||
NIO_STB => nio_stb,
|
||||
RNW => nrw,
|
||||
B8 => b8,
|
||||
B9 => b9,
|
||||
B10 => b10,
|
||||
NOE => noe);
|
||||
|
||||
sr_inited : SR_Latch
|
||||
port map (
|
||||
S => inited_set,
|
||||
R => inited_reset,
|
||||
Q => inited,
|
||||
Q_n => open,
|
||||
Reset => reset,
|
||||
Clk => extclk);
|
||||
|
||||
led <= not (bsy or not slavesel);
|
||||
led <= not (inited_set);
|
||||
--led <= not (bsy or not slavesel);
|
||||
ng <= ndev_sel and nio_sel and nio_stb;
|
||||
inited_reset <= card;
|
||||
bsy <= start_shifting or shifting2;
|
||||
|
||||
process(clk_7m, reset, card, inited_set)
|
||||
begin
|
||||
if(reset = '1' or card = '1') then
|
||||
inited <= '0';
|
||||
elsif rising_edge(inited_set) then
|
||||
inited <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
process(start_shifting, shiftdone, shiftclk)
|
||||
begin
|
||||
if (rising_edge(shiftclk)) then
|
||||
@ -275,7 +259,7 @@ begin
|
||||
--------------------------
|
||||
-- spiclk - spi clock generation
|
||||
-- spiclk is still 2 times the freq. than sclk
|
||||
clksrc <= nphi2 when (ece = '0') else extclk;
|
||||
clksrc <= clk_phi0 when (ece = '0') else clk_7m;
|
||||
|
||||
-- is a pulse signal to allow for divisor==0
|
||||
--shiftclk <= clksrc when divcnt = "000000" else '0';
|
||||
@ -294,26 +278,29 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- interrupt generation
|
||||
int_out <= spiint and slaveinten;
|
||||
|
||||
--------------------------
|
||||
-- interface section
|
||||
-- inputs
|
||||
reset <= not (nreset);
|
||||
selected <= not(ndev_sel);
|
||||
is_read <= selected and nphi2 and nrw;
|
||||
int_din <= data;
|
||||
|
||||
int_din <= data;
|
||||
int_miso <= (spi_miso and not slavesel);
|
||||
|
||||
process(selected, clk_7m)
|
||||
begin
|
||||
if(selected = '0') then
|
||||
is_read <= '0';
|
||||
elsif(rising_edge(clk_7m) and selected = '1' and clk_phi0 = '1' and nrw = '1') then
|
||||
is_read <= '1';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
-- outputs
|
||||
data <= int_dout when (is_read='1') else (others => 'Z'); -- data bus tristate
|
||||
nirq <= '0' when (int_out='1') else 'Z'; -- wired-or
|
||||
spi_sclk <= int_sclk;
|
||||
spi_mosi <= int_mosi when tmo='0' else 'Z'; -- mosi tri-state
|
||||
spi_Nsel <= slavesel;
|
||||
|
||||
|
||||
tc_proc: process (selected, shiftdone)
|
||||
begin
|
||||
@ -324,29 +311,12 @@ begin
|
||||
end if;
|
||||
end process;
|
||||
|
||||
spiint <= tc and ier;
|
||||
|
||||
|
||||
-- inited_set pulse
|
||||
process(extclk, reset)
|
||||
begin
|
||||
if(reset = '1') then
|
||||
inited_set <= '0';
|
||||
elsif falling_edge(extclk) then
|
||||
inited_intff <= inited_int; -- one cycle delayed version
|
||||
inited_set <= '0'; -- default value
|
||||
if (inited_int = '1') and (inited_intff = '0') then
|
||||
inited_set <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--------------------------
|
||||
-- cpu register section
|
||||
-- cpu read
|
||||
cpu_read: process (is_read, addr,
|
||||
spidatain, tc, ier, bsy, frx, tmo, ece, cpol, cpha, divisor,
|
||||
slavesel, slaveinten, wp, card, inited)
|
||||
spidatain, tc, bsy, frx, tmo, ece, cpol, cpha, divisor,
|
||||
slavesel, wp, card, inited)
|
||||
begin
|
||||
if (is_read = '1') then
|
||||
case addr is
|
||||
@ -359,15 +329,14 @@ begin
|
||||
int_dout(3) <= tmo;
|
||||
int_dout(4) <= frx;
|
||||
int_dout(5) <= bsy;
|
||||
int_dout(6) <= ier;
|
||||
int_dout(6) <= '0';
|
||||
int_dout(7) <= tc;
|
||||
when "10" => -- read sclk divisor
|
||||
int_dout(DIV_WIDTH-1 downto 0) <= divisor;
|
||||
int_dout(7 downto 3) <= (others => '0');
|
||||
when "11" => -- read slave select / slave interrupt state
|
||||
int_dout(0) <= slavesel;
|
||||
int_dout(3 downto 1) <= (others => '0');
|
||||
int_dout(4) <= slaveinten;
|
||||
int_dout(4 downto 1) <= (others => '0');
|
||||
int_dout(5) <= wp;
|
||||
int_dout(6) <= card;
|
||||
int_dout(7) <= inited;
|
||||
@ -380,7 +349,7 @@ begin
|
||||
end process;
|
||||
|
||||
-- cpu write
|
||||
cpu_write: process(reset, selected, nrw, addr, int_din)
|
||||
cpu_write: process(reset, selected, nrw, addr, int_din, card, inited)
|
||||
begin
|
||||
if (reset = '1') then
|
||||
cpha <= '0';
|
||||
@ -388,11 +357,12 @@ begin
|
||||
ece <= '0';
|
||||
tmo <= '0';
|
||||
frx <= '0';
|
||||
ier <= '0';
|
||||
slavesel <= '1';
|
||||
slaveinten <= '0';
|
||||
divisor <= (others => '0');
|
||||
spidataout <= (others => '1');
|
||||
inited_set <= '0';
|
||||
elsif (card = '1') then
|
||||
inited_set <= '0';
|
||||
elsif (falling_edge(selected) and nrw = '0') then
|
||||
case addr is
|
||||
when "00" => -- write SPI data out (see other process above)
|
||||
@ -403,15 +373,13 @@ begin
|
||||
ece <= int_din(2);
|
||||
tmo <= int_din(3);
|
||||
frx <= int_din(4);
|
||||
-- no bit 5
|
||||
ier <= int_din(6);
|
||||
-- no bit 7;
|
||||
-- no bit 5 - 7
|
||||
when "10" => -- write divisor
|
||||
divisor <= int_din(DIV_WIDTH-1 downto 0);
|
||||
when "11" => -- write slave select / slave interrupt enable
|
||||
slavesel <= int_din(0);
|
||||
slaveinten <= int_din(4);
|
||||
inited_int <= int_din(7);
|
||||
-- no bit 1 - 6
|
||||
inited_set <= int_din(7);
|
||||
when others =>
|
||||
end case;
|
||||
end if;
|
||||
|
||||
@ -17,19 +17,15 @@
|
||||
<files>
|
||||
<file xil_pn:name="AppleIISd.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="AddressDecoder.sch" xil_pn:type="FILE_SCHEMATIC">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="AppleIISd.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
<file xil_pn:name="sr_latch.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="40"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
@ -59,6 +55,7 @@
|
||||
<property xil_pn:name="Device" xil_pn:value="xc9572xl" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="XC9500XL CPLDs" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exhaustive Fit Mode" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -127,6 +124,7 @@
|
||||
<property xil_pn:name="Preserve Unused Inputs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
@ -138,7 +136,8 @@
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SR_Latch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SR_Latch" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@ -148,7 +147,7 @@
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SR_Latch" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Fit" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-10" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
|
||||
@ -1,55 +0,0 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- Company:
|
||||
-- Engineer:
|
||||
--
|
||||
-- Create Date: 22:26:04 09/09/2017
|
||||
-- Design Name:
|
||||
-- Module Name: sr_latch - Behavioral
|
||||
-- Project Name:
|
||||
-- Target Devices:
|
||||
-- Tool versions:
|
||||
-- Description:
|
||||
--
|
||||
-- Dependencies:
|
||||
--
|
||||
-- Revision:
|
||||
-- Revision 0.01 - File Created
|
||||
-- Additional Comments:
|
||||
--
|
||||
----------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if using
|
||||
-- arithmetic functions with Signed or Unsigned values
|
||||
--use IEEE.NUMERIC_STD.ALL;
|
||||
|
||||
-- Uncomment the following library declaration if instantiating
|
||||
-- any Xilinx primitives in this code.
|
||||
--library UNISIM;
|
||||
--use UNISIM.VComponents.all;
|
||||
|
||||
|
||||
entity SR_Latch is
|
||||
Port ( S,R : in STD_LOGIC;
|
||||
Q : inout STD_LOGIC;
|
||||
Q_n : inout STD_LOGIC;
|
||||
Reset : in STD_LOGIC;
|
||||
Clk : in STD_LOGIC);
|
||||
end SR_Latch;
|
||||
|
||||
architecture SR_Latch_arch of SR_Latch is
|
||||
begin
|
||||
process (S,R,Q,Q_n, Reset, Clk)
|
||||
begin
|
||||
if(rising_edge(Clk)) then
|
||||
if(Reset = '1') then
|
||||
Q <= '0';
|
||||
Q_n <= '1';
|
||||
else
|
||||
Q <= R NOR Q_n;
|
||||
Q_n <= S NOR Q;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
end SR_Latch_arch;
|
||||
Loading…
Reference in New Issue
Block a user