forked from Apple-2-HW/AppleIISd
AddressDecoder testbench
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BIN
Images/AddessDecoder_Test.JPG
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Images/AddessDecoder_Test.JPG
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Images/AppleIISd_Test.JPG
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Images/AppleIISd_Test.JPG
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@ -54,7 +54,9 @@ begin
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DATA_EN <= RNW and not NDEV_SEL;
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DATA_EN <= RNW and not NDEV_SEL;
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NG <= NDEV_SEL and noe_int;
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NG <= NDEV_SEL and noe_int;
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NOE <= noe_int;
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NOE <= noe_int;
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noe_int <= not RNW or not NDEV_SEL or NIO_STB or ncs;
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noe_int <= not RNW or not NDEV_SEL
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or (NIO_SEL and NIO_STB)
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or (NIO_SEL and ncs);
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cfxx <= A(8) and A(9) and A(10) and not NIO_STB;
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cfxx <= A(8) and A(9) and A(10) and not NIO_STB;
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@ -1,79 +1,136 @@
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-- Vhdl test bench created from schematic U:\AppleIISd\VHDL\AddressDecoder.sch - Mon Oct 09 20:12:16 2017
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 23:42:22 10/10/2017
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-- Design Name:
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-- Module Name: C:/Git/AppleIISd/VHDL/AddressDecoder_Test.vhd
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-- Project Name: AppleIISd
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: AddressDecoder
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--
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-- Notes:
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-- Notes:
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-- 1) This testbench template has been automatically generated using types
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic and std_logic_vector for the ports of the unit under test.
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- Xilinx recommends that these types always be used for the top-level
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-- that these types always be used for the top-level I/O of a design in order
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-- I/O of a design in order to guarantee that the testbench will bind
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- correctly to the timing (post-route) simulation model.
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-- simulation model.
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-- 2) To use this template as your testbench, change the filename to any
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--------------------------------------------------------------------------------
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-- name of your choice with the extension .vhd, and use the "Source->Add"
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-- menu in Project Navigator to import the testbench. Then
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-- edit the user defined section below, adding code to generate the
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-- stimulus for your design.
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--
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LIBRARY ieee;
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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LIBRARY UNISIM;
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-- Uncomment the following library declaration if using
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USE UNISIM.Vcomponents.ALL;
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-- arithmetic functions with Signed or Unsigned values
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ENTITY AddressDecoder_AddressDecoder_sch_tb IS
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--USE ieee.numeric_std.ALL;
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END AddressDecoder_AddressDecoder_sch_tb;
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ARCHITECTURE behavioral OF AddressDecoder_AddressDecoder_sch_tb IS
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ENTITY AddressDecoder_Test IS
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END AddressDecoder_Test;
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ARCHITECTURE behavior OF AddressDecoder_Test IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT AddressDecoder
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COMPONENT AddressDecoder
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PORT( A10 : IN STD_LOGIC;
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PORT(
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A9 : IN STD_LOGIC;
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A : IN std_logic_vector(10 downto 8);
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A8 : IN STD_LOGIC;
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B : OUT std_logic_vector(10 downto 8);
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B10 : OUT STD_LOGIC;
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RNW : IN std_logic;
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B9 : OUT STD_LOGIC;
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NDEV_SEL : IN std_logic;
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B8 : OUT STD_LOGIC;
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NIO_SEL : IN std_logic;
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NIO_SEL : IN STD_LOGIC;
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NIO_STB : IN std_logic;
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NDEV_SEL : IN STD_LOGIC;
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NRESET : IN std_logic;
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NOE : OUT STD_LOGIC;
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DATA_EN : OUT std_logic;
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RNW : IN STD_LOGIC;
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NG : OUT std_logic;
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NG : OUT STD_LOGIC;
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NOE : OUT std_logic
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DATA_EN : OUT STD_LOGIC;
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);
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NIO_STB : IN STD_LOGIC);
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END COMPONENT;
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END COMPONENT;
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SIGNAL A10 : STD_LOGIC := '0';
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SIGNAL A9 : STD_LOGIC := '0';
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--Inputs
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SIGNAL A8 : STD_LOGIC := '0';
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signal A : std_logic_vector(10 downto 8) := "101";
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SIGNAL B10 : STD_LOGIC;
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signal RNW : std_logic := '1';
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SIGNAL B9 : STD_LOGIC;
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signal NDEV_SEL : std_logic := '1';
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SIGNAL B8 : STD_LOGIC;
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signal NIO_SEL : std_logic := '1';
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SIGNAL NIO_SEL : STD_LOGIC := '1';
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signal NIO_STB : std_logic := '1';
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SIGNAL NDEV_SEL : STD_LOGIC := '1';
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signal NRESET : std_logic := '1';
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SIGNAL NOE : STD_LOGIC;
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SIGNAL RNW : STD_LOGIC := '1';
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--Outputs
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SIGNAL NG : STD_LOGIC;
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signal B : std_logic_vector(10 downto 8);
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SIGNAL DATA_EN : STD_LOGIC;
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signal DATA_EN : std_logic;
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SIGNAL NIO_STB : STD_LOGIC := '1';
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signal NG : std_logic;
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signal NOE : std_logic;
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BEGIN
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BEGIN
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UUT: AddressDecoder PORT MAP(
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-- Instantiate the Unit Under Test (UUT)
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A10 => A10,
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uut: AddressDecoder PORT MAP (
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A9 => A9,
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A => A,
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A8 => A8,
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B => B,
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B10 => B10,
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B9 => B9,
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B8 => B8,
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NIO_SEL => NIO_SEL,
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NDEV_SEL => NDEV_SEL,
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NOE => NOE,
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RNW => RNW,
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RNW => RNW,
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NG => NG,
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NDEV_SEL => NDEV_SEL,
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NIO_SEL => NIO_SEL,
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NIO_STB => NIO_STB,
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NRESET => NRESET,
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DATA_EN => DATA_EN,
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DATA_EN => DATA_EN,
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NIO_STB => NIO_STB
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NG => NG,
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NOE => NOE
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);
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);
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-- *** Test Bench - User Defined Section ***
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tb : PROCESS
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-- Stimulus process
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BEGIN
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stim_proc: process
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WAIT; -- will wait forever
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begin
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END PROCESS;
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-- hold reset state for 100 ns.
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-- *** End Test Bench - User Defined Section ***
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wait for 50 ns;
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NRESET <= '0';
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wait for 50 ns;
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NRESET <= '1';
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wait for 50 ns;
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-- insert stimulus here
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-- CPLD access
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NDEV_SEL <= '0';
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wait for 10 ns;
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NDEV_SEL <= '1';
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wait for 20 ns;
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-- CnXX access
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NIO_SEL <= '0';
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wait for 10 ns;
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NIO_SEL <= '1';
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wait for 20 ns;
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-- C8xx access, selected
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NIO_STB <= '0';
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wait for 10 ns;
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NIO_STB <= '1';
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wait for 20 ns;
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-- CPLD access
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NDEV_SEL <= '0';
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wait for 10 ns;
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NDEV_SEL <= '1';
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wait for 20 ns;
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-- CFFF access
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A <= "111";
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NIO_STB <= '0';
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wait for 10 ns;
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A <= "000";
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NIO_STB <= '1';
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wait for 20 ns;
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-- C8xx access, unselected
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NIO_STB <= '0';
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wait for 10 ns;
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NIO_STB <= '1';
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wait for 20 ns;
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wait;
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end process;
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END;
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END;
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Binary file not shown.
1058
VHDL/AppleIISd.jed
1058
VHDL/AppleIISd.jed
File diff suppressed because it is too large
Load Diff
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@ -72,6 +72,7 @@ architecture Behavioral of AppleIISd is
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signal rnw_int : std_logic;
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signal rnw_int : std_logic;
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signal data_en : std_logic;
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signal data_en : std_logic;
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signal ndev_sel_int : std_logic;
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component SpiController is
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component SpiController is
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Port (
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Port (
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A => ADD_HIGH,
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A => ADD_HIGH,
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B => B,
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B => B,
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RNW => RNW,
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RNW => RNW,
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NDEV_SEL => NDEV_SEL,
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NDEV_SEL => ndev_sel_int,
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NIO_SEL => NIO_SEL,
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NIO_SEL => NIO_SEL,
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NIO_STB => NIO_STB,
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NIO_STB => NIO_STB,
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NRESET => NRESET,
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NRESET => NRESET,
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end if;
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end if;
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end process;
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end process;
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process(CLK, NRESET)
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begin
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if(NRESET = '0') then
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ndev_sel_int <= '1';
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elsif rising_edge(CLK) then
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ndev_sel_int <= NDEV_SEL;
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end if;
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end process;
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DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
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DATA <= data_out when (data_en = '1') else (others => 'Z'); -- data bus tristate
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-- synthesis translate_off
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-- synthesis translate_off
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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</file>
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<file xil_pn:name="AddressDecoder_Test.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="230"/>
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</file>
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</files>
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</files>
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<properties>
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<properties>
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