AppleIISd/VHDL/AppleIISd.ucf
2017-10-10 22:36:48 +02:00

44 lines
1.2 KiB
Plaintext

#PACE: Start of Constraints generated by PACE
NET "DATA<2>" BUFG = DATA_GATE ;
NET "DATA<3>" BUFG = DATA_GATE ;
NET "DATA<4>" BUFG = DATA_GATE ;
#PACE: Start of PACE I/O Pin Assignments
NET "ADD_HIGH<10>" LOC = "P38" ;
NET "ADD_HIGH<8>" LOC = "P36" ;
NET "ADD_HIGH<9>" LOC = "P37" ;
NET "ADD_LOW<0>" LOC = "P19" ;
NET "ADD_LOW<1>" LOC = "P18" ;
NET "B<10>" LOC = "P22" ;
NET "B<8>" LOC = "P26" ;
NET "B<9>" LOC = "P27" ;
NET "CARD" LOC = "P33" ;
NET "DATA<0>" LOC = "P3" ;
NET "DATA<1>" LOC = "P4" ;
NET "DATA<2>" LOC = "P5" ;
NET "DATA<3>" LOC = "P6" ;
NET "DATA<4>" LOC = "P7" ;
NET "DATA<5>" LOC = "P9" ;
NET "DATA<6>" LOC = "P11" ;
NET "DATA<7>" LOC = "P13" ;
NET "CLK" LOC = "P43" ;
NET "LED" LOC = "P29" ;
NET "NDEV_SEL" LOC = "P24" ;
NET "NG" LOC = "P12" ;
NET "NIO_SEL" LOC = "P14" ;
NET "NIO_STB" LOC = "P42" ;
NET "NOE" LOC = "P25" ;
NET "PHI0" LOC = "P8" ;
NET "NRESET" LOC = "P20" ;
NET "RNW" LOC = "P1" ;
NET "MISO" LOC = "P40" ;
NET "MOSI" LOC = "P35" ;
NET "NSEL" LOC = "P28" ;
NET "SCLK" LOC = "P34" ;
NET "WP" LOC = "P39" ;
#PACE: Start of PACE Area Constraints
#PACE: Start of PACE Prohibit Constraints
#PACE: End of Constraints generated by PACE