Synthesis and Ngdbuild Report synthesis: version Diamond (64-bit) 3.9.0.99.2 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved. Thu Feb 22 10:56:36 2018 Command Line: synthesis -f liron_fpgatop_lattice.synproj -gui -msgset C:/Users/chamberlin/Documents/Liron/lattice/promote.xml Synthesis options: The -a option is MachXO2. The -s option is 4. The -t option is TQFP100. The -d option is LCMXO2-1200HC. Using package TQFP100. Using performance grade 4. ########################################################## ### Lattice Family : MachXO2 ### Device : LCMXO2-1200HC ### Package : TQFP100 ### Speed : 4 ########################################################## INFO - synthesis: User-Selected Strategy Settings Optimization goal = Balanced Top-level module name = top. Target frequency = 1.000000 MHz. Maximum fanout = 1000. Timing path count = 3 BRAM utilization = 100.000000 % DSP usage = true DSP utilization = 100.000000 % fsm_encoding_style = auto resolve_mixed_drivers = 0 fix_gated_clocks = 1 Mux style = Auto Use Carry Chain = true carry_chain_length = 0 Loop Limit = 1950. Use IO Insertion = TRUE Use IO Reg = AUTO Resource Sharing = TRUE Propagate Constants = TRUE Remove Duplicate Registers = TRUE force_gsr = auto ROM style = auto RAM style = auto The -comp option is FALSE. The -syn option is FALSE. -p C:/Users/chamberlin/Documents/Liron/lattice (searchpath added) -p C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data (searchpath added) -p C:/Users/chamberlin/Documents/Liron/lattice/fpgatop (searchpath added) -p C:/Users/chamberlin/Documents/Liron/lattice (searchpath added) Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/top.v Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/addrDecoder.v Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/iwm.v Verilog design file = C:/Users/chamberlin/Documents/Liron/lattice/codeROM.v NGD file = liron_fpgatop.ngd -sdc option: SDC file input not used. -lpf option: Output file option is ON. Hardtimer checking is enabled (default). The -dt option is not used. The -r option is OFF. [ Remove LOC Properties is OFF. ] Technology check ok... Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Compile design. Compile Design Begin Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/top.v. VERI-1482 Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/addrdecoder.v. VERI-1482 Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/iwm.v. VERI-1482 Analyzing Verilog file c:/users/chamberlin/documents/liron/lattice/coderom.v. VERI-1482 Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482 Top module name (Verilog): top INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/top.v(2): compiling module top. VERI-1018 INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/addrdecoder.v(2): compiling module addrDecoder. VERI-1018 INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/iwm.v(2): compiling module iwm. VERI-1018 INFO - synthesis: c:/users/chamberlin/documents/liron/lattice/coderom.v(8): compiling module codeROM. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_1. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_2. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_3. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1120): compiling module VHI. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1124): compiling module VLO. VERI-1018 INFO - synthesis: C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1291): compiling module DP8KC_renamed_due_excessive_length_4. VERI-1018 Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'... Loading device for application map from file 'xo2c1200.nph' in environment: C:/lscc/diamond/3.9_x64/ispfpga. Package Status: Final Version 1.42. Top-level module name = top. ######## Converting I/O port _enbl2 to output. ######## Converting I/O port select to output. ######## Converting I/O port _en35 to output. ######## Missing driver on net spi_clk. Patching with GND. ######## Missing driver on net spi_mosi. Patching with GND. ######## Missing driver on net spi_cs. Patching with GND. GSR instance connected to net n440_c. Applying 1.000000 MHz constraint to all clocks WARNING - synthesis: No user .sdc file. Results of NGD DRC are available in top_drc.log. Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00a/data/xo2alib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/xo2c00/data/xo2clib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/mg5g00/data/mg5glib.ngl'... Loading NGL library 'C:/lscc/diamond/3.9_x64/ispfpga/or5g00/data/orc5glib.ngl'... All blocks are expanded and NGD expansion is successful. Writing NGD file liron_fpgatop.ngd. ################### Begin Area Report (top)###################### Number of register bits => 43 of 1520 (2 % ) BB => 8 DP8KC => 4 FD1P3AX => 29 FD1P3IX => 10 FD1P3JX => 1 FD1S3AX => 2 FD1S3AY => 1 GSR => 1 IB => 22 INV => 1 LUT4 => 115 OB => 19 OBZ => 3 PFUMX => 1 ################### End Area Report ################## ################### Begin BlackBox Report ###################### TSALL => 1 ################### End BlackBox Report ################## ################### Begin Clock Report ###################### Clock Nets Number of Clocks: 2 Net : fclk_c, loads : 39 Net : _devsel_c, loads : 6 Clock Enable Nets Number of Clock Enables: 17 Top 10 highest fanout Clock Enables: Net : myIwm/q7, loads : 21 Net : myIwm/fclk_c_enable_14, loads : 8 Net : myIwm/fclk_c_enable_26, loads : 7 Net : myIwm/fclk_c_enable_20, loads : 6 Net : myIwm/fclk_c_enable_30, loads : 4 Net : myIwm/fclk_c_enable_16, loads : 3 Net : myIwm/_devsel_N_40_enable_4, loads : 1 Net : myIwm/fclk_c_enable_27, loads : 1 Net : myIwm/_devsel_N_40_enable_5, loads : 1 Net : myIwm/_devsel_N_40_enable_1, loads : 1 Highest fanout non-clock nets Top 10 highest fanout non-clock nets: Net : myIwm/q7, loads : 21 Net : addr_c_0, loads : 17 Net : addr_c_3, loads : 13 Net : addr_c_2, loads : 13 Net : addr_c_1, loads : 13 Net : myIwm/q6, loads : 12 Net : myIwm/writeBufferEmpty, loads : 11 Net : myIwm/n142, loads : 11 Net : myIwm/n1871, loads : 11 Net : myIwm/bitTimer_3, loads : 10 ################### End Clock Report ################## Timing Report Summary -------------- -------------------------------------------------------------------------------- Constraint | Constraint| Actual|Levels -------------------------------------------------------------------------------- | | | create_clock -period 1000.000000 -name | | | clk1 [get_nets _devsel_c] | -| -| 0 | | | create_clock -period 1000.000000 -name | | | clk0 [get_nets fclk_c] | 1.000 MHz| 99.890 MHz| 5 | | | -------------------------------------------------------------------------------- All constraints were met. Peak Memory Usage: 53.680 MB -------------------------------------------------------------- Elapsed CPU time for LSE flow : 0.920 secs --------------------------------------------------------------