fpga-disk-controller/yellowstone_blink/hdla_gen_hierarchy.html
steve-chamberlin 31488767c7 initial commit
2019-01-30 12:55:46 -08:00

11 lines
5.7 KiB
HTML

<HTML> <HEAD><TITLE></TITLE> <STYLE TYPE="text/css"> <!-- body,pre{ font-family:'Courier New', monospace; color: #000000; font-size:88%; background-color: #ffffff; } h1 { font-weight: bold; margin-top: 24px; margin-bottom: 10px; border-bottom: 3px solid #000; font-size: 1em; } h2 { font-weight: bold; margin-top: 18px; margin-bottom: 5px; font-size: 0.90em; } h3 { font-weight: bold; margin-top: 12px; margin-bottom: 5px; font-size: 0.80em; } p { font-size:78%; } P.Table { margin-top: 4px; margin-bottom: 4px; margin-right: 4px; margin-left: 4px; } table { border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; border-collapse: collapse; } th { font-weight:bold; padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; text-align:left; font-size:78%; } td { padding: 4px; border-width: 1px 1px 1px 1px; border-style: solid solid solid solid; border-color: black black black black; vertical-align:top; font-size:78%; } a { color:#013C9A; text-decoration:none; } a:visited { color:#013C9A; } a:hover, a:active { text-decoration:underline; color:#5BAFD4; } .pass { background-color: #00ff00; } .fail { background-color: #ff0000; } .comment { font-size: 90%; font-style: italic; } --> </STYLE> </HEAD> <BODY> <PRE>Setting log file to 'C:/Users/chamberlin/Documents/Liron/yellowstone_blink/hdla_gen_hierarchy.html'.
Starting: parse design source files
(VERI-1482) Analyzing Verilog file C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v
(VERI-1482) Analyzing Verilog file C:/Users/chamberlin/Documents/Liron/top.v
INFO - C:/Users/chamberlin/Documents/Liron/top.v(1,8-1,13) (VERI-1018) compiling module blink
INFO - C:/Users/chamberlin/Documents/Liron/top.v(1,1-27,10) (VERI-9000) elaborating module 'blink'
INFO - C:/lscc/diamond/3.9_x64/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v(1793,1-1798,10) (VERI-9000) elaborating module 'OSCH_uniq_1'
WARNING - C:/Users/chamberlin/Documents/Liron/top.v(8,3-13,5) (VERI-1927) port SEDSTDBY remains unconnected for this instance
Done: design load finished with (0) errors, and (1) warnings
</PRE></BODY></HTML>