From 2a2ce54d32097558b81d014039309b68bce7aed8 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sun, 18 Apr 2021 16:50:56 -0600 Subject: [PATCH 01/27] add jst --- src/main.cpp | 20 ++++++++++++++++---- 1 file changed, 16 insertions(+), 4 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index 718e323..4336b6e 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -127,7 +127,8 @@ struct mos6502 : ASMLine rts, clc, sec, - bit + bit, + jsr }; static bool get_is_branch(const OpCode o) { @@ -156,6 +157,7 @@ struct mos6502 : ASMLine case OpCode::ORA: case OpCode::cmp: case OpCode::jmp: + case OpCode::jsr: case OpCode::adc: case OpCode::sbc: case OpCode::rts: @@ -192,6 +194,7 @@ struct mos6502 : ASMLine case OpCode::dec: case OpCode::ORA: case OpCode::jmp: + case OpCode::jsr: case OpCode::bne: case OpCode::bmi: case OpCode::beq: @@ -283,6 +286,8 @@ struct mos6502 : ASMLine return "sec"; case OpCode::bit: return "bit"; + case OpCode::jsr: + return "jsr"; case OpCode::unknown: return ""; }; @@ -353,7 +358,8 @@ struct i386 : ASMLine sbbb, negb, notb, - retl + retl, + call }; static OpCode parse_opcode(Type t, const std::string &o) @@ -400,6 +406,8 @@ struct i386 : ASMLine if (o == "sbbb") return OpCode::sbbb; if (o == "pushl") return OpCode::pushl; if (o == "retl") return OpCode::retl; + if (o == "call") return OpCode::call; + if (o == "calll") return OpCode::call; } } throw std::runtime_error("Unknown opcode: " + o); @@ -483,9 +491,9 @@ void translate_instruction(std::vector &instructions, const i386::OpCod instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num, 1)); instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num, 1)); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value)); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value)); instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value)); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value)); instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num, 1)); } else { throw std::runtime_error("Cannot translate movl instruction"); @@ -736,6 +744,10 @@ void translate_instruction(std::vector &instructions, const i386::OpCod } break; + case i386::OpCode::call: + instructions.emplace_back(mos6502::OpCode::jsr, o1); + break; + default: throw std::runtime_error("Cannot translate unhandled instruction"); From 13af1e8cca2702f781a18d543614502ee5b77da4 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 22 Apr 2021 10:42:21 -0600 Subject: [PATCH 02/27] Get AVR code starting to work, make debuggable --- examples/test.cpp | 2 +- src/main.cpp | 361 +++++++++++++++++++++++++++++++++------------- 2 files changed, 264 insertions(+), 99 deletions(-) diff --git a/examples/test.cpp b/examples/test.cpp index 56d2785..053f156 100644 --- a/examples/test.cpp +++ b/examples/test.cpp @@ -1,6 +1,6 @@ #include -enum class Colors : uint8_t +enum Colors : uint8_t { WHITE=0x01 }; diff --git a/src/main.cpp b/src/main.cpp index 4336b6e..958d0ab 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -6,6 +6,7 @@ #include #include #include +#include struct ASMLine { @@ -69,34 +70,9 @@ struct Operand } }; -Operand get_register(const int reg_num, const int offset = 0) { - switch (reg_num) { - // http://sta.c64.org/cbm64mem.html - case 0x00: return Operand(Operand::Type::literal, "$03"); // unused, fp->int routine pointer - case 0x01: return Operand(Operand::Type::literal, "$04"); - case 0x02: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer - case 0x03: return Operand(Operand::Type::literal, "$06"); - case 0x04: return Operand(Operand::Type::literal, "$fb"); // unused - case 0x05: return Operand(Operand::Type::literal, "$fc"); // unused - case 0x06: return Operand(Operand::Type::literal, "$fd"); // unused - case 0x07: return Operand(Operand::Type::literal, "$fe"); // unused - case 0x08: return Operand(Operand::Type::literal, "$22"); // unused - case 0x09: return Operand(Operand::Type::literal, "$23"); // unused - case 0x0A: return Operand(Operand::Type::literal, "$39"); // Current BASIC line number - case 0x0B: return Operand(Operand::Type::literal, "$3a"); // Current BASIC line number - case 0x10: return get_register(0x00 + offset); - case 0x11: return get_register(0x02 + offset); - case 0x12: return get_register(0x04 + offset); - case 0x13: return get_register(0x06 + offset); - case 0x14: return get_register(0x08 + offset); - case 0x15: return get_register(0x0A + offset); - }; - throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); -} - struct mos6502 : ASMLine { - enum class OpCode + enum class OpCode { unknown, lda, @@ -318,11 +294,9 @@ struct mos6502 : ASMLine bool is_comparison = false; }; - - struct i386 : ASMLine { - enum class OpCode + enum class OpCode { unknown, movzbl, @@ -362,6 +336,32 @@ struct i386 : ASMLine call }; +static Operand get_register(const int reg_num, const int offset = 0) { + switch (reg_num) { + // http://sta.c64.org/cbm64mem.html + case 0x00: return Operand(Operand::Type::literal, "$03"); // unused, fp->int routine pointer + case 0x01: return Operand(Operand::Type::literal, "$04"); + case 0x02: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer + case 0x03: return Operand(Operand::Type::literal, "$06"); + case 0x04: return Operand(Operand::Type::literal, "$fb"); // unused + case 0x05: return Operand(Operand::Type::literal, "$fc"); // unused + case 0x06: return Operand(Operand::Type::literal, "$fd"); // unused + case 0x07: return Operand(Operand::Type::literal, "$fe"); // unused + case 0x08: return Operand(Operand::Type::literal, "$22"); // unused + case 0x09: return Operand(Operand::Type::literal, "$23"); // unused + case 0x0A: return Operand(Operand::Type::literal, "$39"); // Current BASIC line number + case 0x0B: return Operand(Operand::Type::literal, "$3a"); // Current BASIC line number + case 0x10: return get_register(0x00 + offset); + case 0x11: return get_register(0x02 + offset); + case 0x12: return get_register(0x04 + offset); + case 0x13: return get_register(0x06 + offset); + case 0x14: return get_register(0x08 + offset); + case 0x15: return get_register(0x0A + offset); + }; + throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); +} + + static OpCode parse_opcode(Type t, const std::string &o) { switch(t) @@ -473,6 +473,123 @@ struct i386 : ASMLine Operand operand2; }; + + +struct AVR : ASMLine +{ + enum class OpCode + { + unknown, + ldi, + sts, + ret + }; + + static OpCode parse_opcode(Type t, const std::string &o) + { + switch(t) + { + case Type::Label: + return OpCode::unknown; + case Type::Directive: + return OpCode::unknown; + case Type::Instruction: + { + if (o == "ldi") { std::cout << "; parsed ldi\n"; return OpCode::ldi; } + if (o == "sts") return OpCode::sts; + if (o == "ret") return OpCode::ret; + } + } + throw std::runtime_error("Unknown opcode: " + o); + } + +static Operand get_register(const int reg_num, [[maybe_unused]] const int offset = 0) { + switch (reg_num) { + // http://sta.c64.org/cbm64mem.html + case 0: return Operand(Operand::Type::literal, "$03"); // unused, fp->int routine pointer + case 1: return Operand(Operand::Type::literal, "$04"); + case 2: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer + case 3: return Operand(Operand::Type::literal, "$06"); + case 4: return Operand(Operand::Type::literal, "$fb"); // unused + case 5: return Operand(Operand::Type::literal, "$fc"); // unused + case 6: return Operand(Operand::Type::literal, "$fd"); // unused + case 7: return Operand(Operand::Type::literal, "$fe"); // unused + case 8: return Operand(Operand::Type::literal, "$22"); // unused + case 9: return Operand(Operand::Type::literal, "$23"); // unused + case 10: return Operand(Operand::Type::literal, "$39"); // Current BASIC line number + case 11: return Operand(Operand::Type::literal, "$3a"); // Current BASIC line number + case 12: return Operand(Operand::Type::literal, "$61"); // arithmetic register #1 + case 13: return Operand(Operand::Type::literal, "$62"); + case 14: return Operand(Operand::Type::literal, "$63"); + case 15: return Operand(Operand::Type::literal, "$64"); + case 16: return Operand(Operand::Type::literal, "$65"); + case 17: return Operand(Operand::Type::literal, "$69"); // arithmetic register #2 + case 18: return Operand(Operand::Type::literal, "$6a"); + case 19: return Operand(Operand::Type::literal, "$6b"); + case 20: return Operand(Operand::Type::literal, "$6c"); + case 21: return Operand(Operand::Type::literal, "$6d"); + case 22: return Operand(Operand::Type::literal, "$57"); // arithmetic register #3 + case 23: return Operand(Operand::Type::literal, "$58"); + case 24: return Operand(Operand::Type::literal, "$59"); + case 25: return Operand(Operand::Type::literal, "$5a"); + case 26: return Operand(Operand::Type::literal, "$5b"); + case 27: return Operand(Operand::Type::literal, "$5c"); // arithmetic register #4 + case 28: return Operand(Operand::Type::literal, "$5d"); + case 29: return Operand(Operand::Type::literal, "$5e"); + case 30: return Operand(Operand::Type::literal, "$5f"); + case 31: return Operand(Operand::Type::literal, "$60"); + }; + throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); +} + + + static Operand parse_operand(std::string o) + { + if (o.empty()) { + return Operand(); + } + + if (o[0] == 'r' && o.size() > 1) { + return Operand(Operand::Type::reg, atoi(&o[1])); + } else { + return Operand(Operand::Type::literal, std::move(o)); + } + } + + AVR(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1="", std::string o2="") + : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), + opcode(parse_opcode(t, t_opcode)), operand1(parse_operand(o1)), operand2(parse_operand(o2)) + { + } + + int line_num; + std::string line_text; + OpCode opcode; + Operand operand1; + Operand operand2; +}; + +void translate_instruction(std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) +{ + std::cout << "; translating avr instruction : " << static_cast(op) << '\n'; + switch(op) + { + case AVR::OpCode::ldi: + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, o2.value)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + return; + case AVR::OpCode::sts: + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, Operand(o2.type, o2.value)); + return; + case AVR::OpCode::ret: + instructions.emplace_back(mos6502::OpCode::rts); + return; + } + + throw std::runtime_error("Could not translate unhandled instruction"); +} + void translate_instruction(std::vector &instructions, const i386::OpCode op, const Operand &o1, const Operand &o2) { switch(op) @@ -486,15 +603,15 @@ void translate_instruction(std::vector &instructions, const i386::OpCod break; case i386::OpCode::movl: if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); } else { throw std::runtime_error("Cannot translate movl instruction"); } @@ -503,8 +620,8 @@ void translate_instruction(std::vector &instructions, const i386::OpCod if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) { instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); } else { throw std::runtime_error("Cannot translate xorl instruction"); } @@ -515,13 +632,13 @@ void translate_instruction(std::vector &instructions, const i386::OpCod instructions.emplace_back(mos6502::OpCode::sta, o2); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); instructions.emplace_back(mos6502::OpCode::sta, o2); } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); } else { throw std::runtime_error("Cannot translate movb instruction"); } @@ -532,13 +649,13 @@ void translate_instruction(std::vector &instructions, const i386::OpCod instructions.emplace_back(mos6502::OpCode::ORA, o2); instructions.emplace_back(mos6502::OpCode::sta, o2); } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::ORA, get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::ORA, get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); } else { throw std::runtime_error("Cannot translate orb instruction"); } @@ -547,7 +664,7 @@ void translate_instruction(std::vector &instructions, const i386::OpCod case i386::OpCode::movzbl: if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { instructions.emplace_back(mos6502::OpCode::lda, o1); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); } else { throw std::runtime_error("Cannot translate movzbl instruction"); } @@ -555,7 +672,7 @@ void translate_instruction(std::vector &instructions, const i386::OpCod case i386::OpCode::shrb: if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { const auto do_shift = [&instructions](const int reg_num) { - instructions.emplace_back(mos6502::OpCode::lsr, get_register(reg_num)); + instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num)); }; if (o1.type == Operand::Type::literal) { @@ -573,8 +690,8 @@ void translate_instruction(std::vector &instructions, const i386::OpCod case i386::OpCode::shrl: if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { const auto do_shift = [&instructions](const int reg_num) { - instructions.emplace_back(mos6502::OpCode::lsr, get_register(reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::ror, get_register(reg_num)); + instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::ror, i386::get_register(reg_num)); }; if (o1.type == Operand::Type::literal) { @@ -592,16 +709,16 @@ void translate_instruction(std::vector &instructions, const i386::OpCod case i386::OpCode::testb: if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) { // this just tests the register for 0 - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); // instructions.emplace_back(mos6502::OpCode::bit, Operand(Operand::Type::literal, "#$00")); } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { // ands the values - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::bit, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { // ands the values instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::bit, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { // ands the values instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); @@ -612,14 +729,14 @@ void translate_instruction(std::vector &instructions, const i386::OpCod break; case i386::OpCode::decb: if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::dec, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::dec, i386::get_register(o1.reg_num)); } else { instructions.emplace_back(mos6502::OpCode::dec, o1); } break; case i386::OpCode::incb: if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::inc, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); } else { instructions.emplace_back(mos6502::OpCode::inc, o1); } @@ -638,17 +755,17 @@ void translate_instruction(std::vector &instructions, const i386::OpCod break; case i386::OpCode::addb: if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::adc, o2); instructions.emplace_back(mos6502::OpCode::sta, o2); } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::adc, o2); instructions.emplace_back(mos6502::OpCode::sta, o2); @@ -661,7 +778,7 @@ void translate_instruction(std::vector &instructions, const i386::OpCod instructions.emplace_back(mos6502::OpCode::lda, o2); instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); } else { throw std::runtime_error("Cannot translate cmpb instruction"); @@ -669,12 +786,12 @@ void translate_instruction(std::vector &instructions, const i386::OpCod break; case i386::OpCode::andb: if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - const auto reg = get_register(o2.reg_num); + const auto reg = i386::get_register(o2.reg_num); instructions.emplace_back(mos6502::OpCode::lda, reg); instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); instructions.emplace_back(mos6502::OpCode::sta, reg); } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - const auto reg = get_register(o2.reg_num); + const auto reg = i386::get_register(o2.reg_num); instructions.emplace_back(mos6502::OpCode::lda, o2); instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); instructions.emplace_back(mos6502::OpCode::sta, o2); @@ -685,10 +802,10 @@ void translate_instruction(std::vector &instructions, const i386::OpCod case i386::OpCode::negb: if (o1.type == Operand::Type::reg) { // perform a two's complement of the register location - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::inc, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); } else { throw std::runtime_error("Cannot translate negb instruction"); } @@ -696,9 +813,9 @@ void translate_instruction(std::vector &instructions, const i386::OpCod case i386::OpCode::notb: if (o1.type == Operand::Type::reg) { // exclusive or against 0xff to perform a logical not - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); - instructions.emplace_back(mos6502::OpCode::sta, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); } else { throw std::runtime_error("Cannot translate notb instruction"); } @@ -710,7 +827,7 @@ void translate_instruction(std::vector &instructions, const i386::OpCod if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { instructions.emplace_back(mos6502::OpCode::lda, o2); instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::sbc, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, i386::get_register(o1.reg_num)); instructions.emplace_back(mos6502::OpCode::sta, o2); } else { throw std::runtime_error("Cannot translate subb instruction"); @@ -718,9 +835,9 @@ void translate_instruction(std::vector &instructions, const i386::OpCod break; case i386::OpCode::pushl: if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); instructions.emplace_back(mos6502::OpCode::pha); - instructions.emplace_back(mos6502::OpCode::lda, get_register(o1.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); instructions.emplace_back(mos6502::OpCode::pha); } else { throw std::runtime_error("Cannot translate pushl instruction"); @@ -738,7 +855,7 @@ void translate_instruction(std::vector &instructions, const i386::OpCod instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); // reset a instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#$00")); // subtract out the carry flag instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); // invert the bits - instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num)); // place the value + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); // place the value } else { throw std::runtime_error("Cannot translate sbbb instruction"); } @@ -751,7 +868,7 @@ void translate_instruction(std::vector &instructions, const i386::OpCod default: throw std::runtime_error("Cannot translate unhandled instruction"); - }; + } } @@ -773,7 +890,9 @@ std::string to_string(const LogLevel ll) return "unknown"; } -void log(LogLevel ll, const i386 &i, const std::string &message) + +template +void log(LogLevel ll, const FromArch &i, const std::string &message) { std::cout << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n"; } @@ -783,8 +902,10 @@ void log(LogLevel ll, const int line_no, const std::string &line, const std::str std::cout << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; } -void to_mos6502(const i386 &i, std::vector &instructions) +template +void to_mos6502(const FromArch &i, std::vector &instructions) { + std::cout << "; arch " << typeid(FromArch).name() << '\n'; try { switch(i.type) { @@ -795,19 +916,23 @@ void to_mos6502(const i386 &i, std::vector &instructions) instructions.emplace_back(i.type, i.text); return; case ASMLine::Type::Instruction: -// instructions.emplace_back(ASMLine::Type::Directive, "; " + i.line_text); + instructions.emplace_back(ASMLine::Type::Directive, "; " + i.line_text); const auto head = instructions.size(); - translate_instruction(instructions, i.opcode, i.operand1, i.operand2); + + try { + translate_instruction(instructions, i.opcode, i.operand1, i.operand2); + } catch (const std::exception &e) { + log(LogLevel::Error, i, e.what()); + } auto text = i.line_text; if (text[0] == '\t') { text.erase(0, 1); } - for_each(std::next(instructions.begin(), head), instructions.end(), - [ text ](auto &ins){ - - ins.comment = text; + for_each(std::next(instructions.begin(), head), instructions.end(), + [ text ](auto &ins){ + ins.comment = text; } ); return; @@ -866,7 +991,7 @@ bool optimize(std::vector &instructions) const auto operand = instructions[op].op; auto op2 = op+1; // look for multiple stores of the same value - while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta + while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) { ++op2; } @@ -928,14 +1053,14 @@ bool fix_overwritten_flags(std::vector &instructions) { if (instructions[op].is_comparison) { auto op2 = op + 1; - while (op2 < instructions.size() + while (op2 < instructions.size() && !instructions[op2].is_comparison && !instructions[op2].is_branch) { ++op2; } - if (op2 < instructions.size() + if (op2 < instructions.size() && (op2 - op) > 1 && instructions[op2-1].opcode != mos6502::OpCode::plp) { if (instructions[op2].is_comparison) { @@ -959,24 +1084,27 @@ bool fix_overwritten_flags(std::vector &instructions) } -int main() -{ +template +void run(std::istream &input) { + std::cout << "; run\n"; std::regex Comment(R"(\s*\#.*)"); std::regex Label(R"(^(\S+):.*)"); - std::regex Directive(R"(^\t(\..+))"); - std::regex UnaryInstruction(R"(^\t(\S+)\s+(\S+))"); - std::regex BinaryInstruction(R"(^\t(\S+)\s+(\S+),\s+(\S+))"); - std::regex Instruction(R"(^\t(\S+))"); + std::regex Directive(R"(^\s+(\..+))"); + std::regex UnaryInstruction(R"(^\s+(\S+)\s+(\S+))"); + std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+))"); + std::regex Instruction(R"(^\s+(\S+))"); int lineno = 0; - std::vector instructions; - while (std::cin.good()) + + std::vector instructions; + + while (input.good()) { std::string line; - getline(std::cin, line); - + getline(input, line); + std::cout << "; read line: '" << line << "'\n"; try { std::smatch match; if (std::regex_match(line, match, Label)) @@ -986,10 +1114,10 @@ int main() // don't care about comments } else if (std::regex_match(line, match, Directive)) { instructions.emplace_back(lineno, line, ASMLine::Type::Directive, match[1]); - } else if (std::regex_match(line, match, UnaryInstruction)) { - instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1], match[2]); } else if (std::regex_match(line, match, BinaryInstruction)) { instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1], match[2], match[3]); + } else if (std::regex_match(line, match, UnaryInstruction)) { + instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1], match[2]); } else if (std::regex_match(line, match, Instruction)) { instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1]); } else if (line == "") { @@ -1004,9 +1132,13 @@ int main() ++lineno; } + std::cout << "; done reading file" << std::endl; + std::set labels; - for (const auto i : instructions) + std::cout << "; " << instructions.size() << " instructions parsed" << std::endl; + + for (const auto &i : instructions) { if (i.type == ASMLine::Type::Label) { labels.insert(i.text); @@ -1015,7 +1147,7 @@ int main() std::set used_labels{"main"}; - for (const auto i : instructions) + for (const auto &i : instructions) { if (i.type == ASMLine::Type::Instruction) { @@ -1032,6 +1164,7 @@ int main() [&used_labels](const auto &i){ if (i.type == ASMLine::Type::Label) { if (used_labels.count(i.text) == 0) { + std::cout << "; removed label: '" << i.text << "'\n"; // remove all unused labels that aren't 'main' return true; } @@ -1044,7 +1177,7 @@ int main() - const auto new_labels = + const auto new_labels = [&used_labels](){ std::map result; for (const auto &l : used_labels) { @@ -1081,6 +1214,7 @@ int main() for (const auto &i : instructions) { + std::cout << "; translating instruction: '" << i.text << '\'' << std::endl; to_mos6502(i, new_instructions); } @@ -1106,3 +1240,34 @@ int main() std::cout << i.to_string() << '\n'; } } + +int main([[maybe_unused]] const int argc, const char *argv[]) +{ + std::ifstream input_file; + + std::istream &input = [&]() -> std::istream & { + if (argc > 1) { + input_file.open(argv[1]); + return input_file; + } else { + return std::cin; + } + }(); + + const bool is_avr = [&]() { + for (std::size_t index = 0; index < static_cast(argc); ++index) { + if (strstr(argv[index], "avr") != nullptr) { + return true; + } + } + return false; + }(); + + if (is_avr) { + std::cout << "; AVR Mode\n"; + run(input); + } else { + run(input); + } +} + From 5591249f2a79eb515d6d79ad58d3333e7e1e9f9b Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 22 Apr 2021 15:52:35 -0600 Subject: [PATCH 03/27] Almost working programs with AVR conversion * need to add a decent header address * probably need to fix sbrc and sbrs --- CMakeLists.txt | 10 ++- examples/test2.cpp | 8 +-- src/main.cpp | 173 +++++++++++++++++++++++++++++++++++++++++---- 3 files changed, 166 insertions(+), 25 deletions(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index 0040ab1..bfd5a5f 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,13 +1,11 @@ cmake_minimum_required(VERSION 3.5) -set (CMAKE_CXX_STANDARD 14) - project(x86-to-6502) -if(CMAKE_COMPILER_IS_GNUCC) - add_definitions(-Wall -Wextra -Wconversion -Wshadow -Wnon-virtual-dtor -Wold-style-cast -Wcast-align -Wcast-qual -Wunused -Woverloaded-virtual -pedantic -std=c++14) -endif() - add_executable(x86-to-6502 src/main.cpp) +target_compile_features(x86-to-6502 PRIVATE cxx_std_20) +if (CMAKE_COMPILER_IS_GNUCC) + target_compile_options(x86-to-6502 PRIVATE -Wall -Wextra -Wconversion -Wshadow -Wnon-virtual-dtor -Wold-style-cast -Wcast-align -Wcast-qual -Wunused -Woverloaded-virtual -Wpedantic) +endif () diff --git a/examples/test2.cpp b/examples/test2.cpp index 2001fc1..744e29b 100644 --- a/examples/test2.cpp +++ b/examples/test2.cpp @@ -6,22 +6,22 @@ enum class Colors : uint8_t BLACK=0x00 }; -volatile uint8_t &memory_loc(const uint16_t loc) +inline volatile uint8_t &memory_loc(const uint16_t loc) { return *reinterpret_cast(loc); } -void decrement_border_color() +inline void decrement_border_color() { --memory_loc(0xd020); } -void increment_border_color() +inline void increment_border_color() { ++memory_loc(0xd020); } -bool joystick_down() +inline bool joystick_down() { uint8_t joystick_state = memory_loc(0xDC00); return (joystick_state & 0x2) == 0; diff --git a/src/main.cpp b/src/main.cpp index 958d0ab..5b1fd1f 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -34,6 +34,10 @@ std::string fixup_8bit_literal(const std::string &s) { return "#" + std::to_string(static_cast(parse_8bit_literal(s))); } else { + if (s.starts_with("lo8(") && s.ends_with(")")) { + return "#<" + s.substr(4, s.size() - 5); + } + return s; } } @@ -60,6 +64,7 @@ struct Operand Operand(const Type t, std::string v) : type(t), value(std::move(v)) { + assert(type == Type::literal); } @@ -76,6 +81,8 @@ struct mos6502 : ASMLine { unknown, lda, + asl, + rol, ldy, tay, tya, @@ -140,6 +147,8 @@ struct mos6502 : ASMLine case OpCode::clc: case OpCode::sec: case OpCode::bit: + case OpCode::asl: + case OpCode::rol: case OpCode::unknown: break; } @@ -179,6 +188,8 @@ struct mos6502 : ASMLine case OpCode::rts: case OpCode::clc: case OpCode::sec: + case OpCode::rol: + case OpCode::asl: case OpCode::unknown: break; } @@ -206,6 +217,10 @@ struct mos6502 : ASMLine switch (o) { case OpCode::lda: return "lda"; + case OpCode::asl: + return "asl"; + case OpCode::rol: + return "rol"; case OpCode::ldy: return "ldy"; case OpCode::tay: @@ -482,7 +497,21 @@ struct AVR : ASMLine unknown, ldi, sts, - ret + ret, + mov, + lsl, + rol, + rcall, + ld, + subi, + st, + lds, + lsr, + andi, + eor, + sbrc, + sbrs, + rjmp }; static OpCode parse_opcode(Type t, const std::string &o) @@ -495,9 +524,23 @@ struct AVR : ASMLine return OpCode::unknown; case Type::Instruction: { - if (o == "ldi") { std::cout << "; parsed ldi\n"; return OpCode::ldi; } + if (o == "ldi") return OpCode::ldi; if (o == "sts") return OpCode::sts; if (o == "ret") return OpCode::ret; + if (o == "mov") return OpCode::mov; + if (o == "lsl") return OpCode::lsl; + if (o == "rol") return OpCode::rol; + if (o == "rcall") return OpCode::rcall; + if (o == "ld") return OpCode::ld; + if (o == "subi") return OpCode::subi; + if (o == "st") return OpCode::st; + if (o == "lds") return OpCode::lds; + if (o == "lsr") return OpCode::lsr; + if (o == "andi") return OpCode::andi; + if (o == "eor") return OpCode::eor; + if (o == "sbrc") return OpCode::sbrc; + if (o == "rjmp") return OpCode::rjmp; + if (o == "sbrs") return OpCode::sbrs; } } throw std::runtime_error("Unknown opcode: " + o); @@ -538,7 +581,7 @@ static Operand get_register(const int reg_num, [[maybe_unused]] const int offset case 29: return Operand(Operand::Type::literal, "$5e"); case 30: return Operand(Operand::Type::literal, "$5f"); case 31: return Operand(Operand::Type::literal, "$60"); - }; + } throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); } @@ -571,20 +614,111 @@ static Operand get_register(const int reg_num, [[maybe_unused]] const int offset void translate_instruction(std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) { - std::cout << "; translating avr instruction : " << static_cast(op) << '\n'; switch(op) { case AVR::OpCode::ldi: - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, o2.value)); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value))); instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); return; case AVR::OpCode::sts: instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, Operand(o2.type, o2.value)); + instructions.emplace_back(mos6502::OpCode::sta, Operand(o1.type, o1.value)); return; case AVR::OpCode::ret: instructions.emplace_back(mos6502::OpCode::rts); return; + case AVR::OpCode::mov: + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + return; + case AVR::OpCode::lsl: + instructions.emplace_back(mos6502::OpCode::asl, AVR::get_register(o1.reg_num)); + return; + case AVR::OpCode::rol: + instructions.emplace_back(mos6502::OpCode::rol, AVR::get_register(o1.reg_num)); + return; + case AVR::OpCode::rcall: + instructions.emplace_back(mos6502::OpCode::jsr, Operand(o1.type, o1.value)); + return; + case AVR::OpCode::ld: + { + if (o2.value == "Z") { + instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, + "(" + AVR::get_register(30).value + "), Y")); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + return; + } + throw std::runtime_error("Unhandled ld to non-Z"); + } + case AVR::OpCode::subi: + { + // to do: deal with Carry bit (and other flags) nonsense from AVR + // if |x| < |y| -> x-y +carry + // for these special cases with -(1) and -(-(1)) + if (o2.value == "lo8(-(-1))") { + instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1.reg_num)); + return; + } + if (o2.value == "lo8(-(1))") { + instructions.emplace_back(mos6502::OpCode::inc, AVR::get_register(o1.reg_num)); + return; + } + + throw std::runtime_error("Unhandled subi sub case"); + } + case AVR::OpCode::st: { + if (o1.value == "Z") { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, + "(" + AVR::get_register(30).value + "), Y")); + + return; + } + throw std::runtime_error("Unhandled st with non-Z parameter"); + } + case AVR::OpCode::lds: { + instructions.emplace_back(mos6502::OpCode::lda, o2); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + return; + } + case AVR::OpCode::lsr: { + instructions.emplace_back(mos6502::OpCode::lsr, AVR::get_register(o1.reg_num)); + return; + } + case AVR::OpCode::andi: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::AND, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + return; + } + case AVR::OpCode::eor: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::eor, AVR::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + return; + } + case AVR::OpCode::sbrc: { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(std::to_string(1 << (atoi(o2.value.c_str())-1))))); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } + case AVR::OpCode::sbrs: { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(std::to_string(1 << (atoi(o2.value.c_str())-1))))); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } + case AVR::OpCode::rjmp: { + instructions.emplace_back(mos6502::OpCode::jmp, o1); + return; + } } throw std::runtime_error("Could not translate unhandled instruction"); @@ -905,7 +1039,6 @@ void log(LogLevel ll, const int line_no, const std::string &line, const std::str template void to_mos6502(const FromArch &i, std::vector &instructions) { - std::cout << "; arch " << typeid(FromArch).name() << '\n'; try { switch(i.type) { @@ -916,8 +1049,6 @@ void to_mos6502(const FromArch &i, std::vector &instructions) instructions.emplace_back(i.type, i.text); return; case ASMLine::Type::Instruction: - instructions.emplace_back(ASMLine::Type::Directive, "; " + i.line_text); - const auto head = instructions.size(); try { @@ -1104,7 +1235,6 @@ void run(std::istream &input) { { std::string line; getline(input, line); - std::cout << "; read line: '" << line << "'\n"; try { std::smatch match; if (std::regex_match(line, match, Label)) @@ -1132,12 +1262,8 @@ void run(std::istream &input) { ++lineno; } - std::cout << "; done reading file" << std::endl; - std::set labels; - std::cout << "; " << instructions.size() << " instructions parsed" << std::endl; - for (const auto &i : instructions) { if (i.type == ASMLine::Type::Label) { @@ -1212,10 +1338,27 @@ void run(std::istream &input) { std::vector new_instructions; + bool skip_next_instruction = false; + std::string next_label_name; for (const auto &i : instructions) { - std::cout << "; translating instruction: '" << i.text << '\'' << std::endl; to_mos6502(i, new_instructions); + + // intentionally copy so we don't invalidate the reference + const auto last_instruction = new_instructions.back(); + const auto last_instruction_loc = new_instructions.size() - 1; + + if (skip_next_instruction) { + new_instructions.emplace_back(ASMLine::Type::Label, next_label_name); + skip_next_instruction = false; + } + + if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_instruction")) + { + skip_next_instruction = true; + next_label_name = last_instruction.text; + new_instructions.erase(std::next(new_instructions.begin(), static_cast(last_instruction_loc))); + } } while (fix_overwritten_flags(new_instructions)) From 24012c1ff7c9d14919bfab9e38621b015e209219 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 22 Apr 2021 18:52:50 -0600 Subject: [PATCH 04/27] Fix use of address 1 to literal 1 for skip instructions Thank you to the viewers who pointed out the issue at the end of the stream. At this point, simple code works, but the conditional from the joystick input does not seem to work yet. * also add location header for linker * also filter errors and directives better --- examples/test.cpp | 10 +++++----- src/main.cpp | 19 ++++++++++--------- 2 files changed, 15 insertions(+), 14 deletions(-) diff --git a/examples/test.cpp b/examples/test.cpp index 053f156..af2685f 100644 --- a/examples/test.cpp +++ b/examples/test.cpp @@ -5,22 +5,22 @@ enum Colors : uint8_t WHITE=0x01 }; -volatile uint8_t &memory_loc(const uint16_t loc) +static volatile uint8_t &memory_loc(const uint16_t loc) { return *reinterpret_cast(loc); } -void decrement_border_color() +static void decrement_border_color() { --memory_loc(0xd020); } -void increment_border_color() +static void increment_border_color() { ++memory_loc(0xd020); } -bool joystick_down() +static bool joystick_down() { uint8_t joystick_state = memory_loc(0xDC00); return (joystick_state & 0x2) == 0; @@ -36,7 +36,7 @@ int main() while(true) { if (joystick_down()) { - increment_border_color(); +// increment_border_color(); } else { decrement_border_color(); } diff --git a/src/main.cpp b/src/main.cpp index 5b1fd1f..c73fb81 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -700,7 +700,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } case AVR::OpCode::sbrc: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(std::to_string(1 << (atoi(o2.value.c_str())-1))))); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())-1))))); instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); @@ -708,7 +708,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } case AVR::OpCode::sbrs: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(std::to_string(1 << (atoi(o2.value.c_str())-1))))); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())-1))))); instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); @@ -1028,12 +1028,12 @@ std::string to_string(const LogLevel ll) template void log(LogLevel ll, const FromArch &i, const std::string &message) { - std::cout << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n"; + std::cerr << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n"; } void log(LogLevel ll, const int line_no, const std::string &line, const std::string &message) { - std::cout << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; + std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; } template @@ -1217,10 +1217,9 @@ bool fix_overwritten_flags(std::vector &instructions) template void run(std::istream &input) { - std::cout << "; run\n"; std::regex Comment(R"(\s*\#.*)"); std::regex Label(R"(^(\S+):.*)"); - std::regex Directive(R"(^\s+(\..+))"); + std::regex Directive(R"(^\s*(\..+))"); std::regex UnaryInstruction(R"(^\s+(\S+)\s+(\S+))"); std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+))"); std::regex Instruction(R"(^\s+(\S+))"); @@ -1251,9 +1250,6 @@ void run(std::istream &input) { } else if (std::regex_match(line, match, Instruction)) { instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1]); } else if (line == "") { - //std::cout << "EmptyLine\n"; - } else { - throw std::runtime_error("Unparsed Input, Line: " + std::to_string(lineno)); } } catch (const std::exception &e) { log(LogLevel::Error, lineno, line, e.what()); @@ -1295,6 +1291,9 @@ void run(std::istream &input) { return true; } } + if (i.type == ASMLine::Type::Directive) { + return true; + } return false; } ), @@ -1337,6 +1336,8 @@ void run(std::istream &input) { std::vector new_instructions; + new_instructions.emplace_back(ASMLine::Type::Directive, ".word $1000"); + new_instructions.emplace_back(ASMLine::Type::Directive, "* = $1000"); bool skip_next_instruction = false; std::string next_label_name; From ad75dcdfef403e375d25c2e16ba7974c1aacd52c Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 22 Apr 2021 20:44:44 -0600 Subject: [PATCH 05/27] Fix which bit is tested with the sbrs instruction --- src/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index c73fb81..c971802 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -700,7 +700,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } case AVR::OpCode::sbrc: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())-1))))); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); @@ -708,7 +708,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } case AVR::OpCode::sbrs: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())-1))))); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); From 51c5767f0e16e8d0551c6052398e32218d4d2a07 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sun, 2 May 2021 18:10:12 -0600 Subject: [PATCH 06/27] Ability to copy from .data section resources to RAM --- src/main.cpp | 177 ++++++++++++++++++++++++++++++++++++++++++--------- 1 file changed, 148 insertions(+), 29 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index c971802..e8fdd64 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -28,6 +28,17 @@ int parse_8bit_literal(const std::string &s) return std::stoi(std::string(std::next(std::begin(s)), std::end(s))); } + +std::string strip_lo_hi(const std::string &s) +{ + if ((s.starts_with("lo8(") || s.starts_with("hi8(")) + && s.ends_with(")")) { + return s.substr(4, s.size() - 5); + } + + return s; +} + std::string fixup_8bit_literal(const std::string &s) { if (s[0] == '$') @@ -35,7 +46,13 @@ std::string fixup_8bit_literal(const std::string &s) return "#" + std::to_string(static_cast(parse_8bit_literal(s))); } else { if (s.starts_with("lo8(") && s.ends_with(")")) { - return "#<" + s.substr(4, s.size() - 5); + return "#<" + strip_lo_hi(s); + } + if (s.starts_with("hi8(") && s.ends_with(")")) { + return "#>" + strip_lo_hi(s); + } + if (s == "0") { + return "#0"; } return s; @@ -511,7 +528,9 @@ struct AVR : ASMLine eor, sbrc, sbrs, - rjmp + brne, + rjmp, + dec }; static OpCode parse_opcode(Type t, const std::string &o) @@ -541,16 +560,38 @@ struct AVR : ASMLine if (o == "sbrc") return OpCode::sbrc; if (o == "rjmp") return OpCode::rjmp; if (o == "sbrs") return OpCode::sbrs; + if (o == "brne") return OpCode::brne; + if (o == "dec") return OpCode::dec; } } throw std::runtime_error("Unknown opcode: " + o); } + static int get_register_number(const char reg_name) + { + if (reg_name == 'X') { + return 26; + } + + if (reg_name == 'Y') { + return 28; + } + + if (reg_name == 'Z') { + return 30; + } + + } + + static Operand get_register(const char reg_name, const int byte = 0) { + return get_register(get_register_number(reg_name), byte); + } + static Operand get_register(const int reg_num, [[maybe_unused]] const int offset = 0) { switch (reg_num) { // http://sta.c64.org/cbm64mem.html - case 0: return Operand(Operand::Type::literal, "$03"); // unused, fp->int routine pointer - case 1: return Operand(Operand::Type::literal, "$04"); + case 0: return Operand(Operand::Type::literal, "$a7"); // bit buffer for rs232 + case 1: return Operand(Operand::Type::literal, "$a8"); // counter for rs232 case 2: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer case 3: return Operand(Operand::Type::literal, "$06"); case 4: return Operand(Operand::Type::literal, "$fb"); // unused @@ -612,10 +653,42 @@ static Operand get_register(const int reg_num, [[maybe_unused]] const int offset Operand operand2; }; +void indirect_load(std::vector &instructions, const std::string &from_address_low_byte, const std::string &to_address) +{ + instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, + "(" + from_address_low_byte + "), Y")); + instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, to_address)); +} + +void indirect_store(std::vector &instructions, const std::string &from_address, const std::string &to_address_low_byte) +{ + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, from_address)); + instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, + "(" + to_address_low_byte + "), Y") ); +} + + +void increment_16_bit(std::vector & instructions, int reg) { + //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg)); + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#1")); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg+1)); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg+1)); + +} + void translate_instruction(std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) { switch(op) { + case AVR::OpCode::dec: + instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1.reg_num)); + return; case AVR::OpCode::ldi: instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value))); instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); @@ -642,11 +715,13 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; case AVR::OpCode::ld: { - if (o2.value == "Z") { - instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, - "(" + AVR::get_register(30).value + "), Y")); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { + indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1.reg_num).value); + return; + } + if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") { + indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1.reg_num).value); + increment_16_bit(instructions, AVR::get_register_number(o2.value[0])); return; } throw std::runtime_error("Unhandled ld to non-Z"); @@ -668,15 +743,16 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode throw std::runtime_error("Unhandled subi sub case"); } case AVR::OpCode::st: { - if (o1.value == "Z") { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); - instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, - "(" + AVR::get_register(30).value + "), Y")); - + if (o1.value == "Z" || o1.value == "Y"||o1.value == "X") { + indirect_store(instructions, AVR::get_register(o2.reg_num).value, AVR::get_register(o1.value[0]).value); return; } - throw std::runtime_error("Unhandled st with non-Z parameter"); + if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") { + indirect_store(instructions, AVR::get_register(o2.reg_num).value, AVR::get_register(o1.value[0]).value); + increment_16_bit(instructions, AVR::get_register_number(o1.value[0])); + return; + } + throw std::runtime_error("Unhandled st"); } case AVR::OpCode::lds: { instructions.emplace_back(mos6502::OpCode::lda, o2); @@ -715,6 +791,15 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(ASMLine::Type::Directive, new_label_name); return; } + case AVR::OpCode::brne: { + if (o1.value == "0b") { + instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, "memcpy_0")); + } else { + instructions.emplace_back(mos6502::OpCode::bne, o1); + } + return; + } + case AVR::OpCode::rjmp: { instructions.emplace_back(mos6502::OpCode::jmp, o1); return; @@ -1043,10 +1128,18 @@ void to_mos6502(const FromArch &i, std::vector &instructions) switch(i.type) { case ASMLine::Type::Label: - instructions.emplace_back(i.type, i.text); + if (i.text == "0") { + instructions.emplace_back(i.type, "-memcpy_0"); + } else { + instructions.emplace_back(i.type, i.text); + } return; case ASMLine::Type::Directive: - instructions.emplace_back(i.type, i.text); + if (i.text.starts_with(".string")) { + instructions.emplace_back(ASMLine::Type::Directive, ".asc " + i.text.substr(7)); + } else { + instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + i.text); + } return; case ASMLine::Type::Instruction: const auto head = instructions.size(); @@ -1054,6 +1147,7 @@ void to_mos6502(const FromArch &i, std::vector &instructions) try { translate_instruction(instructions, i.opcode, i.operand1, i.operand2); } catch (const std::exception &e) { + instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + i.text + "' " + e.what()); log(LogLevel::Error, i, e.what()); } @@ -1218,7 +1312,7 @@ bool fix_overwritten_flags(std::vector &instructions) template void run(std::istream &input) { std::regex Comment(R"(\s*\#.*)"); - std::regex Label(R"(^(\S+):.*)"); + std::regex Label(R"(^\s*(\S+):.*)"); std::regex Directive(R"(^\s*(\..+))"); std::regex UnaryInstruction(R"(^\s+(\S+)\s+(\S+))"); std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+))"); @@ -1273,26 +1367,35 @@ void run(std::istream &input) { { if (i.type == ASMLine::Type::Instruction) { - if (labels.count(i.operand1.value) != 0) { - used_labels.insert(i.operand1.value); - used_labels.insert(i.operand2.value); - } +// if (labels.count(i.operand1.value) != 0) { + used_labels.insert(strip_lo_hi(i.operand1.value)); + used_labels.insert(strip_lo_hi(i.operand2.value)); +// } + } } - + used_labels.erase("X"); + used_labels.erase("X+"); + used_labels.erase("-X"); + used_labels.erase("Y"); + used_labels.erase("Y+"); + used_labels.erase("-Y"); + used_labels.erase("Z"); + used_labels.erase("Z+"); + used_labels.erase("-Z"); // remove all labels and directives that we don't need instructions.erase( std::remove_if(std::begin(instructions), std::end(instructions), [&used_labels](const auto &i){ if (i.type == ASMLine::Type::Label) { - if (used_labels.count(i.text) == 0) { - std::cout << "; removed label: '" << i.text << "'\n"; + // if (used_labels.count(i.text) == 0) { + // std::cout << "; removed label: '" << i.text << "'\n"; // remove all unused labels that aren't 'main' - return true; - } + // return true; + // } } if (i.type == ASMLine::Type::Directive) { - return true; + // return true; } return false; } @@ -1305,24 +1408,39 @@ void run(std::istream &input) { const auto new_labels = [&used_labels](){ std::map result; +// result.emplace(std::make_pair("0", "-memcpy_0")); for (const auto &l : used_labels) { auto newl = l; std::transform(newl.begin(), newl.end(), newl.begin(), [](const auto c) { return std::tolower(c); }); newl.erase(std::remove_if(newl.begin(), newl.end(), [](const auto c){ return !std::isalnum(c); }), std::end(newl)); + result.emplace(std::make_pair(l, newl)); } return result; }(); + for (const auto &l : new_labels) { + std::clog << "Label: '" << l.first << "': '" << l.second << "'\n"; + } for (auto &i : instructions) { if (i.type == ASMLine::Type::Label) { + std::clog << "Looking up Label: '" << i.text << "'\n"; i.text = new_labels.at(i.text); } + if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8(")) + { + const auto potential_label = strip_lo_hi(i.operand2.value); + const auto itr1 = new_labels.find(potential_label); + if (itr1 != new_labels.end()) { + i.operand2.value.replace(4, potential_label.size(), itr1->second); + } + } + const auto itr1 = new_labels.find(i.operand1.value); if (itr1 != new_labels.end()) { i.operand1.value = itr1->second; @@ -1338,6 +1456,7 @@ void run(std::istream &input) { std::vector new_instructions; new_instructions.emplace_back(ASMLine::Type::Directive, ".word $1000"); new_instructions.emplace_back(ASMLine::Type::Directive, "* = $1000"); + new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); bool skip_next_instruction = false; std::string next_label_name; From b0980ac10abf66dd4ed3906ac7b0e0add33d97e3 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Mon, 3 May 2021 09:57:49 -0600 Subject: [PATCH 07/27] More multi-byte operations working --- src/main.cpp | 209 ++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 148 insertions(+), 61 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index e8fdd64..9986ff0 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -51,9 +51,13 @@ std::string fixup_8bit_literal(const std::string &s) if (s.starts_with("hi8(") && s.ends_with(")")) { return "#>" + strip_lo_hi(s); } + // todo make this a generic number check if (s == "0") { return "#0"; } + if (s == "1") { + return "#1"; + } return s; } @@ -121,6 +125,7 @@ struct mos6502 : ASMLine bne, beq, bmi, + bpl, jmp, adc, sbc, @@ -136,6 +141,7 @@ struct mos6502 : ASMLine case OpCode::beq: case OpCode::bne: case OpCode::bmi: + case OpCode::bpl: return true; case OpCode::lda: case OpCode::ldy: @@ -296,6 +302,8 @@ struct mos6502 : ASMLine return "bit"; case OpCode::jsr: return "jsr"; + case OpCode::bpl: + return "bpl"; case OpCode::unknown: return ""; }; @@ -521,6 +529,7 @@ struct AVR : ASMLine rcall, ld, subi, + sbci, st, lds, lsr, @@ -530,7 +539,8 @@ struct AVR : ASMLine sbrs, brne, rjmp, - dec + dec, + sbiw }; static OpCode parse_opcode(Type t, const std::string &o) @@ -552,6 +562,7 @@ struct AVR : ASMLine if (o == "rcall") return OpCode::rcall; if (o == "ld") return OpCode::ld; if (o == "subi") return OpCode::subi; + if (o == "sbci") return OpCode::sbci; if (o == "st") return OpCode::st; if (o == "lds") return OpCode::lds; if (o == "lsr") return OpCode::lsr; @@ -562,6 +573,7 @@ struct AVR : ASMLine if (o == "sbrs") return OpCode::sbrs; if (o == "brne") return OpCode::brne; if (o == "dec") return OpCode::dec; + if (o == "sbiw") return OpCode::sbiw; } } throw std::runtime_error("Unknown opcode: " + o); @@ -669,6 +681,40 @@ void indirect_store(std::vector &instructions, const std::string &from_ "(" + to_address_low_byte + "), Y") ); } +void fixup_16_bit_N_Z_flags(std::vector &instructions) +{ + + // need to get both Z and N set appropriately + // assuming A contains higher order byte and Y contains lower order byte + // todo, abstract this out so it can be used after any 16 bit op + instructions.emplace_back(ASMLine::Type::Directive, "; set CPU flags assuming A holds the higher order byte already"); + std::string set_flag_label = "flags_set_after_16_bit_op_" + std::to_string(instructions.size()); + // if high order is negative, we know it's not 0 and it is negative + instructions.emplace_back(mos6502::OpCode::bmi, Operand(Operand::Type::literal, set_flag_label)); + // if it's not 0, then branch down, we know the result is not 0 and not negative + instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, set_flag_label)); + // if the higher order byte is 0, test the lower order byte, which was saved for us in Y + instructions.emplace_back(mos6502::OpCode::tya); + // if low order is not negative, we know it's 0 or not 0 + instructions.emplace_back(mos6502::OpCode::bpl, Operand(Operand::Type::literal, set_flag_label)); + // if low order byte is negative, shift right by one bit, then we'll get the proper Z/N flags + instructions.emplace_back(mos6502::OpCode::lsr); + instructions.emplace_back(ASMLine::Type::Label, set_flag_label); +} + + +void subtract_16_bit(std::vector &instructions, int reg, const std::uint16_t value) { + //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); + instructions.emplace_back(mos6502::OpCode::sec); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg)); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string(value & 0xFF))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8) & 0xFF))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::tay); + fixup_16_bit_N_Z_flags(instructions); +} void increment_16_bit(std::vector & instructions, int reg) { //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); @@ -679,76 +725,104 @@ void increment_16_bit(std::vector & instructions, int reg) { instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg+1)); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#0")); instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg+1)); - } void translate_instruction(std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) { + const auto translate_register_number = [](const Operand ®) { + if (reg.value == "__zero_reg__") { + return 1; + } else { + return reg.reg_num; + } + }; + + const auto o1_reg_num = translate_register_number(o1); + const auto o2_reg_num = translate_register_number(o2); + switch(op) { case AVR::OpCode::dec: - instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); return; case AVR::OpCode::ldi: instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); return; case AVR::OpCode::sts: - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); instructions.emplace_back(mos6502::OpCode::sta, Operand(o1.type, o1.value)); return; case AVR::OpCode::ret: instructions.emplace_back(mos6502::OpCode::rts); return; case AVR::OpCode::mov: - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); return; case AVR::OpCode::lsl: - instructions.emplace_back(mos6502::OpCode::asl, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::asl, AVR::get_register(o1_reg_num)); return; case AVR::OpCode::rol: - instructions.emplace_back(mos6502::OpCode::rol, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::rol, AVR::get_register(o1_reg_num)); return; case AVR::OpCode::rcall: - instructions.emplace_back(mos6502::OpCode::jsr, Operand(o1.type, o1.value)); + instructions.emplace_back(mos6502::OpCode::jsr, o1); return; case AVR::OpCode::ld: { if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { - indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1.reg_num).value); + indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); return; } if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") { - indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1.reg_num).value); + indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); increment_16_bit(instructions, AVR::get_register_number(o2.value[0])); return; } throw std::runtime_error("Unhandled ld to non-Z"); } + case AVR::OpCode::sbci: + { + // we want to utilize the carry flag, however it was set previously + // (it's really a borrow flag on the 6502) + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + fixup_16_bit_N_Z_flags(instructions); + return; + } case AVR::OpCode::subi: { // to do: deal with Carry bit (and other flags) nonsense from AVR // if |x| < |y| -> x-y +carry // for these special cases with -(1) and -(-(1)) if (o2.value == "lo8(-(-1))") { - instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); return; } if (o2.value == "lo8(-(1))") { - instructions.emplace_back(mos6502::OpCode::inc, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::inc, AVR::get_register(o1_reg_num)); return; } - throw std::runtime_error("Unhandled subi sub case"); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + // have to set carry flag, since it gets inverted by sbc + instructions.emplace_back(mos6502::OpCode::sec); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + // temporarily store lower order (not carried substraction) byte into Y for checking + // later if this is a two byte subtraction operation + instructions.emplace_back(mos6502::OpCode::tay); + return; } case AVR::OpCode::st: { if (o1.value == "Z" || o1.value == "Y"||o1.value == "X") { - indirect_store(instructions, AVR::get_register(o2.reg_num).value, AVR::get_register(o1.value[0]).value); + indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); return; } if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") { - indirect_store(instructions, AVR::get_register(o2.reg_num).value, AVR::get_register(o1.value[0]).value); + indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); increment_16_bit(instructions, AVR::get_register_number(o1.value[0])); return; } @@ -756,28 +830,28 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::lds: { instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); return; } case AVR::OpCode::lsr: { - instructions.emplace_back(mos6502::OpCode::lsr, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lsr, AVR::get_register(o1_reg_num)); return; } case AVR::OpCode::andi: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::AND, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); return; } case AVR::OpCode::eor: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, AVR::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::eor, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); return; } case AVR::OpCode::sbrc: { instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); instructions.emplace_back(ASMLine::Type::Directive, new_label_name); @@ -785,7 +859,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::sbrs: { instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); instructions.emplace_back(ASMLine::Type::Directive, new_label_name); @@ -804,6 +878,11 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(mos6502::OpCode::jmp, o1); return; } + + case AVR::OpCode::sbiw: { + subtract_16_bit(instructions, o1_reg_num, atoi(o2.value.c_str())); + return; + } } throw std::runtime_error("Could not translate unhandled instruction"); @@ -1137,6 +1216,27 @@ void to_mos6502(const FromArch &i, std::vector &instructions) case ASMLine::Type::Directive: if (i.text.starts_with(".string")) { instructions.emplace_back(ASMLine::Type::Directive, ".asc " + i.text.substr(7)); + } else if (i.text.starts_with(".zero")) { + const auto count = atoi(i.text.data() + 6); + + std::string zeros; + for (int i = 0; i < count; ++i) + { + if ((i % 20) == 0) { + if (!zeros.empty()) { + instructions.emplace_back(ASMLine::Type::Directive, zeros); + zeros.clear(); + } + zeros += ".byt 0"; + } else { + zeros += ",0"; + } + } + + if (!zeros.empty()) { + instructions.emplace_back(ASMLine::Type::Directive, zeros); + } + } else { instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + i.text); } @@ -1308,6 +1408,16 @@ bool fix_overwritten_flags(std::vector &instructions) return false; } +void setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, std::vector &new_instructions) { + // set __zero_reg__ (reg 1 on AVR) to 0 + new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); + new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1)); +} + + +void +setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, [[maybe_unused]] std::vector &new_instructions) { +} template void run(std::istream &input) { @@ -1367,48 +1477,23 @@ void run(std::istream &input) { { if (i.type == ASMLine::Type::Instruction) { -// if (labels.count(i.operand1.value) != 0) { - used_labels.insert(strip_lo_hi(i.operand1.value)); - used_labels.insert(strip_lo_hi(i.operand2.value)); -// } + const auto check_label = [&](const auto &value){ + if (labels.count(value) != 0) { + used_labels.insert(value); + } + }; + + check_label(i.operand1.value); + check_label(i.operand2.value); + check_label(strip_lo_hi(i.operand1.value)); + check_label(strip_lo_hi(i.operand2.value)); } } - used_labels.erase("X"); - used_labels.erase("X+"); - used_labels.erase("-X"); - used_labels.erase("Y"); - used_labels.erase("Y+"); - used_labels.erase("-Y"); - used_labels.erase("Z"); - used_labels.erase("Z+"); - used_labels.erase("-Z"); - // remove all labels and directives that we don't need - instructions.erase( - std::remove_if(std::begin(instructions), std::end(instructions), - [&used_labels](const auto &i){ - if (i.type == ASMLine::Type::Label) { - // if (used_labels.count(i.text) == 0) { - // std::cout << "; removed label: '" << i.text << "'\n"; - // remove all unused labels that aren't 'main' - // return true; - // } - } - if (i.type == ASMLine::Type::Directive) { - // return true; - } - return false; - } - ), - std::end(instructions) - ); - - const auto new_labels = [&used_labels](){ std::map result; -// result.emplace(std::make_pair("0", "-memcpy_0")); for (const auto &l : used_labels) { auto newl = l; std::transform(newl.begin(), newl.end(), newl.begin(), [](const auto c) { return std::tolower(c); }); @@ -1456,8 +1541,10 @@ void run(std::istream &input) { std::vector new_instructions; new_instructions.emplace_back(ASMLine::Type::Directive, ".word $1000"); new_instructions.emplace_back(ASMLine::Type::Directive, "* = $1000"); + setup_target_cpu_state(instructions, new_instructions); new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); + bool skip_next_instruction = false; std::string next_label_name; for (const auto &i : instructions) From 14b3f4192e47bc8f8eacdbdf6e2f5ff17c2974d2 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Tue, 4 May 2021 23:29:48 -0600 Subject: [PATCH 08/27] Fix several CPU bugs and add several more instructions --- src/main.cpp | 156 +++++++++++++++++++++++++++++++++++++++++++++------ 1 file changed, 140 insertions(+), 16 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index 9986ff0..02772c3 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -44,23 +44,27 @@ std::string fixup_8bit_literal(const std::string &s) if (s[0] == '$') { return "#" + std::to_string(static_cast(parse_8bit_literal(s))); - } else { + } + + if (s.starts_with("0x")) { + return "#$" + s.substr(2); + } + if (s.starts_with("lo8(") && s.ends_with(")")) { return "#<" + strip_lo_hi(s); } if (s.starts_with("hi8(") && s.ends_with(")")) { return "#>" + strip_lo_hi(s); } - // todo make this a generic number check - if (s == "0") { - return "#0"; - } - if (s == "1") { - return "#1"; + + const auto is_num = std::all_of(begin(s), end(s), [](const auto c){ return (c >= '0' && c <= '9') || c == '-';}); + + if (is_num) { + return "#<" + s; } return s; - } + } struct Operand @@ -133,7 +137,9 @@ struct mos6502 : ASMLine clc, sec, bit, - jsr + jsr, + bcc, + bcs }; static bool get_is_branch(const OpCode o) { @@ -142,6 +148,8 @@ struct mos6502 : ASMLine case OpCode::bne: case OpCode::bmi: case OpCode::bpl: + case OpCode::bcc: + case OpCode::bcs: return true; case OpCode::lda: case OpCode::ldy: @@ -304,7 +312,11 @@ struct mos6502 : ASMLine return "jsr"; case OpCode::bpl: return "bpl"; - case OpCode::unknown: + case OpCode::bcc: + return "bcc"; + case OpCode::bcs: + return "bcs"; + case OpCode::unknown: return ""; }; @@ -540,7 +552,16 @@ struct AVR : ASMLine brne, rjmp, dec, - sbiw + sbiw, + push, + pop, + com, + swap, + clr, + cpse, + cpi, + brlo + }; static OpCode parse_opcode(Type t, const std::string &o) @@ -574,6 +595,15 @@ struct AVR : ASMLine if (o == "brne") return OpCode::brne; if (o == "dec") return OpCode::dec; if (o == "sbiw") return OpCode::sbiw; + if (o == "push") return OpCode::push; + if (o == "pop") return OpCode::pop; + if (o == "com") return OpCode::com; + if (o == "swap") return OpCode::swap; + if (o == "clr") return OpCode::clr; + if (o == "cpse") return OpCode::cpse; + if (o == "cpi") return OpCode::cpi; + if (o == "brlo") return OpCode::brlo; + } } throw std::runtime_error("Unknown opcode: " + o); @@ -732,6 +762,8 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode const auto translate_register_number = [](const Operand ®) { if (reg.value == "__zero_reg__") { return 1; + } else if (reg.value == "__temp_reg__") { + return 0; } else { return reg.reg_num; } @@ -849,6 +881,14 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); return; } + case AVR::OpCode::cpse: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o2_reg_num)); + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } case AVR::OpCode::sbrc: { instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); @@ -883,6 +923,60 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode subtract_16_bit(instructions, o1_reg_num, atoi(o2.value.c_str())); return; } + + case AVR::OpCode::push: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::pha); + return; + } + case AVR::OpCode::pop: { + instructions.emplace_back(mos6502::OpCode::pla); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::com: { + // We're doing this in the same way the AVR does it, to make sure the C flag is set properly + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$FF")); + instructions.emplace_back(mos6502::OpCode::sbc, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::clr: { + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::cpi: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sec); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + return; + } + case AVR::OpCode::brlo: { + instructions.emplace_back(mos6502::OpCode::bcc, o1); + return; + } + case AVR::OpCode::swap: { + // from http://www.6502.org/source/general/SWN.html + // ASL A + // ADC #$80 + // ROL A + // ASL A + // ADC #$80 + // ROL A + + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::asl); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); + instructions.emplace_back(mos6502::OpCode::rol); + instructions.emplace_back(mos6502::OpCode::asl); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); + instructions.emplace_back(mos6502::OpCode::rol); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + + return; + } } throw std::runtime_error("Could not translate unhandled instruction"); @@ -1287,7 +1381,8 @@ bool optimize(std::vector &instructions) { next_instruction(op); if (instructions[op].opcode == mos6502::OpCode::tay) { - instructions.erase(std::next(std::begin(instructions), op), std::next(std::begin(instructions), op+1)); + instructions[op] = mos6502(ASMLine::Type::Directive, + "; removed redundant tay: " + instructions[op].to_string()); return true; } } @@ -1302,12 +1397,29 @@ bool optimize(std::vector &instructions) if (instructions[next].opcode == mos6502::OpCode::lda && instructions[next].op == instructions[op].op) { - instructions.erase(std::next(std::begin(instructions), next), std::next(std::begin(instructions), next+1)); + instructions[next] = mos6502(ASMLine::Type::Directive, + "; removed redundant lda: " + instructions[next].to_string()); return true; } } } + for (size_t op = 0; op < instructions.size() - 1; ++op) { + if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) { + auto op2 = op+1; + + while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)) { + // while inside this label + if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == + instructions[op].op.value) { + instructions[op2] = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string()); + return true; + } + ++op2; + } + } + } + for (size_t op = 0; op < instructions.size() - 1; ++op) { if (instructions[op].opcode == mos6502::OpCode::lda @@ -1323,14 +1435,14 @@ bool optimize(std::vector &instructions) if (instructions[op2].opcode == mos6502::OpCode::lda && operand == instructions[op2].op) { - instructions.erase(std::next(std::begin(instructions), op2), std::next(std::begin(instructions), op2+1)); + instructions[op2] = mos6502(ASMLine::Type::Directive, + "; removed redundant lda: " + instructions[op2].to_string()); return true; } } } - return false; } @@ -1359,6 +1471,14 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); instructions[op].comment = instructions[op+1].comment = instructions[op+2].comment = comment; return true; + } else if (instructions[op].opcode == mos6502::OpCode::bcc) { + const auto comment = instructions[op].comment; + instructions[op] = mos6502(mos6502::OpCode::bcs, Operand(Operand::Type::literal, new_pos)); + instructions.insert(std::next(std::begin(instructions), op + 1), + mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); + instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); + instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; + return true; } else { throw std::runtime_error("Don't know how to reorg this branch"); } @@ -1514,7 +1634,11 @@ void run(std::istream &input) { if (i.type == ASMLine::Type::Label) { std::clog << "Looking up Label: '" << i.text << "'\n"; - i.text = new_labels.at(i.text); + if (i.text == "0") { + i.text = "-memcpy_0"; + }else { + i.text = new_labels.at(i.text); + } } if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8(")) From 1547abccab5c69def1c54bee09defbe50fdc7536 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Tue, 4 May 2021 23:31:39 -0600 Subject: [PATCH 09/27] Apply some clang-format action --- .clang-format | 98 +++ src/main.cpp | 1873 ++++++++++++++++++++++++------------------------- 2 files changed, 1033 insertions(+), 938 deletions(-) create mode 100644 .clang-format diff --git a/.clang-format b/.clang-format new file mode 100644 index 0000000..4ede542 --- /dev/null +++ b/.clang-format @@ -0,0 +1,98 @@ +AccessModifierOffset: -2 +AlignAfterOpenBracket: DontAlign +AlignConsecutiveAssignments: false +AlignConsecutiveDeclarations: false +AlignEscapedNewlines: Left +AlignOperands: true +AlignTrailingComments: false +AllowAllParametersOfDeclarationOnNextLine: false +AllowShortBlocksOnASingleLine: true +AllowShortCaseLabelsOnASingleLine: false +AllowShortFunctionsOnASingleLine: All +AllowShortIfStatementsOnASingleLine: true +AllowShortLoopsOnASingleLine: true +AlwaysBreakAfterDefinitionReturnType: None +AlwaysBreakAfterReturnType: None +AlwaysBreakBeforeMultilineStrings: true +AlwaysBreakTemplateDeclarations: false +BinPackArguments: false +BinPackParameters: false +BraceWrapping: + AfterClass: true + AfterControlStatement: false + AfterEnum: false + AfterFunction: true + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: true + AfterUnion: false + BeforeCatch: false + BeforeElse: false + IndentBraces: false + SplitEmptyFunction: false + SplitEmptyNamespace: true + SplitEmptyRecord: true +BreakAfterJavaFieldAnnotations: true +BreakBeforeBinaryOperators: NonAssignment +BreakBeforeBraces: Custom +BreakBeforeInheritanceComma: true +BreakBeforeTernaryOperators: true +BreakConstructorInitializers: BeforeColon +BreakConstructorInitializersBeforeComma: false +BreakStringLiterals: true +ColumnLimit: 0 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false +ConstructorInitializerAllOnOneLineOrOnePerLine: false +ConstructorInitializerIndentWidth: 2 +ContinuationIndentWidth: 2 +Cpp11BracedListStyle: false +DerivePointerAlignment: false +DisableFormat: false +ExperimentalAutoDetectBinPacking: true +FixNamespaceComments: true +ForEachMacros: +- foreach +- Q_FOREACH +- BOOST_FOREACH +IncludeCategories: +- Priority: 2 + Regex: ^"(llvm|llvm-c|clang|clang-c)/ +- Priority: 3 + Regex: ^(<|"(gtest|gmock|isl|json)/) +- Priority: 1 + Regex: .* +IncludeIsMainRegex: (Test)?$ +IndentCaseLabels: false +IndentWidth: 2 +IndentWrappedFunctionNames: true +JavaScriptQuotes: Leave +JavaScriptWrapImports: true +KeepEmptyLinesAtTheStartOfBlocks: true +Language: Cpp +MacroBlockBegin: '' +MacroBlockEnd: '' +MaxEmptyLinesToKeep: 2 +NamespaceIndentation: Inner +ObjCBlockIndentWidth: 7 +ObjCSpaceAfterProperty: true +ObjCSpaceBeforeProtocolList: false +PointerAlignment: Right +ReflowComments: true +SortIncludes: false +SortUsingDeclarations: false +SpaceAfterCStyleCast: false +SpaceAfterTemplateKeyword: false +SpaceBeforeAssignmentOperators: true +SpaceBeforeParens: ControlStatements +SpaceInEmptyParentheses: false +SpacesBeforeTrailingComments: 0 +SpacesInAngles: false +SpacesInCStyleCastParentheses: false +SpacesInContainerLiterals: true +SpacesInParentheses: false +SpacesInSquareBrackets: false +Standard: Cpp11 +TabWidth: 8 +UseTab: Never + diff --git a/src/main.cpp b/src/main.cpp index 02772c3..8c1be3f 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -10,8 +10,7 @@ struct ASMLine { - enum class Type - { + enum class Type { Label, Instruction, Directive @@ -32,7 +31,7 @@ int parse_8bit_literal(const std::string &s) std::string strip_lo_hi(const std::string &s) { if ((s.starts_with("lo8(") || s.starts_with("hi8(")) - && s.ends_with(")")) { + && s.ends_with(")")) { return s.substr(4, s.size() - 5); } @@ -41,8 +40,7 @@ std::string strip_lo_hi(const std::string &s) std::string fixup_8bit_literal(const std::string &s) { - if (s[0] == '$') - { + if (s[0] == '$') { return "#" + std::to_string(static_cast(parse_8bit_literal(s))); } @@ -50,27 +48,25 @@ std::string fixup_8bit_literal(const std::string &s) return "#$" + s.substr(2); } - if (s.starts_with("lo8(") && s.ends_with(")")) { - return "#<" + strip_lo_hi(s); - } - if (s.starts_with("hi8(") && s.ends_with(")")) { - return "#>" + strip_lo_hi(s); - } + if (s.starts_with("lo8(") && s.ends_with(")")) { + return "#<" + strip_lo_hi(s); + } + if (s.starts_with("hi8(") && s.ends_with(")")) { + return "#>" + strip_lo_hi(s); + } - const auto is_num = std::all_of(begin(s), end(s), [](const auto c){ return (c >= '0' && c <= '9') || c == '-';}); + const auto is_num = std::all_of(begin(s), end(s), [](const auto c) { return (c >= '0' && c <= '9') || c == '-'; }); - if (is_num) { - return "#<" + s; - } - - return s; + if (is_num) { + return "#<" + s; + } + return s; } struct Operand { - enum class Type - { + enum class Type { empty, literal, reg /*ister*/ @@ -82,7 +78,8 @@ struct Operand Operand() = default; - bool operator==(const Operand &other) const { + bool operator==(const Operand &other) const + { return type == other.type && reg_num == other.reg_num && value == other.value; } @@ -102,8 +99,7 @@ struct Operand struct mos6502 : ASMLine { - enum class OpCode - { + enum class OpCode { unknown, lda, asl, @@ -142,87 +138,89 @@ struct mos6502 : ASMLine bcs }; - static bool get_is_branch(const OpCode o) { + static bool get_is_branch(const OpCode o) + { switch (o) { - case OpCode::beq: - case OpCode::bne: - case OpCode::bmi: - case OpCode::bpl: - case OpCode::bcc: - case OpCode::bcs: - return true; - case OpCode::lda: - case OpCode::ldy: - case OpCode::tay: - case OpCode::tya: - case OpCode::cpy: - case OpCode::eor: - case OpCode::sta: - case OpCode::sty: - case OpCode::pha: - case OpCode::pla: - case OpCode::php: - case OpCode::plp: - case OpCode::lsr: - case OpCode::ror: - case OpCode::AND: - case OpCode::inc: - case OpCode::dec: - case OpCode::ORA: - case OpCode::cmp: - case OpCode::jmp: - case OpCode::jsr: - case OpCode::adc: - case OpCode::sbc: - case OpCode::rts: - case OpCode::clc: - case OpCode::sec: - case OpCode::bit: - case OpCode::asl: - case OpCode::rol: - case OpCode::unknown: - break; + case OpCode::beq: + case OpCode::bne: + case OpCode::bmi: + case OpCode::bpl: + case OpCode::bcc: + case OpCode::bcs: + return true; + case OpCode::lda: + case OpCode::ldy: + case OpCode::tay: + case OpCode::tya: + case OpCode::cpy: + case OpCode::eor: + case OpCode::sta: + case OpCode::sty: + case OpCode::pha: + case OpCode::pla: + case OpCode::php: + case OpCode::plp: + case OpCode::lsr: + case OpCode::ror: + case OpCode::AND: + case OpCode::inc: + case OpCode::dec: + case OpCode::ORA: + case OpCode::cmp: + case OpCode::jmp: + case OpCode::jsr: + case OpCode::adc: + case OpCode::sbc: + case OpCode::rts: + case OpCode::clc: + case OpCode::sec: + case OpCode::bit: + case OpCode::asl: + case OpCode::rol: + case OpCode::unknown: + break; } return false; } - static bool get_is_comparison(const OpCode o) { + static bool get_is_comparison(const OpCode o) + { switch (o) { - case OpCode::cmp: - case OpCode::cpy: - case OpCode::bit: - return true; - case OpCode::lda: - case OpCode::ldy: - case OpCode::tay: - case OpCode::tya: - case OpCode::eor: - case OpCode::sta: - case OpCode::sty: - case OpCode::pha: - case OpCode::pla: - case OpCode::php: - case OpCode::plp: - case OpCode::lsr: - case OpCode::ror: - case OpCode::AND: - case OpCode::inc: - case OpCode::dec: - case OpCode::ORA: - case OpCode::jmp: - case OpCode::jsr: - case OpCode::bne: - case OpCode::bmi: - case OpCode::beq: - case OpCode::adc: - case OpCode::sbc: - case OpCode::rts: - case OpCode::clc: - case OpCode::sec: - case OpCode::rol: - case OpCode::asl: - case OpCode::unknown: - break; + case OpCode::cmp: + case OpCode::cpy: + case OpCode::bit: + return true; + case OpCode::lda: + case OpCode::ldy: + case OpCode::tay: + case OpCode::tya: + case OpCode::eor: + case OpCode::sta: + case OpCode::sty: + case OpCode::pha: + case OpCode::pla: + case OpCode::php: + case OpCode::plp: + case OpCode::lsr: + case OpCode::ror: + case OpCode::AND: + case OpCode::inc: + case OpCode::dec: + case OpCode::ORA: + case OpCode::jmp: + case OpCode::jsr: + case OpCode::bne: + case OpCode::bmi: + case OpCode::beq: + case OpCode::adc: + case OpCode::sbc: + case OpCode::rts: + case OpCode::clc: + case OpCode::sec: + case OpCode::rol: + case OpCode::asl: + case OpCode::unknown: + break; } return false; } @@ -246,78 +244,78 @@ struct mos6502 : ASMLine static std::string to_string(const OpCode o) { switch (o) { - case OpCode::lda: - return "lda"; - case OpCode::asl: - return "asl"; - case OpCode::rol: - return "rol"; - case OpCode::ldy: - return "ldy"; - case OpCode::tay: - return "tay"; - case OpCode::tya: - return "tya"; - case OpCode::cpy: - return "cpy"; - case OpCode::eor: - return "eor"; - case OpCode::sta: - return "sta"; - case OpCode::sty: - return "sty"; - case OpCode::pha: - return "pha"; - case OpCode::pla: - return "pla"; - case OpCode::php: - return "php"; - case OpCode::plp: - return "plp"; - case OpCode::lsr: - return "lsr"; - case OpCode::ror: - return "ror"; - case OpCode::AND: - return "and"; - case OpCode::inc: - return "inc"; - case OpCode::dec: - return "dec"; - case OpCode::ORA: - return "ora"; - case OpCode::cmp: - return "cmp"; - case OpCode::bne: - return "bne"; - case OpCode::bmi: - return "bmi"; - case OpCode::beq: - return "beq"; - case OpCode::jmp: - return "jmp"; - case OpCode::adc: - return "adc"; - case OpCode::sbc: - return "sbc"; - case OpCode::rts: - return "rts"; - case OpCode::clc: - return "clc"; - case OpCode::sec: - return "sec"; - case OpCode::bit: - return "bit"; - case OpCode::jsr: - return "jsr"; - case OpCode::bpl: - return "bpl"; - case OpCode::bcc: - return "bcc"; - case OpCode::bcs: - return "bcs"; - case OpCode::unknown: - return ""; + case OpCode::lda: + return "lda"; + case OpCode::asl: + return "asl"; + case OpCode::rol: + return "rol"; + case OpCode::ldy: + return "ldy"; + case OpCode::tay: + return "tay"; + case OpCode::tya: + return "tya"; + case OpCode::cpy: + return "cpy"; + case OpCode::eor: + return "eor"; + case OpCode::sta: + return "sta"; + case OpCode::sty: + return "sty"; + case OpCode::pha: + return "pha"; + case OpCode::pla: + return "pla"; + case OpCode::php: + return "php"; + case OpCode::plp: + return "plp"; + case OpCode::lsr: + return "lsr"; + case OpCode::ror: + return "ror"; + case OpCode::AND: + return "and"; + case OpCode::inc: + return "inc"; + case OpCode::dec: + return "dec"; + case OpCode::ORA: + return "ora"; + case OpCode::cmp: + return "cmp"; + case OpCode::bne: + return "bne"; + case OpCode::bmi: + return "bmi"; + case OpCode::beq: + return "beq"; + case OpCode::jmp: + return "jmp"; + case OpCode::adc: + return "adc"; + case OpCode::sbc: + return "sbc"; + case OpCode::rts: + return "rts"; + case OpCode::clc: + return "clc"; + case OpCode::sec: + return "sec"; + case OpCode::bit: + return "bit"; + case OpCode::jsr: + return "jsr"; + case OpCode::bpl: + return "bpl"; + case OpCode::bcc: + return "bcc"; + case OpCode::bcs: + return "bcs"; + case OpCode::unknown: + return ""; }; return ""; @@ -326,14 +324,13 @@ struct mos6502 : ASMLine std::string to_string() const { switch (type) { - case ASMLine::Type::Label: - return text; // + ':'; - case ASMLine::Type::Directive: - case ASMLine::Type::Instruction: - { - const std::string line = '\t' + text + ' ' + op.value; - return line + std::string(static_cast(std::max(15 - static_cast(line.size()), 1)), ' ') + "; " + comment; - } + case ASMLine::Type::Label: + return text;// + ':'; + case ASMLine::Type::Directive: + case ASMLine::Type::Instruction: { + const std::string line = '\t' + text + ' ' + op.value; + return line + std::string(static_cast(std::max(15 - static_cast(line.size()), 1)), ' ') + "; " + comment; + } }; throw std::runtime_error("Unable to render: " + text); } @@ -348,8 +345,7 @@ struct mos6502 : ASMLine struct i386 : ASMLine { - enum class OpCode - { + enum class OpCode { unknown, movzbl, movzwl, @@ -388,79 +384,96 @@ struct i386 : ASMLine call }; -static Operand get_register(const int reg_num, const int offset = 0) { - switch (reg_num) { + static Operand get_register(const int reg_num, const int offset = 0) + { + switch (reg_num) { // http://sta.c64.org/cbm64mem.html - case 0x00: return Operand(Operand::Type::literal, "$03"); // unused, fp->int routine pointer - case 0x01: return Operand(Operand::Type::literal, "$04"); - case 0x02: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer - case 0x03: return Operand(Operand::Type::literal, "$06"); - case 0x04: return Operand(Operand::Type::literal, "$fb"); // unused - case 0x05: return Operand(Operand::Type::literal, "$fc"); // unused - case 0x06: return Operand(Operand::Type::literal, "$fd"); // unused - case 0x07: return Operand(Operand::Type::literal, "$fe"); // unused - case 0x08: return Operand(Operand::Type::literal, "$22"); // unused - case 0x09: return Operand(Operand::Type::literal, "$23"); // unused - case 0x0A: return Operand(Operand::Type::literal, "$39"); // Current BASIC line number - case 0x0B: return Operand(Operand::Type::literal, "$3a"); // Current BASIC line number - case 0x10: return get_register(0x00 + offset); - case 0x11: return get_register(0x02 + offset); - case 0x12: return get_register(0x04 + offset); - case 0x13: return get_register(0x06 + offset); - case 0x14: return get_register(0x08 + offset); - case 0x15: return get_register(0x0A + offset); - }; - throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); -} + case 0x00: + return Operand(Operand::Type::literal, "$03");// unused, fp->int routine pointer + case 0x01: + return Operand(Operand::Type::literal, "$04"); + case 0x02: + return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer + case 0x03: + return Operand(Operand::Type::literal, "$06"); + case 0x04: + return Operand(Operand::Type::literal, "$fb");// unused + case 0x05: + return Operand(Operand::Type::literal, "$fc");// unused + case 0x06: + return Operand(Operand::Type::literal, "$fd");// unused + case 0x07: + return Operand(Operand::Type::literal, "$fe");// unused + case 0x08: + return Operand(Operand::Type::literal, "$22");// unused + case 0x09: + return Operand(Operand::Type::literal, "$23");// unused + case 0x0A: + return Operand(Operand::Type::literal, "$39");// Current BASIC line number + case 0x0B: + return Operand(Operand::Type::literal, "$3a");// Current BASIC line number + case 0x10: + return get_register(0x00 + offset); + case 0x11: + return get_register(0x02 + offset); + case 0x12: + return get_register(0x04 + offset); + case 0x13: + return get_register(0x06 + offset); + case 0x14: + return get_register(0x08 + offset); + case 0x15: + return get_register(0x0A + offset); + }; + throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); + } static OpCode parse_opcode(Type t, const std::string &o) { - switch(t) - { - case Type::Label: - return OpCode::unknown; - case Type::Directive: - return OpCode::unknown; - case Type::Instruction: - { - if (o == "movzwl") return OpCode::movzwl; - if (o == "movzbl") return OpCode::movzbl; - if (o == "shrb") return OpCode::shrb; - if (o == "shrl") return OpCode::shrl; - if (o == "xorl") return OpCode::xorl; - if (o == "andl") return OpCode::andl; - if (o == "ret") return OpCode::ret; - if (o == "movb") return OpCode::movb; - if (o == "cmpb") return OpCode::cmpb; - if (o == "movl") return OpCode::movl; - if (o == "jmp") return OpCode::jmp; - if (o == "testb") return OpCode::testb; - if (o == "incl") return OpCode::incl; - if (o == "sarl") return OpCode::sarl; - if (o == "decl") return OpCode::decl; - if (o == "jne") return OpCode::jne; - if (o == "je") return OpCode::je; - if (o == "js") return OpCode::js; - if (o == "subl") return OpCode::subl; - if (o == "subb") return OpCode::subb; - if (o == "addl") return OpCode::addl; - if (o == "addb") return OpCode::addb; - if (o == "sall") return OpCode::sall; - if (o == "orl") return OpCode::orl; - if (o == "andb") return OpCode::andb; - if (o == "orb") return OpCode::orb; - if (o == "decb") return OpCode::decb; - if (o == "incb") return OpCode::incb; - if (o == "rep") return OpCode::rep; - if (o == "notb") return OpCode::notb; - if (o == "negb") return OpCode::negb; - if (o == "sbbb") return OpCode::sbbb; - if (o == "pushl") return OpCode::pushl; - if (o == "retl") return OpCode::retl; - if (o == "call") return OpCode::call; - if (o == "calll") return OpCode::call; - } + switch (t) { + case Type::Label: + return OpCode::unknown; + case Type::Directive: + return OpCode::unknown; + case Type::Instruction: { + if (o == "movzwl") return OpCode::movzwl; + if (o == "movzbl") return OpCode::movzbl; + if (o == "shrb") return OpCode::shrb; + if (o == "shrl") return OpCode::shrl; + if (o == "xorl") return OpCode::xorl; + if (o == "andl") return OpCode::andl; + if (o == "ret") return OpCode::ret; + if (o == "movb") return OpCode::movb; + if (o == "cmpb") return OpCode::cmpb; + if (o == "movl") return OpCode::movl; + if (o == "jmp") return OpCode::jmp; + if (o == "testb") return OpCode::testb; + if (o == "incl") return OpCode::incl; + if (o == "sarl") return OpCode::sarl; + if (o == "decl") return OpCode::decl; + if (o == "jne") return OpCode::jne; + if (o == "je") return OpCode::je; + if (o == "js") return OpCode::js; + if (o == "subl") return OpCode::subl; + if (o == "subb") return OpCode::subb; + if (o == "addl") return OpCode::addl; + if (o == "addb") return OpCode::addb; + if (o == "sall") return OpCode::sall; + if (o == "orl") return OpCode::orl; + if (o == "andb") return OpCode::andb; + if (o == "orb") return OpCode::orb; + if (o == "decb") return OpCode::decb; + if (o == "incb") return OpCode::incb; + if (o == "rep") return OpCode::rep; + if (o == "notb") return OpCode::notb; + if (o == "negb") return OpCode::negb; + if (o == "sbbb") return OpCode::sbbb; + if (o == "pushl") return OpCode::pushl; + if (o == "retl") return OpCode::retl; + if (o == "call") return OpCode::call; + if (o == "calll") return OpCode::call; + } } throw std::runtime_error("Unknown opcode: " + o); } @@ -512,8 +525,8 @@ static Operand get_register(const int reg_num, const int offset = 0) { } } - i386(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1="", std::string o2="") - : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), + i386(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1 = "", std::string o2 = "") + : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), opcode(parse_opcode(t, t_opcode)), operand1(parse_operand(o1)), operand2(parse_operand(o2)) { } @@ -526,11 +539,9 @@ static Operand get_register(const int reg_num, const int offset = 0) { }; - struct AVR : ASMLine { - enum class OpCode - { + enum class OpCode { unknown, ldi, sts, @@ -566,45 +577,42 @@ struct AVR : ASMLine static OpCode parse_opcode(Type t, const std::string &o) { - switch(t) - { - case Type::Label: - return OpCode::unknown; - case Type::Directive: - return OpCode::unknown; - case Type::Instruction: - { - if (o == "ldi") return OpCode::ldi; - if (o == "sts") return OpCode::sts; - if (o == "ret") return OpCode::ret; - if (o == "mov") return OpCode::mov; - if (o == "lsl") return OpCode::lsl; - if (o == "rol") return OpCode::rol; - if (o == "rcall") return OpCode::rcall; - if (o == "ld") return OpCode::ld; - if (o == "subi") return OpCode::subi; - if (o == "sbci") return OpCode::sbci; - if (o == "st") return OpCode::st; - if (o == "lds") return OpCode::lds; - if (o == "lsr") return OpCode::lsr; - if (o == "andi") return OpCode::andi; - if (o == "eor") return OpCode::eor; - if (o == "sbrc") return OpCode::sbrc; - if (o == "rjmp") return OpCode::rjmp; - if (o == "sbrs") return OpCode::sbrs; - if (o == "brne") return OpCode::brne; - if (o == "dec") return OpCode::dec; - if (o == "sbiw") return OpCode::sbiw; - if (o == "push") return OpCode::push; - if (o == "pop") return OpCode::pop; - if (o == "com") return OpCode::com; - if (o == "swap") return OpCode::swap; - if (o == "clr") return OpCode::clr; - if (o == "cpse") return OpCode::cpse; - if (o == "cpi") return OpCode::cpi; - if (o == "brlo") return OpCode::brlo; - - } + switch (t) { + case Type::Label: + return OpCode::unknown; + case Type::Directive: + return OpCode::unknown; + case Type::Instruction: { + if (o == "ldi") return OpCode::ldi; + if (o == "sts") return OpCode::sts; + if (o == "ret") return OpCode::ret; + if (o == "mov") return OpCode::mov; + if (o == "lsl") return OpCode::lsl; + if (o == "rol") return OpCode::rol; + if (o == "rcall") return OpCode::rcall; + if (o == "ld") return OpCode::ld; + if (o == "subi") return OpCode::subi; + if (o == "sbci") return OpCode::sbci; + if (o == "st") return OpCode::st; + if (o == "lds") return OpCode::lds; + if (o == "lsr") return OpCode::lsr; + if (o == "andi") return OpCode::andi; + if (o == "eor") return OpCode::eor; + if (o == "sbrc") return OpCode::sbrc; + if (o == "rjmp") return OpCode::rjmp; + if (o == "sbrs") return OpCode::sbrs; + if (o == "brne") return OpCode::brne; + if (o == "dec") return OpCode::dec; + if (o == "sbiw") return OpCode::sbiw; + if (o == "push") return OpCode::push; + if (o == "pop") return OpCode::pop; + if (o == "com") return OpCode::com; + if (o == "swap") return OpCode::swap; + if (o == "clr") return OpCode::clr; + if (o == "cpse") return OpCode::cpse; + if (o == "cpi") return OpCode::cpi; + if (o == "brlo") return OpCode::brlo; + } } throw std::runtime_error("Unknown opcode: " + o); } @@ -622,51 +630,84 @@ struct AVR : ASMLine if (reg_name == 'Z') { return 30; } - } - static Operand get_register(const char reg_name, const int byte = 0) { + static Operand get_register(const char reg_name, const int byte = 0) + { return get_register(get_register_number(reg_name), byte); } -static Operand get_register(const int reg_num, [[maybe_unused]] const int offset = 0) { - switch (reg_num) { + static Operand get_register(const int reg_num, [[maybe_unused]] const int offset = 0) + { + switch (reg_num) { // http://sta.c64.org/cbm64mem.html - case 0: return Operand(Operand::Type::literal, "$a7"); // bit buffer for rs232 - case 1: return Operand(Operand::Type::literal, "$a8"); // counter for rs232 - case 2: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer - case 3: return Operand(Operand::Type::literal, "$06"); - case 4: return Operand(Operand::Type::literal, "$fb"); // unused - case 5: return Operand(Operand::Type::literal, "$fc"); // unused - case 6: return Operand(Operand::Type::literal, "$fd"); // unused - case 7: return Operand(Operand::Type::literal, "$fe"); // unused - case 8: return Operand(Operand::Type::literal, "$22"); // unused - case 9: return Operand(Operand::Type::literal, "$23"); // unused - case 10: return Operand(Operand::Type::literal, "$39"); // Current BASIC line number - case 11: return Operand(Operand::Type::literal, "$3a"); // Current BASIC line number - case 12: return Operand(Operand::Type::literal, "$61"); // arithmetic register #1 - case 13: return Operand(Operand::Type::literal, "$62"); - case 14: return Operand(Operand::Type::literal, "$63"); - case 15: return Operand(Operand::Type::literal, "$64"); - case 16: return Operand(Operand::Type::literal, "$65"); - case 17: return Operand(Operand::Type::literal, "$69"); // arithmetic register #2 - case 18: return Operand(Operand::Type::literal, "$6a"); - case 19: return Operand(Operand::Type::literal, "$6b"); - case 20: return Operand(Operand::Type::literal, "$6c"); - case 21: return Operand(Operand::Type::literal, "$6d"); - case 22: return Operand(Operand::Type::literal, "$57"); // arithmetic register #3 - case 23: return Operand(Operand::Type::literal, "$58"); - case 24: return Operand(Operand::Type::literal, "$59"); - case 25: return Operand(Operand::Type::literal, "$5a"); - case 26: return Operand(Operand::Type::literal, "$5b"); - case 27: return Operand(Operand::Type::literal, "$5c"); // arithmetic register #4 - case 28: return Operand(Operand::Type::literal, "$5d"); - case 29: return Operand(Operand::Type::literal, "$5e"); - case 30: return Operand(Operand::Type::literal, "$5f"); - case 31: return Operand(Operand::Type::literal, "$60"); + case 0: + return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232 + case 1: + return Operand(Operand::Type::literal, "$a8");// counter for rs232 + case 2: + return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer + case 3: + return Operand(Operand::Type::literal, "$06"); + case 4: + return Operand(Operand::Type::literal, "$fb");// unused + case 5: + return Operand(Operand::Type::literal, "$fc");// unused + case 6: + return Operand(Operand::Type::literal, "$fd");// unused + case 7: + return Operand(Operand::Type::literal, "$fe");// unused + case 8: + return Operand(Operand::Type::literal, "$22");// unused + case 9: + return Operand(Operand::Type::literal, "$23");// unused + case 10: + return Operand(Operand::Type::literal, "$39");// Current BASIC line number + case 11: + return Operand(Operand::Type::literal, "$3a");// Current BASIC line number + case 12: + return Operand(Operand::Type::literal, "$61");// arithmetic register #1 + case 13: + return Operand(Operand::Type::literal, "$62"); + case 14: + return Operand(Operand::Type::literal, "$63"); + case 15: + return Operand(Operand::Type::literal, "$64"); + case 16: + return Operand(Operand::Type::literal, "$65"); + case 17: + return Operand(Operand::Type::literal, "$69");// arithmetic register #2 + case 18: + return Operand(Operand::Type::literal, "$6a"); + case 19: + return Operand(Operand::Type::literal, "$6b"); + case 20: + return Operand(Operand::Type::literal, "$6c"); + case 21: + return Operand(Operand::Type::literal, "$6d"); + case 22: + return Operand(Operand::Type::literal, "$57");// arithmetic register #3 + case 23: + return Operand(Operand::Type::literal, "$58"); + case 24: + return Operand(Operand::Type::literal, "$59"); + case 25: + return Operand(Operand::Type::literal, "$5a"); + case 26: + return Operand(Operand::Type::literal, "$5b"); + case 27: + return Operand(Operand::Type::literal, "$5c");// arithmetic register #4 + case 28: + return Operand(Operand::Type::literal, "$5d"); + case 29: + return Operand(Operand::Type::literal, "$5e"); + case 30: + return Operand(Operand::Type::literal, "$5f"); + case 31: + return Operand(Operand::Type::literal, "$60"); + } + throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); } - throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); -} static Operand parse_operand(std::string o) @@ -682,8 +723,8 @@ static Operand get_register(const int reg_num, [[maybe_unused]] const int offset } } - AVR(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1="", std::string o2="") - : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), + AVR(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1 = "", std::string o2 = "") + : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), opcode(parse_opcode(t, t_opcode)), operand1(parse_operand(o1)), operand2(parse_operand(o2)) { } @@ -698,8 +739,7 @@ static Operand get_register(const int reg_num, [[maybe_unused]] const int offset void indirect_load(std::vector &instructions, const std::string &from_address_low_byte, const std::string &to_address) { instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, - "(" + from_address_low_byte + "), Y")); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "(" + from_address_low_byte + "), Y")); instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, to_address)); } @@ -707,8 +747,7 @@ void indirect_store(std::vector &instructions, const std::string &from_ { instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, from_address)); instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); - instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, - "(" + to_address_low_byte + "), Y") ); + instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, "(" + to_address_low_byte + "), Y")); } void fixup_16_bit_N_Z_flags(std::vector &instructions) @@ -733,7 +772,8 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) } -void subtract_16_bit(std::vector &instructions, int reg, const std::uint16_t value) { +void subtract_16_bit(std::vector &instructions, int reg, const std::uint16_t value) +{ //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); instructions.emplace_back(mos6502::OpCode::sec); instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg)); @@ -746,15 +786,16 @@ void subtract_16_bit(std::vector &instructions, int reg, const std::ui fixup_16_bit_N_Z_flags(instructions); } -void increment_16_bit(std::vector & instructions, int reg) { +void increment_16_bit(std::vector &instructions, int reg) +{ //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg)); instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#1")); instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg)); - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg+1)); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg + 1)); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#0")); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg+1)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg + 1)); } void translate_instruction(std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) @@ -772,512 +813,503 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode const auto o1_reg_num = translate_register_number(o1); const auto o2_reg_num = translate_register_number(o2); - switch(op) - { - case AVR::OpCode::dec: + switch (op) { + case AVR::OpCode::dec: + instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); + return; + case AVR::OpCode::ldi: + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + case AVR::OpCode::sts: + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, Operand(o1.type, o1.value)); + return; + case AVR::OpCode::ret: + instructions.emplace_back(mos6502::OpCode::rts); + return; + case AVR::OpCode::mov: + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + case AVR::OpCode::lsl: + instructions.emplace_back(mos6502::OpCode::asl, AVR::get_register(o1_reg_num)); + return; + case AVR::OpCode::rol: + instructions.emplace_back(mos6502::OpCode::rol, AVR::get_register(o1_reg_num)); + return; + case AVR::OpCode::rcall: + instructions.emplace_back(mos6502::OpCode::jsr, o1); + return; + case AVR::OpCode::ld: { + if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { + indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); + return; + } + if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") { + indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); + increment_16_bit(instructions, AVR::get_register_number(o2.value[0])); + return; + } + throw std::runtime_error("Unhandled ld to non-Z"); + } + case AVR::OpCode::sbci: { + // we want to utilize the carry flag, however it was set previously + // (it's really a borrow flag on the 6502) + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + fixup_16_bit_N_Z_flags(instructions); + return; + } + case AVR::OpCode::subi: { + // to do: deal with Carry bit (and other flags) nonsense from AVR + // if |x| < |y| -> x-y +carry + // for these special cases with -(1) and -(-(1)) + if (o2.value == "lo8(-(-1))") { instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); return; - case AVR::OpCode::ldi: - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - case AVR::OpCode::sts: - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, Operand(o1.type, o1.value)); - return; - case AVR::OpCode::ret: - instructions.emplace_back(mos6502::OpCode::rts); - return; - case AVR::OpCode::mov: - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - case AVR::OpCode::lsl: - instructions.emplace_back(mos6502::OpCode::asl, AVR::get_register(o1_reg_num)); - return; - case AVR::OpCode::rol: - instructions.emplace_back(mos6502::OpCode::rol, AVR::get_register(o1_reg_num)); - return; - case AVR::OpCode::rcall: - instructions.emplace_back(mos6502::OpCode::jsr, o1); - return; - case AVR::OpCode::ld: - { - if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { - indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); - return; - } - if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") { - indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); - increment_16_bit(instructions, AVR::get_register_number(o2.value[0])); - return; - } - throw std::runtime_error("Unhandled ld to non-Z"); } - case AVR::OpCode::sbci: - { - // we want to utilize the carry flag, however it was set previously - // (it's really a borrow flag on the 6502) - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - fixup_16_bit_N_Z_flags(instructions); - return; - } - case AVR::OpCode::subi: - { - // to do: deal with Carry bit (and other flags) nonsense from AVR - // if |x| < |y| -> x-y +carry - // for these special cases with -(1) and -(-(1)) - if (o2.value == "lo8(-(-1))") { - instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); - return; - } - if (o2.value == "lo8(-(1))") { - instructions.emplace_back(mos6502::OpCode::inc, AVR::get_register(o1_reg_num)); - return; - } - - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - // have to set carry flag, since it gets inverted by sbc - instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - // temporarily store lower order (not carried substraction) byte into Y for checking - // later if this is a two byte subtraction operation - instructions.emplace_back(mos6502::OpCode::tay); - return; - } - case AVR::OpCode::st: { - if (o1.value == "Z" || o1.value == "Y"||o1.value == "X") { - indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); - return; - } - if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") { - indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); - increment_16_bit(instructions, AVR::get_register_number(o1.value[0])); - return; - } - throw std::runtime_error("Unhandled st"); - } - case AVR::OpCode::lds: { - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::lsr: { - instructions.emplace_back(mos6502::OpCode::lsr, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::andi: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::AND, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::eor: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::cpse: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o2_reg_num)); - std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); - instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); - instructions.emplace_back(ASMLine::Type::Directive, new_label_name); - return; - } - case AVR::OpCode::sbrc: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); - std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); - instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); - instructions.emplace_back(ASMLine::Type::Directive, new_label_name); - return; - } - case AVR::OpCode::sbrs: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); - std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); - instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); - instructions.emplace_back(ASMLine::Type::Directive, new_label_name); - return; - } - case AVR::OpCode::brne: { - if (o1.value == "0b") { - instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, "memcpy_0")); - } else { - instructions.emplace_back(mos6502::OpCode::bne, o1); - } + if (o2.value == "lo8(-(1))") { + instructions.emplace_back(mos6502::OpCode::inc, AVR::get_register(o1_reg_num)); return; } - case AVR::OpCode::rjmp: { - instructions.emplace_back(mos6502::OpCode::jmp, o1); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + // have to set carry flag, since it gets inverted by sbc + instructions.emplace_back(mos6502::OpCode::sec); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + // temporarily store lower order (not carried substraction) byte into Y for checking + // later if this is a two byte subtraction operation + instructions.emplace_back(mos6502::OpCode::tay); + return; + } + case AVR::OpCode::st: { + if (o1.value == "Z" || o1.value == "Y" || o1.value == "X") { + indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); return; } + if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") { + indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); + increment_16_bit(instructions, AVR::get_register_number(o1.value[0])); + return; + } + throw std::runtime_error("Unhandled st"); + } + case AVR::OpCode::lds: { + instructions.emplace_back(mos6502::OpCode::lda, o2); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::lsr: { + instructions.emplace_back(mos6502::OpCode::lsr, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::andi: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::AND, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::eor: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::eor, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::cpse: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o2_reg_num)); + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } + case AVR::OpCode::sbrc: { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } + case AVR::OpCode::sbrs: { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); + instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } + case AVR::OpCode::brne: { + if (o1.value == "0b") { + instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, "memcpy_0")); + } else { + instructions.emplace_back(mos6502::OpCode::bne, o1); + } + return; + } - case AVR::OpCode::sbiw: { - subtract_16_bit(instructions, o1_reg_num, atoi(o2.value.c_str())); - return; - } + case AVR::OpCode::rjmp: { + instructions.emplace_back(mos6502::OpCode::jmp, o1); + return; + } - case AVR::OpCode::push: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::pha); - return; - } - case AVR::OpCode::pop: { - instructions.emplace_back(mos6502::OpCode::pla); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::com: { - // We're doing this in the same way the AVR does it, to make sure the C flag is set properly - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$FF")); - instructions.emplace_back(mos6502::OpCode::sbc, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::clr: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); - return; - } - case AVR::OpCode::cpi: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); - return; - } - case AVR::OpCode::brlo: { - instructions.emplace_back(mos6502::OpCode::bcc, o1); - return; - } - case AVR::OpCode::swap: { - // from http://www.6502.org/source/general/SWN.html - // ASL A - // ADC #$80 - // ROL A - // ASL A - // ADC #$80 - // ROL A + case AVR::OpCode::sbiw: { + subtract_16_bit(instructions, o1_reg_num, atoi(o2.value.c_str())); + return; + } - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::asl); - instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); - instructions.emplace_back(mos6502::OpCode::rol); - instructions.emplace_back(mos6502::OpCode::asl); - instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); - instructions.emplace_back(mos6502::OpCode::rol); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + case AVR::OpCode::push: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::pha); + return; + } + case AVR::OpCode::pop: { + instructions.emplace_back(mos6502::OpCode::pla); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::com: { + // We're doing this in the same way the AVR does it, to make sure the C flag is set properly + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$FF")); + instructions.emplace_back(mos6502::OpCode::sbc, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::clr: { + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::cpi: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sec); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + return; + } + case AVR::OpCode::brlo: { + instructions.emplace_back(mos6502::OpCode::bcc, o1); + return; + } + case AVR::OpCode::swap: { + // from http://www.6502.org/source/general/SWN.html + // ASL A + // ADC #$80 + // ROL A + // ASL A + // ADC #$80 + // ROL A - return; - } + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::asl); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); + instructions.emplace_back(mos6502::OpCode::rol); + instructions.emplace_back(mos6502::OpCode::asl); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); + instructions.emplace_back(mos6502::OpCode::rol); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + + return; + } } throw std::runtime_error("Could not translate unhandled instruction"); } - + void translate_instruction(std::vector &instructions, const i386::OpCode op, const Operand &o1, const Operand &o2) { - switch(op) - { - case i386::OpCode::ret: - instructions.emplace_back(mos6502::OpCode::rts); - break; - case i386::OpCode::retl: - /// \todo I don't know if this is completely correct for retl translation - instructions.emplace_back(mos6502::OpCode::rts); - break; - case i386::OpCode::movl: - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); - } else { - throw std::runtime_error("Cannot translate movl instruction"); - } - break; - case i386::OpCode::xorl: - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg - && o1.reg_num == o2.reg_num) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); - } else { - throw std::runtime_error("Cannot translate xorl instruction"); - } - break; - case i386::OpCode::movb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else { - throw std::runtime_error("Cannot translate movb instruction"); - } - break; - case i386::OpCode::orb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::ORA, o2); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else { - throw std::runtime_error("Cannot translate orb instruction"); - } - break; + switch (op) { + case i386::OpCode::ret: + instructions.emplace_back(mos6502::OpCode::rts); + break; + case i386::OpCode::retl: + /// \todo I don't know if this is completely correct for retl translation + instructions.emplace_back(mos6502::OpCode::rts); + break; + case i386::OpCode::movl: + if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); + } else { + throw std::runtime_error("Cannot translate movl instruction"); + } + break; + case i386::OpCode::xorl: + if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg + && o1.reg_num == o2.reg_num) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); + } else { + throw std::runtime_error("Cannot translate xorl instruction"); + } + break; + case i386::OpCode::movb: + if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + } else { + throw std::runtime_error("Cannot translate movb instruction"); + } + break; + case i386::OpCode::orb: + if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::ORA, o2); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + } else { + throw std::runtime_error("Cannot translate orb instruction"); + } + break; - case i386::OpCode::movzbl: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, o1); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else { - throw std::runtime_error("Cannot translate movzbl instruction"); - } - break; - case i386::OpCode::shrb: - if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { - const auto do_shift = [&instructions](const int reg_num) { - instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num)); - }; + case i386::OpCode::movzbl: + if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, o1); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + } else { + throw std::runtime_error("Cannot translate movzbl instruction"); + } + break; + case i386::OpCode::shrb: + if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { + const auto do_shift = [&instructions](const int reg_num) { + instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num)); + }; - if (o1.type == Operand::Type::literal) { - const auto count = parse_8bit_literal(o1.value); - for (int i = 0; i < count; ++i) { - do_shift(o2.reg_num); - } - } else { - do_shift(o1.reg_num); + if (o1.type == Operand::Type::literal) { + const auto count = parse_8bit_literal(o1.value); + for (int i = 0; i < count; ++i) { + do_shift(o2.reg_num); } } else { - throw std::runtime_error("Cannot translate shrb instruction"); + do_shift(o1.reg_num); } - break; - case i386::OpCode::shrl: - if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { - const auto do_shift = [&instructions](const int reg_num) { - instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::ror, i386::get_register(reg_num)); - }; + } else { + throw std::runtime_error("Cannot translate shrb instruction"); + } + break; + case i386::OpCode::shrl: + if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { + const auto do_shift = [&instructions](const int reg_num) { + instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::ror, i386::get_register(reg_num)); + }; - if (o1.type == Operand::Type::literal) { - const auto count = parse_8bit_literal(o1.value); - for (int i = 0; i < count; ++i) { - do_shift(o2.reg_num); - } - } else { - do_shift(o1.reg_num); + if (o1.type == Operand::Type::literal) { + const auto count = parse_8bit_literal(o1.value); + for (int i = 0; i < count; ++i) { + do_shift(o2.reg_num); } } else { - throw std::runtime_error("Cannot translate shrl instruction"); + do_shift(o1.reg_num); } - break; - case i386::OpCode::testb: - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) { - // this just tests the register for 0 - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); -// instructions.emplace_back(mos6502::OpCode::bit, Operand(Operand::Type::literal, "#$00")); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - // ands the values - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - // ands the values - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - // ands the values - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::bit, o2); - } else { - throw std::runtime_error("Cannot translate testb instruction"); - } - break; - case i386::OpCode::decb: - if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::dec, i386::get_register(o1.reg_num)); - } else { - instructions.emplace_back(mos6502::OpCode::dec, o1); - } - break; - case i386::OpCode::incb: - if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); - } else { - instructions.emplace_back(mos6502::OpCode::inc, o1); - } - break; - case i386::OpCode::jne: - instructions.emplace_back(mos6502::OpCode::bne, o1); - break; - case i386::OpCode::je: - instructions.emplace_back(mos6502::OpCode::beq, o1); - break; - case i386::OpCode::js: - instructions.emplace_back(mos6502::OpCode::bmi, o1); - break; - case i386::OpCode::jmp: - instructions.emplace_back(mos6502::OpCode::jmp, o1); - break; - case i386::OpCode::addb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::adc, o2); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::adc, o2); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else { - throw std::runtime_error("Cannot translate addb instruction"); - } - break; - case i386::OpCode::cmpb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); - } else { - throw std::runtime_error("Cannot translate cmpb instruction"); - } - break; - case i386::OpCode::andb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - const auto reg = i386::get_register(o2.reg_num); - instructions.emplace_back(mos6502::OpCode::lda, reg); - instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, reg); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - const auto reg = i386::get_register(o2.reg_num); - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else { - throw std::runtime_error("Cannot translate andb instruction"); - } - break; - case i386::OpCode::negb: - if (o1.type == Operand::Type::reg) { - // perform a two's complement of the register location - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); - } else { - throw std::runtime_error("Cannot translate negb instruction"); - } - break; - case i386::OpCode::notb: - if (o1.type == Operand::Type::reg) { - // exclusive or against 0xff to perform a logical not - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); - } else { - throw std::runtime_error("Cannot translate notb instruction"); - } - break; - case i386::OpCode::subb: - // DEST <- DEST - SRC - // o2 = o2 - o1 - // Ensure that we set the carry flag before performing the subtraction - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::sbc, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else { - throw std::runtime_error("Cannot translate subb instruction"); - } - break; - case i386::OpCode::pushl: - if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::pha); - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::pha); - } else { - throw std::runtime_error("Cannot translate pushl instruction"); - } - break; + } else { + throw std::runtime_error("Cannot translate shrl instruction"); + } + break; + case i386::OpCode::testb: + if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) { + // this just tests the register for 0 + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + // instructions.emplace_back(mos6502::OpCode::bit, Operand(Operand::Type::literal, "#$00")); + } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { + // ands the values + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + // ands the values + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { + // ands the values + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::bit, o2); + } else { + throw std::runtime_error("Cannot translate testb instruction"); + } + break; + case i386::OpCode::decb: + if (o1.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::dec, i386::get_register(o1.reg_num)); + } else { + instructions.emplace_back(mos6502::OpCode::dec, o1); + } + break; + case i386::OpCode::incb: + if (o1.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); + } else { + instructions.emplace_back(mos6502::OpCode::inc, o1); + } + break; + case i386::OpCode::jne: + instructions.emplace_back(mos6502::OpCode::bne, o1); + break; + case i386::OpCode::je: + instructions.emplace_back(mos6502::OpCode::beq, o1); + break; + case i386::OpCode::js: + instructions.emplace_back(mos6502::OpCode::bmi, o1); + break; + case i386::OpCode::jmp: + instructions.emplace_back(mos6502::OpCode::jmp, o1); + break; + case i386::OpCode::addb: + if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::adc, o2); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::adc, o2); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else { + throw std::runtime_error("Cannot translate addb instruction"); + } + break; + case i386::OpCode::cmpb: + if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, o2); + instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); + instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); + } else { + throw std::runtime_error("Cannot translate cmpb instruction"); + } + break; + case i386::OpCode::andb: + if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { + const auto reg = i386::get_register(o2.reg_num); + instructions.emplace_back(mos6502::OpCode::lda, reg); + instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::sta, reg); + } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { + const auto reg = i386::get_register(o2.reg_num); + instructions.emplace_back(mos6502::OpCode::lda, o2); + instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else { + throw std::runtime_error("Cannot translate andb instruction"); + } + break; + case i386::OpCode::negb: + if (o1.type == Operand::Type::reg) { + // perform a two's complement of the register location + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); + } else { + throw std::runtime_error("Cannot translate negb instruction"); + } + break; + case i386::OpCode::notb: + if (o1.type == Operand::Type::reg) { + // exclusive or against 0xff to perform a logical not + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); + } else { + throw std::runtime_error("Cannot translate notb instruction"); + } + break; + case i386::OpCode::subb: + // DEST <- DEST - SRC + // o2 = o2 - o1 + // Ensure that we set the carry flag before performing the subtraction + if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { + instructions.emplace_back(mos6502::OpCode::lda, o2); + instructions.emplace_back(mos6502::OpCode::sec); + instructions.emplace_back(mos6502::OpCode::sbc, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, o2); + } else { + throw std::runtime_error("Cannot translate subb instruction"); + } + break; + case i386::OpCode::pushl: + if (o1.type == Operand::Type::reg) { + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); + instructions.emplace_back(mos6502::OpCode::pha); + instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); + instructions.emplace_back(mos6502::OpCode::pha); + } else { + throw std::runtime_error("Cannot translate pushl instruction"); + } + break; - case i386::OpCode::sbbb: - // DEST <- (DEST – (SRC + CF)) - // o2 <- (o2 - (o1 + cf)) - // if o1 and o2 are the same we get - // o2 <- (o2 - (o2 + cf)) - // o2 <- -cf - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg - && o1.reg_num == o2.reg_num) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); // reset a - instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#$00")); // subtract out the carry flag - instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); // invert the bits - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); // place the value - } else { - throw std::runtime_error("Cannot translate sbbb instruction"); - } - break; + case i386::OpCode::sbbb: + // DEST <- (DEST – (SRC + CF)) + // o2 <- (o2 - (o1 + cf)) + // if o1 and o2 are the same we get + // o2 <- (o2 - (o2 + cf)) + // o2 <- -cf + if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg + && o1.reg_num == o2.reg_num) { + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00"));// reset a + instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#$00"));// subtract out the carry flag + instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff"));// invert the bits + instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));// place the value + } else { + throw std::runtime_error("Cannot translate sbbb instruction"); + } + break; - case i386::OpCode::call: - instructions.emplace_back(mos6502::OpCode::jsr, o1); - break; - - default: - throw std::runtime_error("Cannot translate unhandled instruction"); + case i386::OpCode::call: + instructions.emplace_back(mos6502::OpCode::jsr, o1); + break; + default: + throw std::runtime_error("Cannot translate unhandled instruction"); } - } -enum class LogLevel -{ +enum class LogLevel { Warning, Error }; std::string to_string(const LogLevel ll) { - switch (ll) - { - case LogLevel::Warning: - return "warning"; - case LogLevel::Error: - return "error"; + switch (ll) { + case LogLevel::Warning: + return "warning"; + case LogLevel::Error: + return "error"; } return "unknown"; } @@ -1291,70 +1323,66 @@ void log(LogLevel ll, const FromArch &i, const std::string &message) void log(LogLevel ll, const int line_no, const std::string &line, const std::string &message) { - std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; + std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; } template void to_mos6502(const FromArch &i, std::vector &instructions) { try { - switch(i.type) - { - case ASMLine::Type::Label: - if (i.text == "0") { - instructions.emplace_back(i.type, "-memcpy_0"); - } else { - instructions.emplace_back(i.type, i.text); - } - return; - case ASMLine::Type::Directive: - if (i.text.starts_with(".string")) { - instructions.emplace_back(ASMLine::Type::Directive, ".asc " + i.text.substr(7)); - } else if (i.text.starts_with(".zero")) { - const auto count = atoi(i.text.data() + 6); + switch (i.type) { + case ASMLine::Type::Label: + if (i.text == "0") { + instructions.emplace_back(i.type, "-memcpy_0"); + } else { + instructions.emplace_back(i.type, i.text); + } + return; + case ASMLine::Type::Directive: + if (i.text.starts_with(".string")) { + instructions.emplace_back(ASMLine::Type::Directive, ".asc " + i.text.substr(7)); + } else if (i.text.starts_with(".zero")) { + const auto count = atoi(i.text.data() + 6); - std::string zeros; - for (int i = 0; i < count; ++i) - { - if ((i % 20) == 0) { - if (!zeros.empty()) { - instructions.emplace_back(ASMLine::Type::Directive, zeros); - zeros.clear(); - } - zeros += ".byt 0"; - } else { - zeros += ",0"; + std::string zeros; + for (int i = 0; i < count; ++i) { + if ((i % 20) == 0) { + if (!zeros.empty()) { + instructions.emplace_back(ASMLine::Type::Directive, zeros); + zeros.clear(); } + zeros += ".byt 0"; + } else { + zeros += ",0"; } - - if (!zeros.empty()) { - instructions.emplace_back(ASMLine::Type::Directive, zeros); - } - - } else { - instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + i.text); - } - return; - case ASMLine::Type::Instruction: - const auto head = instructions.size(); - - try { - translate_instruction(instructions, i.opcode, i.operand1, i.operand2); - } catch (const std::exception &e) { - instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + i.text + "' " + e.what()); - log(LogLevel::Error, i, e.what()); } - auto text = i.line_text; - if (text[0] == '\t') { - text.erase(0, 1); + if (!zeros.empty()) { + instructions.emplace_back(ASMLine::Type::Directive, zeros); } - for_each(std::next(instructions.begin(), head), instructions.end(), - [ text ](auto &ins){ - ins.comment = text; - } - ); - return; + + } else { + instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + i.text); + } + return; + case ASMLine::Type::Instruction: + const auto head = instructions.size(); + + try { + translate_instruction(instructions, i.opcode, i.operand1, i.operand2); + } catch (const std::exception &e) { + instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + i.text + "' " + e.what()); + log(LogLevel::Error, i, e.what()); + } + + auto text = i.line_text; + if (text[0] == '\t') { + text.erase(0, 1); + } + for_each(std::next(instructions.begin(), head), instructions.end(), [text](auto &ins) { + ins.comment = text; + }); + return; } } catch (const std::exception &e) { log(LogLevel::Error, i, e.what()); @@ -1374,31 +1402,26 @@ bool optimize(std::vector &instructions) return i; }; - for (size_t op = 0; op < instructions.size() - 1; ++op) - { + for (size_t op = 0; op < instructions.size() - 1; ++op) { // look for a transfer of Y -> A immediately followed by A -> Y - if (instructions[op].opcode == mos6502::OpCode::tya) - { + if (instructions[op].opcode == mos6502::OpCode::tya) { next_instruction(op); if (instructions[op].opcode == mos6502::OpCode::tay) { instructions[op] = mos6502(ASMLine::Type::Directive, - "; removed redundant tay: " + instructions[op].to_string()); + "; removed redundant tay: " + instructions[op].to_string()); return true; } } } - for (size_t op = 0; op < instructions.size() - 1; ++op) - { + for (size_t op = 0; op < instructions.size() - 1; ++op) { // look for a store A -> loc immediately followed by loc -> A - if (instructions[op].opcode == mos6502::OpCode::sta) - { + if (instructions[op].opcode == mos6502::OpCode::sta) { const auto next = next_instruction(op); if (instructions[next].opcode == mos6502::OpCode::lda - && instructions[next].op == instructions[op].op) - { + && instructions[next].op == instructions[op].op) { instructions[next] = mos6502(ASMLine::Type::Directive, - "; removed redundant lda: " + instructions[next].to_string()); + "; removed redundant lda: " + instructions[next].to_string()); return true; } } @@ -1406,12 +1429,11 @@ bool optimize(std::vector &instructions) for (size_t op = 0; op < instructions.size() - 1; ++op) { if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) { - auto op2 = op+1; + auto op2 = op + 1; while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)) { // while inside this label - if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == - instructions[op].op.value) { + if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == instructions[op].op.value) { instructions[op2] = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string()); return true; } @@ -1420,26 +1442,21 @@ bool optimize(std::vector &instructions) } } - for (size_t op = 0; op < instructions.size() - 1; ++op) - { + for (size_t op = 0; op < instructions.size() - 1; ++op) { if (instructions[op].opcode == mos6502::OpCode::lda - && instructions[op].op.type == Operand::Type::literal) - { + && instructions[op].op.type == Operand::Type::literal) { const auto operand = instructions[op].op; - auto op2 = op+1; + auto op2 = op + 1; // look for multiple stores of the same value - while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta - || instructions[op2].type == ASMLine::Type::Directive)) { + while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) { ++op2; } if (instructions[op2].opcode == mos6502::OpCode::lda - && operand == instructions[op2].op) - { + && operand == instructions[op2].op) { instructions[op2] = mos6502(ASMLine::Type::Directive, - "; removed redundant lda: " + instructions[op2].to_string()); + "; removed redundant lda: " + instructions[op2].to_string()); return true; } - } } @@ -1449,17 +1466,14 @@ bool optimize(std::vector &instructions) bool fix_long_branches(std::vector &instructions, int &branch_patch_count) { std::map labels; - for (size_t op = 0; op < instructions.size(); ++op) - { + for (size_t op = 0; op < instructions.size(); ++op) { if (instructions[op].type == ASMLine::Type::Label) { labels[instructions[op].text] = op; } } - for (size_t op = 0; op < instructions.size(); ++op) - { - if (instructions[op].is_branch && std::abs(static_cast(labels[instructions[op].op.value]) - static_cast(op)) * 3 > 255) - { + for (size_t op = 0; op < instructions.size(); ++op) { + if (instructions[op].is_branch && std::abs(static_cast(labels[instructions[op].op.value]) - static_cast(op)) * 3 > 255) { ++branch_patch_count; const auto going_to = instructions[op].op.value; const auto new_pos = "patch_" + std::to_string(branch_patch_count); @@ -1469,13 +1483,13 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou instructions[op] = mos6502(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_pos)); instructions.insert(std::next(std::begin(instructions), op + 1), mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); - instructions[op].comment = instructions[op+1].comment = instructions[op+2].comment = comment; + instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; return true; } else if (instructions[op].opcode == mos6502::OpCode::bcc) { const auto comment = instructions[op].comment; instructions[op] = mos6502(mos6502::OpCode::bcs, Operand(Operand::Type::literal, new_pos)); instructions.insert(std::next(std::begin(instructions), op + 1), - mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); + mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; return true; @@ -1494,20 +1508,18 @@ bool fix_overwritten_flags(std::vector &instructions) return false; } - for (size_t op = 0; op < instructions.size(); ++op) - { + for (size_t op = 0; op < instructions.size(); ++op) { if (instructions[op].is_comparison) { auto op2 = op + 1; while (op2 < instructions.size() && !instructions[op2].is_comparison - && !instructions[op2].is_branch) - { + && !instructions[op2].is_branch) { ++op2; } if (op2 < instructions.size() && (op2 - op) > 1 - && instructions[op2-1].opcode != mos6502::OpCode::plp) { + && instructions[op2 - 1].opcode != mos6502::OpCode::plp) { if (instructions[op2].is_comparison) { continue; } @@ -1516,11 +1528,10 @@ bool fix_overwritten_flags(std::vector &instructions) // insert a pull of processor status before the branch instructions.insert(std::next(std::begin(instructions), op2), mos6502(mos6502::OpCode::plp)); // insert a push of processor status after the comparison - instructions.insert(std::next(std::begin(instructions), op+1), mos6502(mos6502::OpCode::php)); + instructions.insert(std::next(std::begin(instructions), op + 1), mos6502(mos6502::OpCode::php)); return true; } - } } } @@ -1528,19 +1539,21 @@ bool fix_overwritten_flags(std::vector &instructions) return false; } -void setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, std::vector &new_instructions) { +void setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, std::vector &new_instructions) +{ // set __zero_reg__ (reg 1 on AVR) to 0 new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1)); } -void -setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, [[maybe_unused]] std::vector &new_instructions) { +void setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, [[maybe_unused]] std::vector &new_instructions) +{ } template -void run(std::istream &input) { +void run(std::istream &input) +{ std::regex Comment(R"(\s*\#.*)"); std::regex Label(R"(^\s*(\S+):.*)"); std::regex Directive(R"(^\s*(\..+))"); @@ -1551,17 +1564,14 @@ void run(std::istream &input) { int lineno = 0; - std::vector instructions; - while (input.good()) - { + while (input.good()) { std::string line; getline(input, line); try { std::smatch match; - if (std::regex_match(line, match, Label)) - { + if (std::regex_match(line, match, Label)) { instructions.emplace_back(lineno, line, ASMLine::Type::Label, match[1]); } else if (std::regex_match(line, match, Comment)) { // don't care about comments @@ -1584,21 +1594,18 @@ void run(std::istream &input) { std::set labels; - for (const auto &i : instructions) - { + for (const auto &i : instructions) { if (i.type == ASMLine::Type::Label) { labels.insert(i.text); } } - std::set used_labels{"main"}; + std::set used_labels{ "main" }; - for (const auto &i : instructions) - { - if (i.type == ASMLine::Type::Instruction) - { + for (const auto &i : instructions) { + if (i.type == ASMLine::Type::Instruction) { - const auto check_label = [&](const auto &value){ + const auto check_label = [&](const auto &value) { if (labels.count(value) != 0) { used_labels.insert(value); } @@ -1612,12 +1619,12 @@ void run(std::istream &input) { } const auto new_labels = - [&used_labels](){ + [&used_labels]() { std::map result; for (const auto &l : used_labels) { auto newl = l; std::transform(newl.begin(), newl.end(), newl.begin(), [](const auto c) { return std::tolower(c); }); - newl.erase(std::remove_if(newl.begin(), newl.end(), [](const auto c){ return !std::isalnum(c); }), std::end(newl)); + newl.erase(std::remove_if(newl.begin(), newl.end(), [](const auto c) { return !std::isalnum(c); }), std::end(newl)); result.emplace(std::make_pair(l, newl)); } @@ -1629,20 +1636,17 @@ void run(std::istream &input) { std::clog << "Label: '" << l.first << "': '" << l.second << "'\n"; } - for (auto &i : instructions) - { - if (i.type == ASMLine::Type::Label) - { + for (auto &i : instructions) { + if (i.type == ASMLine::Type::Label) { std::clog << "Looking up Label: '" << i.text << "'\n"; if (i.text == "0") { i.text = "-memcpy_0"; - }else { + } else { i.text = new_labels.at(i.text); } } - if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8(")) - { + if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8(")) { const auto potential_label = strip_lo_hi(i.operand2.value); const auto itr1 = new_labels.find(potential_label); if (itr1 != new_labels.end()) { @@ -1671,8 +1675,7 @@ void run(std::istream &input) { bool skip_next_instruction = false; std::string next_label_name; - for (const auto &i : instructions) - { + for (const auto &i : instructions) { to_mos6502(i, new_instructions); // intentionally copy so we don't invalidate the reference @@ -1684,33 +1687,28 @@ void run(std::istream &input) { skip_next_instruction = false; } - if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_instruction")) - { + if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_instruction")) { skip_next_instruction = true; next_label_name = last_instruction.text; new_instructions.erase(std::next(new_instructions.begin(), static_cast(last_instruction_loc))); } } - while (fix_overwritten_flags(new_instructions)) - { + while (fix_overwritten_flags(new_instructions)) { // do it however many times it takes } - while (optimize(new_instructions)) - { + while (optimize(new_instructions)) { // do it however many times it takes } int branch_patch_count = 0; - while (fix_long_branches(new_instructions, branch_patch_count)) - { + while (fix_long_branches(new_instructions, branch_patch_count)) { // do it however many times it takes } - for (const auto i : new_instructions) - { + for (const auto i : new_instructions) { std::cout << i.to_string() << '\n'; } } @@ -1744,4 +1742,3 @@ int main([[maybe_unused]] const int argc, const char *argv[]) run(input); } } - From 77c25389aa957ef87e70751554e22d24954c459e Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Wed, 5 May 2021 15:56:08 -0600 Subject: [PATCH 10/27] 16 bit counter example working --- examples/16bit_counter.cpp | 127 +++++++++++++++++++++++++++++++++++++ src/main.cpp | 111 +++++++++++++++++++++++++++----- 2 files changed, 223 insertions(+), 15 deletions(-) create mode 100644 examples/16bit_counter.cpp diff --git a/examples/16bit_counter.cpp b/examples/16bit_counter.cpp new file mode 100644 index 0000000..118899f --- /dev/null +++ b/examples/16bit_counter.cpp @@ -0,0 +1,127 @@ +#include +#include +#include +#include +#include + +enum Colors : uint8_t { WHITE = 0x01 }; + +inline volatile uint8_t &memory_loc(const uint16_t loc) { + return *reinterpret_cast(loc); +} + +inline void poke(const uint16_t loc, const uint8_t value) { + memory_loc(loc) = value; +} + +inline std::uint8_t peek(const std::uint16_t loc) { return memory_loc(loc); } + +inline void decrement_border_color() { --memory_loc(0xd020); } + +inline void increment_border_color() { ++memory_loc(0xd020); } + +inline bool joystick_down() { + uint8_t joystick_state = memory_loc(0xDC00); + return (joystick_state & 2) == 0; +} + +void use_data(std::array &data); + +inline void puts(uint8_t x, uint8_t y, std::string_view str) { + const auto start = 0x400 + (y * 40 + x); + + std::memcpy(const_cast(&memory_loc(start)), str.data(), + str.size()); +} + + +inline void put_hex(uint8_t x, uint8_t y, uint8_t value) +{ + +} + +inline void put_hex(uint8_t x, uint8_t y, uint16_t value) +{ +} + +inline void putc(uint8_t x, uint8_t y, uint8_t c) { + const auto start = 0x400 + (y * 40 + x); + poke(start, c); +} + +struct Clock { + using milliseconds = std::chrono::duration; + + // return elapsed time since last restart + [[nodiscard]] milliseconds restart() { + // stop Timer A + poke(0xDC0E, 0b00000000); + + // last value + const auto previous_value = static_cast( + peek(0xDC04) | (static_cast(peek(0xDC05)) << 8)); + + // reset timer + poke(0xDC04, 0xFF); + poke(0xDC05, 0xFF); + + // restart timer A + poke(0xDC0E, 0b00010001); + + return milliseconds{0xFFFF - previous_value}; + } + + Clock() { [[maybe_unused]] const auto value = restart(); } +}; + +int main() { + + // static constexpr std::array data{0}; + // std::memcpy(const_cast(&memory_loc(0x400)), data.data(), + // data.size()); + + /* + puts(5, 5, "hello world"); + puts(10, 10, "hellooooo world"); + + Clock game_clock{}; + */ + + std::uint16_t us_elapsed = 0; + + int y = 0; + while (true) { + // const auto us_elapsed = game_clock.restart().count(); + + for (int i = 0; i < 4; ++i) { + const auto nibble = static_cast((us_elapsed >> (i * 4)) & 0xF); + if (nibble <= 9) { + putc(6 - i, y, nibble + 48); + } else { + putc(6 - i, y, nibble - 9); + } + } + + if (y++ == 5) { + y = 0; + } + ++us_elapsed; + increment_border_color(); + } + + /* + const auto background_color = [](Colors col) { + memory_loc(0xd021) = static_cast(col); + }; + + background_color(Colors::WHITE); + + while(true) { + if (joystick_down()) { + increment_border_color(); + } else { + decrement_border_color(); + } + } + */ +} diff --git a/src/main.cpp b/src/main.cpp index 8c1be3f..7a341b6 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -107,6 +107,8 @@ struct mos6502 : ASMLine ldy, tay, tya, + tax, + txa, cpy, eor, sta, @@ -152,6 +154,8 @@ struct mos6502 : ASMLine case OpCode::ldy: case OpCode::tay: case OpCode::tya: + case OpCode::tax: + case OpCode::txa: case OpCode::cpy: case OpCode::eor: case OpCode::sta: @@ -194,6 +198,8 @@ struct mos6502 : ASMLine case OpCode::ldy: case OpCode::tay: case OpCode::tya: + case OpCode::tax: + case OpCode::txa: case OpCode::eor: case OpCode::sta: case OpCode::sty: @@ -256,6 +262,10 @@ struct mos6502 : ASMLine return "tay"; case OpCode::tya: return "tya"; + case OpCode::tax: + return "tax"; + case OpCode::txa: + return "txa"; case OpCode::cpy: return "cpy"; case OpCode::eor: @@ -571,15 +581,18 @@ struct AVR : ASMLine clr, cpse, cpi, - brlo - + brlo, + add, + adc, + cpc, + brsh, + breq }; static OpCode parse_opcode(Type t, const std::string &o) { switch (t) { case Type::Label: - return OpCode::unknown; case Type::Directive: return OpCode::unknown; case Type::Instruction: { @@ -612,6 +625,11 @@ struct AVR : ASMLine if (o == "cpse") return OpCode::cpse; if (o == "cpi") return OpCode::cpi; if (o == "brlo") return OpCode::brlo; + if (o == "add") return OpCode::add; + if (o == "adc") return OpCode::adc; + if (o == "cpc") return OpCode::cpc; + if (o == "brsh") return OpCode::brsh; + if (o == "breq") return OpCode::breq; } } throw std::runtime_error("Unknown opcode: " + o); @@ -622,14 +640,14 @@ struct AVR : ASMLine if (reg_name == 'X') { return 26; } - if (reg_name == 'Y') { return 28; } - if (reg_name == 'Z') { return 30; } + + throw std::runtime_error("Unknown register name"); } static Operand get_register(const char reg_name, const int byte = 0) @@ -763,7 +781,7 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) // if it's not 0, then branch down, we know the result is not 0 and not negative instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, set_flag_label)); // if the higher order byte is 0, test the lower order byte, which was saved for us in Y - instructions.emplace_back(mos6502::OpCode::tya); + instructions.emplace_back(mos6502::OpCode::txa); // if low order is not negative, we know it's 0 or not 0 instructions.emplace_back(mos6502::OpCode::bpl, Operand(Operand::Type::literal, set_flag_label)); // if low order byte is negative, shift right by one bit, then we'll get the proper Z/N flags @@ -782,7 +800,7 @@ void subtract_16_bit(std::vector &instructions, int reg, const std::uin instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg + 1)); instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8) & 0xFF))); instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg + 1)); - instructions.emplace_back(mos6502::OpCode::tay); + instructions.emplace_back(mos6502::OpCode::tax); fixup_16_bit_N_Z_flags(instructions); } @@ -882,7 +900,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); // temporarily store lower order (not carried substraction) byte into Y for checking // later if this is a two byte subtraction operation - instructions.emplace_back(mos6502::OpCode::tay); + instructions.emplace_back(mos6502::OpCode::tax); return; } case AVR::OpCode::st: { @@ -985,14 +1003,24 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } case AVR::OpCode::cpi: { + // note that this will leave the C flag in the 6502 borrow state, not normal carry state instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::sec); instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); return; } case AVR::OpCode::brlo: { - instructions.emplace_back(mos6502::OpCode::bcc, o1); - return; + + if (o1.value == ".+2") { + // assumes 6502 'borrow' for Carry flag instead of carry, so bcc instead of bcs + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::bcc, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } else { + instructions.emplace_back(mos6502::OpCode::bcc, o1); + return; + } } case AVR::OpCode::swap: { // from http://www.6502.org/source/general/SWN.html @@ -1014,6 +1042,46 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } + case AVR::OpCode::add: { + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::adc, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::adc: { + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::adc, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + return; + } + case AVR::OpCode::cpc: { + // this instruction seems to need to be used in the case after a sbc operation, where the + // carry flag is set to the appropriate borrow state, so I'm going to not invert + // the carry flag here, and assume that it's set how the 6502 wants it to be + // set from the previous operation + + instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, AVR::get_register(o2_reg_num)); + return; + } + case AVR::OpCode::brsh: { + if (o1.value == ".+2") { + // assumes 6502 'borrow' for Carry flag instead of carry, so bcs instead of bcc + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::bcs, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } + + throw std::runtime_error("Unable to handle unknown brsh offset"); + } + + case AVR::OpCode::breq: { + instructions.emplace_back(mos6502::OpCode::beq, o1); + return; + } + } throw std::runtime_error("Could not translate unhandled instruction"); @@ -1485,6 +1553,13 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; return true; + } else if (instructions[op].opcode == mos6502::OpCode::beq) { + const auto comment = instructions[op].comment; + instructions[op] = mos6502(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_pos)); + instructions.insert(std::next(std::begin(instructions), op + 1), mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); + instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); + instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; + return true; } else if (instructions[op].opcode == mos6502::OpCode::bcc) { const auto comment = instructions[op].comment; instructions[op] = mos6502(mos6502::OpCode::bcs, Operand(Operand::Type::literal, new_pos)); @@ -1494,7 +1569,7 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; return true; } else { - throw std::runtime_error("Don't know how to reorg this branch"); + throw std::runtime_error("Don't know how to reorg this branch: " + instructions[op].to_string()); } } } @@ -1673,7 +1748,7 @@ void run(std::istream &input) new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); - bool skip_next_instruction = false; + int instructions_to_skip = 0; std::string next_label_name; for (const auto &i : instructions) { to_mos6502(i, new_instructions); @@ -1682,13 +1757,19 @@ void run(std::istream &input) const auto last_instruction = new_instructions.back(); const auto last_instruction_loc = new_instructions.size() - 1; - if (skip_next_instruction) { + if (instructions_to_skip == 1) { new_instructions.emplace_back(ASMLine::Type::Label, next_label_name); - skip_next_instruction = false; } + --instructions_to_skip; + if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_instruction")) { - skip_next_instruction = true; + instructions_to_skip = 1; + next_label_name = last_instruction.text; + new_instructions.erase(std::next(new_instructions.begin(), static_cast(last_instruction_loc))); + } + if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_2_instructions")) { + instructions_to_skip = 2; next_label_name = last_instruction.text; new_instructions.erase(std::next(new_instructions.begin(), static_cast(last_instruction_loc))); } From ab9dd4e1b7227cb0ceda809a568aaf94297b0cc6 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Wed, 5 May 2021 16:44:30 -0600 Subject: [PATCH 11/27] Updated 16bit counter example with higher level functions --- examples/16bit_counter.cpp | 57 ++++++++++++++++++++------------------ src/main.cpp | 11 +++++++- 2 files changed, 40 insertions(+), 28 deletions(-) diff --git a/examples/16bit_counter.cpp b/examples/16bit_counter.cpp index 118899f..162ec55 100644 --- a/examples/16bit_counter.cpp +++ b/examples/16bit_counter.cpp @@ -34,21 +34,29 @@ inline void puts(uint8_t x, uint8_t y, std::string_view str) { str.size()); } - -inline void put_hex(uint8_t x, uint8_t y, uint8_t value) -{ - -} - -inline void put_hex(uint8_t x, uint8_t y, uint16_t value) -{ -} - inline void putc(uint8_t x, uint8_t y, uint8_t c) { const auto start = 0x400 + (y * 40 + x); poke(start, c); } +inline void put_hex(uint8_t x, uint8_t y, uint8_t value) { + const auto put_nibble = [](auto x, auto y, uint8_t nibble) { + if (nibble <= 9) { + putc(x, y, nibble + 48); + } else { + putc(x, y, nibble - 9); + } + }; + + put_nibble(x + 1, y, 0xF & value); + put_nibble(x, y, 0xF & (value >> 4)); +} + +inline void put_hex(uint8_t x, uint8_t y, uint16_t value) { + put_hex(x+2,y, static_cast(0xFF & value)); + put_hex(x,y, static_cast(0xFF & (value >> 8))); +} + struct Clock { using milliseconds = std::chrono::duration; @@ -83,29 +91,24 @@ int main() { /* puts(5, 5, "hello world"); puts(10, 10, "hellooooo world"); +*/ + Clock game_clock{}; + - Clock game_clock{}; - */ + std::uint16_t counter = 0; - std::uint16_t us_elapsed = 0; - - int y = 0; + std::uint8_t y = 15; while (true) { - // const auto us_elapsed = game_clock.restart().count(); + const auto us_elapsed = game_clock.restart().count(); - for (int i = 0; i < 4; ++i) { - const auto nibble = static_cast((us_elapsed >> (i * 4)) & 0xF); - if (nibble <= 9) { - putc(6 - i, y, nibble + 48); - } else { - putc(6 - i, y, nibble - 9); - } + put_hex(5, y, us_elapsed); + put_hex(11, y, counter); + + if (y++ == 20) { + y = 15; } - if (y++ == 5) { - y = 0; - } - ++us_elapsed; + ++counter; increment_border_color(); } diff --git a/src/main.cpp b/src/main.cpp index 7a341b6..0e0a235 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -1072,9 +1072,10 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(mos6502::OpCode::bcs, Operand(Operand::Type::literal, new_label_name)); instructions.emplace_back(ASMLine::Type::Directive, new_label_name); return; + } else { + instructions.emplace_back(mos6502::OpCode::bcs, o1); } - throw std::runtime_error("Unable to handle unknown brsh offset"); } case AVR::OpCode::breq: { @@ -1568,6 +1569,14 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; return true; + } else if (instructions[op].opcode == mos6502::OpCode::bcs) { + const auto comment = instructions[op].comment; + instructions[op] = mos6502(mos6502::OpCode::bcc, Operand(Operand::Type::literal, new_pos)); + instructions.insert(std::next(std::begin(instructions), op + 1), + mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); + instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); + instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; + return true; } else { throw std::runtime_error("Don't know how to reorg this branch: " + instructions[op].to_string()); } From d39ad32438bded26d4d65b7b81e415b5c709e8b3 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Wed, 5 May 2021 17:02:38 -0600 Subject: [PATCH 12/27] convert sec/sbc with cmp, increase perf --- src/main.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main.cpp b/src/main.cpp index 0e0a235..06ab0be 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -1005,8 +1005,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode case AVR::OpCode::cpi: { // note that this will leave the C flag in the 6502 borrow state, not normal carry state instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); + instructions.emplace_back(mos6502::OpCode::cmp, Operand(o2.type, fixup_8bit_literal(o2.value))); return; } case AVR::OpCode::brlo: { @@ -1074,6 +1073,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode return; } else { instructions.emplace_back(mos6502::OpCode::bcs, o1); + return; } } From f95290b68ce89010cdb8b917472bdfbaedc88cdc Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Wed, 5 May 2021 20:21:06 -0600 Subject: [PATCH 13/27] Apply a few more optimization rounds --- src/main.cpp | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-) diff --git a/src/main.cpp b/src/main.cpp index 06ab0be..451f97b 100644 --- a/src/main.cpp +++ b/src/main.cpp @@ -773,7 +773,7 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) // need to get both Z and N set appropriately // assuming A contains higher order byte and Y contains lower order byte - // todo, abstract this out so it can be used after any 16 bit op + instructions.emplace_back(ASMLine::Type::Directive, "; BEGIN remove if next is lda"); instructions.emplace_back(ASMLine::Type::Directive, "; set CPU flags assuming A holds the higher order byte already"); std::string set_flag_label = "flags_set_after_16_bit_op_" + std::to_string(instructions.size()); // if high order is negative, we know it's not 0 and it is negative @@ -787,6 +787,7 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) // if low order byte is negative, shift right by one bit, then we'll get the proper Z/N flags instructions.emplace_back(mos6502::OpCode::lsr); instructions.emplace_back(ASMLine::Type::Label, set_flag_label); + instructions.emplace_back(ASMLine::Type::Directive, "; END remove if next is lda"); } @@ -1471,6 +1472,67 @@ bool optimize(std::vector &instructions) return i; }; + + // remove unused flag-fix-up blocks + // it might make sense in the future to only insert these if determined they are needed? + for (size_t op = 10; op < instructions.size(); ++op) { + if (instructions[op].opcode == mos6502::OpCode::lda) { + if (instructions[op-1].text == "; END remove if next is lda") + { + for (size_t inner_op = op-1; inner_op > 1; --inner_op) { + instructions[inner_op] = mos6502(ASMLine::Type::Directive, + "; removed unused flag fix-up: " + instructions[inner_op].to_string()); + + if (instructions[inner_op].text.find("; BEGIN") != std::string::npos) { + return true; + } + } + } + } + } + + + // look for redundant load of lda after a tax + for (size_t op = 0; op < instructions.size() - 3; ++op) { + if (instructions[op].opcode == mos6502::OpCode::sta + && instructions[op+1].opcode == mos6502::OpCode::tax + && instructions[op+2].opcode == mos6502::OpCode::lda + && instructions[op].op.value == instructions[op+2].op.value) + { + instructions[op+2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op+2].to_string()); + return true; + } + } + + // look for redundant stores to 0-page registers with sta + for (size_t op = 0; op < instructions.size(); ++op) { + // todo, make sure this is in the register map + if (instructions[op].opcode == mos6502::OpCode::sta + && instructions[op].op.value.size() == 3) + { + for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) { + if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) { + // we just found a use of ourselves back, abort the search, there's probably something else going on + break; + } + + // abort at label + if (instructions[next_op].type == ASMLine::Type::Label) { + break; + } + + if (instructions[next_op].opcode == mos6502::OpCode::sta + && instructions[next_op].op.value == instructions[op].op.value) { + // looks like we found a redundant store, remove the first one + instructions[op] = mos6502(ASMLine::Type::Directive, + "; removed redundant sta: " + instructions[op].to_string()); + return true; + } + } + } + + } + for (size_t op = 0; op < instructions.size() - 1; ++op) { // look for a transfer of Y -> A immediately followed by A -> Y if (instructions[op].opcode == mos6502::OpCode::tya) { From 21d23dfcb9d0fcecef0f3f9c59c9f75c8014da52 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 11:39:33 -0600 Subject: [PATCH 14/27] Add a new compile script --- compile.sh | 1 + 1 file changed, 1 insertion(+) create mode 100755 compile.sh diff --git a/compile.sh b/compile.sh new file mode 100755 index 0000000..d75d0d5 --- /dev/null +++ b/compile.sh @@ -0,0 +1 @@ +avr-gcc $1 -Wall -Wextra -c -o- -S -O3 -I ~/avr-libstdcpp/include/ -std=c++20 | tee $1.asm | ./avr-to-6502 | tee $1.asm && xa -O PETSCREEN -M $1.prg From 4ffae19177be51d5dadc6af9bc56b97c4cb919ff Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 14:04:59 -0600 Subject: [PATCH 15/27] change name to 6502-c++ and merge in files from cpp_starter_project --- .clang-tidy | 7 + .cmake-format.yaml | 19 ++ CMakeLists.txt | 85 ++++- LICENSE | 24 ++ README.md | 467 ++++++++++++++++++++++++++++ cmake/Cache.cmake | 29 ++ cmake/CompilerWarnings.cmake | 78 +++++ cmake/Conan.cmake | 23 ++ cmake/Doxygen.cmake | 11 + cmake/PreventInSourceBuilds.cmake | 18 ++ cmake/Sanitizers.cmake | 66 ++++ cmake/StandardProjectSettings.cmake | 42 +++ cmake/StaticAnalyzers.cmake | 37 +++ src/{main.cpp => 6502-c++.cpp} | 105 +++---- src/CMakeLists.txt | 17 + test/CMakeLists.txt | 64 ++++ test/catch_main.cpp | 5 + test/constexpr_tests.cpp | 14 + test/tests.cpp | 14 + 19 files changed, 1064 insertions(+), 61 deletions(-) create mode 100644 .clang-tidy create mode 100644 .cmake-format.yaml create mode 100644 LICENSE create mode 100644 README.md create mode 100644 cmake/Cache.cmake create mode 100644 cmake/CompilerWarnings.cmake create mode 100644 cmake/Conan.cmake create mode 100644 cmake/Doxygen.cmake create mode 100644 cmake/PreventInSourceBuilds.cmake create mode 100644 cmake/Sanitizers.cmake create mode 100644 cmake/StandardProjectSettings.cmake create mode 100644 cmake/StaticAnalyzers.cmake rename src/{main.cpp => 6502-c++.cpp} (94%) create mode 100644 src/CMakeLists.txt create mode 100644 test/CMakeLists.txt create mode 100644 test/catch_main.cpp create mode 100644 test/constexpr_tests.cpp create mode 100644 test/tests.cpp diff --git a/.clang-tidy b/.clang-tidy new file mode 100644 index 0000000..f95f74f --- /dev/null +++ b/.clang-tidy @@ -0,0 +1,7 @@ +--- +Checks: '*,-fuchsia-*,-google-*,-zircon-*,-abseil-*,-modernize-use-trailing-return-type,-llvm*' +WarningsAsErrors: '*' +HeaderFilterRegex: '' +FormatStyle: none + + diff --git a/.cmake-format.yaml b/.cmake-format.yaml new file mode 100644 index 0000000..03c1da7 --- /dev/null +++ b/.cmake-format.yaml @@ -0,0 +1,19 @@ +additional_commands: + foo: + flags: + - BAR + - BAZ + kwargs: + DEPENDS: '*' + HEADERS: '*' + SOURCES: '*' +bullet_char: '*' +dangle_parens: false +enum_char: . +line_ending: unix +line_width: 120 +max_pargs_hwrap: 3 +separate_ctrl_name_with_space: false +separate_fn_name_with_space: false +tab_size: 2 + diff --git a/CMakeLists.txt b/CMakeLists.txt index bfd5a5f..bdaad0e 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -1,11 +1,82 @@ -cmake_minimum_required(VERSION 3.5) +cmake_minimum_required(VERSION 3.15) -project(x86-to-6502) +# Set the project name to your project name, my project isn't very descriptive +project(6502-c++ CXX) +include(cmake/StandardProjectSettings.cmake) +include(cmake/PreventInSourceBuilds.cmake) -add_executable(x86-to-6502 src/main.cpp) +# Link this 'library' to set the c++ standard / compile-time options requested +add_library(project_options INTERFACE) +target_compile_features(project_options INTERFACE cxx_std_20) -target_compile_features(x86-to-6502 PRIVATE cxx_std_20) +if(CMAKE_CXX_COMPILER_ID MATCHES ".*Clang") + option(ENABLE_BUILD_WITH_TIME_TRACE "Enable -ftime-trace to generate time tracing .json files on clang" OFF) + if(ENABLE_BUILD_WITH_TIME_TRACE) + target_compile_options(project_options INTERFACE -ftime-trace) + endif() +endif() -if (CMAKE_COMPILER_IS_GNUCC) - target_compile_options(x86-to-6502 PRIVATE -Wall -Wextra -Wconversion -Wshadow -Wnon-virtual-dtor -Wold-style-cast -Wcast-align -Wcast-qual -Wunused -Woverloaded-virtual -Wpedantic) -endif () +# Link this 'library' to use the warnings specified in CompilerWarnings.cmake +add_library(project_warnings INTERFACE) + +# enable cache system +include(cmake/Cache.cmake) + +# standard compiler warnings +include(cmake/CompilerWarnings.cmake) +set_project_warnings(project_warnings) + +# sanitizer options if supported by compiler +include(cmake/Sanitizers.cmake) +enable_sanitizers(project_options) + +# enable doxygen +include(cmake/Doxygen.cmake) +enable_doxygen() + +# allow for static analysis options +include(cmake/StaticAnalyzers.cmake) + +option(BUILD_SHARED_LIBS "Enable compilation of shared libraries" OFF) +option(ENABLE_TESTING "Enable Test Builds" ON) +option(ENABLE_FUZZING "Enable Fuzzing Builds" OFF) + +# Very basic PCH example +option(ENABLE_PCH "Enable Precompiled Headers" OFF) +if(ENABLE_PCH) + # This sets a global PCH parameter, each project will build its own PCH, which is a good idea if any #define's change + # + # consider breaking this out per project as necessary + target_precompile_headers( + project_options + INTERFACE + + + + ) +endif() + +# Set up some extra Conan dependencies based on our needs before loading Conan +set(CONAN_EXTRA_REQUIRES "") +set(CONAN_EXTRA_OPTIONS "") + +if(CPP_STARTER_USE_SDL) + set(CONAN_EXTRA_REQUIRES ${CONAN_EXTRA_REQUIRES} sdl2/2.0.10@bincrafters/stable) + # set(CONAN_EXTRA_OPTIONS ${CONAN_EXTRA_OPTIONS} sdl2:wayland=True) +endif() + +include(cmake/Conan.cmake) +run_conan() + +if(ENABLE_TESTING) + enable_testing() + message("Building Tests. Be sure to check out test/constexpr_tests for constexpr testing") + add_subdirectory(test) +endif() + +if(ENABLE_FUZZING) + message("Building Fuzz Tests, using fuzzing sanitizer https://www.llvm.org/docs/LibFuzzer.html") + add_subdirectory(fuzz_test) +endif() + +add_subdirectory(src) diff --git a/LICENSE b/LICENSE new file mode 100644 index 0000000..fdddb29 --- /dev/null +++ b/LICENSE @@ -0,0 +1,24 @@ +This is free and unencumbered software released into the public domain. + +Anyone is free to copy, modify, publish, use, compile, sell, or +distribute this software, either in source code form or as a compiled +binary, for any purpose, commercial or non-commercial, and by any +means. + +In jurisdictions that recognize copyright laws, the author or authors +of this software dedicate any and all copyright interest in the +software to the public domain. We make this dedication for the benefit +of the public at large and to the detriment of our heirs and +successors. We intend this dedication to be an overt act of +relinquishment in perpetuity of all present and future rights to this +software under copyright law. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY CLAIM, DAMAGES OR +OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, +ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR +OTHER DEALINGS IN THE SOFTWARE. + +For more information, please refer to diff --git a/README.md b/README.md new file mode 100644 index 0000000..f826489 --- /dev/null +++ b/README.md @@ -0,0 +1,467 @@ +# cpp_starter_project + +[![codecov](https://codecov.io/gh/lefticus/cpp_starter_project/branch/master/graph/badge.svg)](https://codecov.io/gh/lefticus/cpp_starter_project) + +[![Build Status](https://travis-ci.org/lefticus/cpp_starter_project.svg?branch=master)](https://travis-ci.org/lefticus/cpp_starter_project) + +[![Build status](https://ci.appveyor.com/api/projects/status/ro4lbfoa7n0sy74c/branch/master?svg=true)](https://ci.appveyor.com/project/lefticus/cpp-starter-project/branch/master) + +![CMake](https://github.com/lefticus/cpp_starter_project/workflows/CMake/badge.svg) + + +## Getting Started + +### Use the Github template +First, click the green `Use this template` button near the top of this page. +This will take you to Github's ['Generate Repository'](https://github.com/lefticus/cpp_starter_project/generate) page. +Fill in a repository name and short description, and click 'Create repository from template'. +This will allow you to create a new repository in your Github account, +prepopulated with the contents of this project. +Now you can clone the project locally and get to work! + + $ git clone https://github.com//.git + +### Remove frameworks you're not going to use +If you know you're not going to use one or more of the optional gui/graphics +frameworks (fltk, gtkmm, imgui, etc.), you can remove them with `git rm`: + + $ git rm -r src/ + +## Dependencies + +Note about install commands: +- for Windows, we use [choco](https://chocolatey.org/install). +- for MacOS, we use [brew](https://brew.sh/). +- In case of an error in cmake, make sure that the dependencies are on the PATH. + +### Necessary Dependencies +1. A C++ compiler that supports C++17. +See [cppreference.com](https://en.cppreference.com/w/cpp/compiler_support) +to see which features are supported by each compiler. +The following compilers should work: + + * [gcc 7+](https://gcc.gnu.org/) +
+ Install command + + - Debian/Ubuntu: + + sudo apt install build-essential + + - Windows: + + choco install mingw -y + + - MacOS: + + brew install gcc +
+ + * [clang 6+](https://clang.llvm.org/) +
+ Install command + + - Debian/Ubuntu: + + bash -c "$(wget -O - https://apt.llvm.org/llvm.sh)" + + - Windows: + + Visual Studio 2019 ships with LLVM (see the Visual Studio section). However, to install LLVM separately: + + choco install llvm -y + + llvm-utils for using external LLVM with Visual Studio generator: + + git clone https://github.com/zufuliu/llvm-utils.git + cd llvm-utils/VS2017 + .\install.bat + + - MacOS: + + brew install llvm +
+ + * [Visual Studio 2019 or higher](https://visualstudio.microsoft.com/) +
+ Install command + Environment setup + + On Windows, you need to install Visual Studio 2019 because of the SDK and libraries that ship with it. + + Visual Studio IDE - 2019 Community (installs Clang too): + + choco install -y visualstudio2019community --package-parameters "add Microsoft.VisualStudio.Workload.NativeDesktop --includeRecommended --includeOptional --passive --locale en-US" + + Put MSVC compiler, Clang compiler, and vcvarsall.bat on the path: + + choco install vswhere -y + refreshenv + + # change to x86 for 32bit + $clpath = vswhere -products * -latest -prerelease -find **/Hostx64/x64/* + $clangpath = vswhere -products * -latest -prerelease -find **/Llvm/bin/* + $vcvarsallpath = vswhere -products * -latest -prerelease -find **/Auxiliary/Build/* + + $path = [System.Environment]::GetEnvironmentVariable("PATH", "User") + [Environment]::SetEnvironmentVariable("Path", $path + ";$clpath" + ";$clangpath" + ";$vcvarsallpath", "User") + refreshenv + +
+ + +2. [Conan](https://conan.io/) +
+ Install Command + + - Via pip - https://docs.conan.io/en/latest/installation.html#install-with-pip-recommended + + pip install --user conan + + - Windows: + + choco install conan -y + + - MacOS: + + brew install conan + +
+ +3. [CMake 3.15+](https://cmake.org/) +
+ Install Command + + - Debian/Ubuntu: + + sudo apt-get install cmake + + - Windows: + + choco install cmake -y + + - MacOS: + + brew install cmake + +
+ +### Optional Dependencies +#### C++ Tools + * [Doxygen](http://doxygen.nl/) +
+ Install Command + + - Debian/Ubuntu: + + sudo apt-get install doxygen + sudo apt-get install graphviz + + - Windows: + + choco install doxygen.install -y + choco install graphviz -y + + - MacOS: + + brew install doxygen + brew install graphviz + +
+ + + * [ccache](https://ccache.dev/) +
+ Install Command + + - Debian/Ubuntu: + + sudo apt-get install ccache + + - Windows: + + choco install ccache -y + + - MacOS: + + brew install ccache + +
+ + + * [Cppcheck](http://cppcheck.sourceforge.net/) +
+ Install Command + + - Debian/Ubuntu: + + sudo apt-get install cppcheck + + - Windows: + + choco install cppcheck -y + + - MacOS: + + brew install cppcheck + +
+ + + * [include-what-you-use](https://include-what-you-use.org/) +
+ Install Command + + Follow instructions here: + https://github.com/include-what-you-use/include-what-you-use#how-to-install +
+ +#### GUI libraries +This project can be made to work with several optional GUI frameworks. + +If desired, you should install the following optional dependencies as +directed by their documentation, linked here: + +- [FLTK](https://www.fltk.org/doc-1.4/index.html) +- [GTKMM](https://www.gtkmm.org/en/documentation.html) +- [QT](https://doc.qt.io/) + +The following dependencies can be downloaded automatically by CMake and Conan. +All you need to do to install them is to turn on a CMake flag during +configuration. +If you run into difficulty using them, please refer to their documentation, +linked here: + +- [NANA](http://nanapro.org/en-us/documentation/) +- [SDL](http://wiki.libsdl.org/FrontPage) +- [IMGUI](https://github.com/ocornut/imgui/tree/master/docs): + This framework depends on SFML, and if you are using Linux, you may need + to install several of SFML's dependencies using your package manager. See + [the SFML build tutorial](https://www.sfml-dev.org/tutorials/2.5/compile-with-cmake.php) + for specifics. + +## Build Instructions + +### Build directory +Make a build directory: +``` +mkdir build +``` +### Specify the compiler using environment variables + +By default (if you don't set environment variables `CC` and `CXX`), the system default compiler will be used. + +Conan and CMake use the environment variables CC and CXX to decide which compiler to use. So to avoid the conflict issues only specify the compilers using these variables. + +CMake will detect which compiler was used to build each of the Conan targets. If you build all of your Conan targets with one compiler, and then build your CMake targets with a different compiler, the project may fail to build. + +
+Commands for setting the compilers + +- Debian/Ubuntu/MacOS: + + Set your desired compiler (`clang`, `gcc`, etc): + + - Temporarily (only for the current shell) + + Run one of the followings in the terminal: + + - clang + + CC=clang CXX=clang++ + + - gcc + + CC=gcc CXX=g++ + + - Permanent: + + Open `~/.bashrc` using your text editor: + + gedit ~/.bashrc + + Add `CC` and `CXX` to point to the compilers: + + export CC=clang + export CXX=clang++ + + Save and close the file. + +- Windows: + + - Permanent: + + Run one of the followings in PowerShell: + + - Visual Studio generator and compiler (cl) + + [Environment]::SetEnvironmentVariable("CC", "cl.exe", "User") + [Environment]::SetEnvironmentVariable("CXX", "cl.exe", "User") + refreshenv + + Set the architecture using [vsvarsall](https://docs.microsoft.com/en-us/cpp/build/building-on-the-command-line?view=vs-2019#vcvarsall-syntax): + + vsvarsall.bat x64 + + - clang + + [Environment]::SetEnvironmentVariable("CC", "clang.exe", "User") + [Environment]::SetEnvironmentVariable("CXX", "clang++.exe", "User") + refreshenv + + - gcc + + [Environment]::SetEnvironmentVariable("CC", "gcc.exe", "User") + [Environment]::SetEnvironmentVariable("CXX", "g++.exe", "User") + refreshenv + + + - Temporarily (only for the current shell): + + $Env:CC="clang.exe" + $Env:CXX="clang++.exe" + +
+ +### Configure your build + +To configure the project and write makefiles, you could use `cmake` with a bunch of command line options. +The easier option is to run cmake interactively: + +#### **Configure via cmake-gui**: + +1) Open cmake-gui from the project directory: +``` +cmake-gui . +``` +2) Set the build directory: + +![build_dir](https://user-images.githubusercontent.com/16418197/82524586-fa48e380-9af4-11ea-8514-4e18a063d8eb.jpg) + +3) Configure the generator: + +In cmake-gui, from the upper menu select `Tools/Configure`. + +**Warning**: if you have set `CC` and `CXX` always choose the `use default native compilers` option. This picks `CC` and `CXX`. Don't change the compiler at this stage! + +
+Windows - MinGW Makefiles + +Choose MinGW Makefiles as the generator: + +mingw + +
+ +
+Windows - Visual Studio generator and compiler + +You should have already set `C` and `CXX` to `cl.exe`. + +Choose "Visual Studio 16 2019" as the generator: + +default_vs + +
+ +
+ +Windows - Visual Studio generator and Clang Compiler + +You should have already set `C` and `CXX` to `clang.exe` and `clang++.exe`. + +Choose "Visual Studio 16 2019" as the generator. To tell Visual studio to use `clang-cl.exe`: +- If you use the LLVM that is shipped with Visual Studio: write `ClangCl` under "optional toolset to use". + +visual_studio + +- If you use an external LLVM: write [`LLVM_v142`](https://github.com/zufuliu/llvm-utils#llvm-for-visual-studio-2017-and-2019) + under "optional toolset to use". + +visual_studio + +
+
+ +4) Choose the Cmake options and then generate: + +![generate](https://user-images.githubusercontent.com/16418197/82781591-c97feb80-9e1f-11ea-86c8-f2748b96f516.png) + +#### **Configure via ccmake**: +with the Cmake Curses Dialog Command Line tool: + + ccmake -S . -B ./build + +Once `ccmake` has finished setting up, press 'c' to configure the project, +press 'g' to generate, and 'q' to quit. + +### Build +Once you have selected all the options you would like to use, you can build the +project (all targets): + + cmake --build ./build + +For Visual Studio, give the build configuration (Release, RelWithDeb, Debug, etc) like the following: + + cmake --build ./build -- /p:configuration=Release + +## Troubleshooting + +### Update Conan +Many problems that users have can be resolved by updating Conan, so if you are +having any trouble with this project, you should start by doing that. + +To update conan: + + $ pip install --user --upgrade conan + +You may need to use `pip3` instead of `pip` in this command, depending on your +platform. + +### Clear Conan cache +If you continue to have trouble with your Conan dependencies, you can try +clearing your Conan cache: + + $ conan remove -f '*' + +The next time you run `cmake` or `cmake --build`, your Conan dependencies will +be rebuilt. If you aren't using your system's default compiler, don't forget to +set the CC, CXX, CMAKE_C_COMPILER, and CMAKE_CXX_COMPILER variables, as +described in the 'Build using an alternate compiler' section above. + +### Identifying misconfiguration of Conan dependencies + +If you have a dependency 'A' that requires a specific version of another +dependency 'B', and your project is trying to use the wrong version of +dependency 'B', Conan will produce warnings about this configuration error +when you run CMake. These warnings can easily get lost between a couple +hundred or thousand lines of output, depending on the size of your project. + +If your project has a Conan configuration error, you can use `conan info` to +find it. `conan info` displays information about the dependency graph of your +project, with colorized output in some terminals. + + $ cd build + $ conan info . + +In my terminal, the first couple lines of `conan info`'s output show all of the +project's configuration warnings in a bright yellow font. + +For example, the package `spdlog/1.5.0` depends on the package `fmt/6.1.2`. +If you were to modify the file `cmake/Conan.cmake` so that it requires an +earlier version of `fmt`, such as `fmt/6.0.0`, and then run: + + $ conan remove -f '*' # clear Conan cache + $ rm -rf build # clear previous CMake build + $ mkdir build && cd build + $ cmake .. # rebuild Conan dependencies + $ conan info . + +...the first line of output would be a warning that `spdlog` needs a more recent +version of `fmt`. + +## Testing +See [Catch2 tutorial](https://github.com/catchorg/Catch2/blob/master/docs/tutorial.md) + +## Fuzz testing + +See [libFuzzer Tutorial](https://github.com/google/fuzzing/blob/master/tutorial/libFuzzerTutorial.md) diff --git a/cmake/Cache.cmake b/cmake/Cache.cmake new file mode 100644 index 0000000..31f5e7e --- /dev/null +++ b/cmake/Cache.cmake @@ -0,0 +1,29 @@ +option(ENABLE_CACHE "Enable cache if available" ON) +if(NOT ENABLE_CACHE) + return() +endif() + +set(CACHE_OPTION + "ccache" + CACHE STRING "Compiler cache to be used") +set(CACHE_OPTION_VALUES "ccache" "sccache") +set_property(CACHE CACHE_OPTION PROPERTY STRINGS ${CACHE_OPTION_VALUES}) +list( + FIND + CACHE_OPTION_VALUES + ${CACHE_OPTION} + CACHE_OPTION_INDEX) + +if(${CACHE_OPTION_INDEX} EQUAL -1) + message( + STATUS + "Using custom compiler cache system: '${CACHE_OPTION}', explicitly supported entries are ${CACHE_OPTION_VALUES}") +endif() + +find_program(CACHE_BINARY ${CACHE_OPTION}) +if(CACHE_BINARY) + message(STATUS "${CACHE_OPTION} found and enabled") + set(CMAKE_CXX_COMPILER_LAUNCHER ${CACHE_BINARY}) +else() + message(WARNING "${CACHE_OPTION} is enabled but was not found. Not using it") +endif() diff --git a/cmake/CompilerWarnings.cmake b/cmake/CompilerWarnings.cmake new file mode 100644 index 0000000..8243154 --- /dev/null +++ b/cmake/CompilerWarnings.cmake @@ -0,0 +1,78 @@ +# from here: +# +# https://github.com/lefticus/cppbestpractices/blob/master/02-Use_the_Tools_Available.md + +function(set_project_warnings project_name) + option(WARNINGS_AS_ERRORS "Treat compiler warnings as errors" TRUE) + + set(MSVC_WARNINGS + /W4 # Baseline reasonable warnings + /w14242 # 'identifier': conversion from 'type1' to 'type1', possible loss of data + /w14254 # 'operator': conversion from 'type1:field_bits' to 'type2:field_bits', possible loss of data + /w14263 # 'function': member function does not override any base class virtual member function + /w14265 # 'classname': class has virtual functions, but destructor is not virtual instances of this class may not + # be destructed correctly + /w14287 # 'operator': unsigned/negative constant mismatch + /we4289 # nonstandard extension used: 'variable': loop control variable declared in the for-loop is used outside + # the for-loop scope + /w14296 # 'operator': expression is always 'boolean_value' + /w14311 # 'variable': pointer truncation from 'type1' to 'type2' + /w14545 # expression before comma evaluates to a function which is missing an argument list + /w14546 # function call before comma missing argument list + /w14547 # 'operator': operator before comma has no effect; expected operator with side-effect + /w14549 # 'operator': operator before comma has no effect; did you intend 'operator'? + /w14555 # expression has no effect; expected expression with side- effect + /w14619 # pragma warning: there is no warning number 'number' + /w14640 # Enable warning on thread un-safe static member initialization + /w14826 # Conversion from 'type1' to 'type_2' is sign-extended. This may cause unexpected runtime behavior. + /w14905 # wide string literal cast to 'LPSTR' + /w14906 # string literal cast to 'LPWSTR' + /w14928 # illegal copy-initialization; more than one user-defined conversion has been implicitly applied + /permissive- # standards conformance mode for MSVC compiler. + ) + + set(CLANG_WARNINGS + -Wall + -Wextra # reasonable and standard + -Wshadow # warn the user if a variable declaration shadows one from a parent context + -Wnon-virtual-dtor # warn the user if a class with virtual functions has a non-virtual destructor. This helps + # catch hard to track down memory errors + -Wold-style-cast # warn for c-style casts + -Wcast-align # warn for potential performance problem casts + -Wunused # warn on anything being unused + -Woverloaded-virtual # warn if you overload (not override) a virtual function + -Wpedantic # warn if non-standard C++ is used + -Wconversion # warn on type conversions that may lose data + -Wsign-conversion # warn on sign conversions + -Wnull-dereference # warn if a null dereference is detected + -Wdouble-promotion # warn if float is implicit promoted to double + -Wformat=2 # warn on security issues around functions that format output (ie printf) + ) + + if(WARNINGS_AS_ERRORS) + set(CLANG_WARNINGS ${CLANG_WARNINGS} -Werror) + set(MSVC_WARNINGS ${MSVC_WARNINGS} /WX) + endif() + + set(GCC_WARNINGS + ${CLANG_WARNINGS} + -Wmisleading-indentation # warn if indentation implies blocks where blocks do not exist + -Wduplicated-cond # warn if if / else chain has duplicated conditions + -Wduplicated-branches # warn if if / else branches have duplicated code + -Wlogical-op # warn about logical operations being used where bitwise were probably wanted + -Wuseless-cast # warn if you perform a cast to the same type + ) + + if(MSVC) + set(PROJECT_WARNINGS ${MSVC_WARNINGS}) + elseif(CMAKE_CXX_COMPILER_ID MATCHES ".*Clang") + set(PROJECT_WARNINGS ${CLANG_WARNINGS}) + elseif(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + set(PROJECT_WARNINGS ${GCC_WARNINGS}) + else() + message(AUTHOR_WARNING "No compiler warnings set for '${CMAKE_CXX_COMPILER_ID}' compiler.") + endif() + + target_compile_options(${project_name} INTERFACE ${PROJECT_WARNINGS}) + +endfunction() diff --git a/cmake/Conan.cmake b/cmake/Conan.cmake new file mode 100644 index 0000000..a514b15 --- /dev/null +++ b/cmake/Conan.cmake @@ -0,0 +1,23 @@ +macro(run_conan) + # Download automatically, you can also just copy the conan.cmake file + if(NOT EXISTS "${CMAKE_BINARY_DIR}/conan.cmake") + message(STATUS "Downloading conan.cmake from https://github.com/conan-io/cmake-conan") + file(DOWNLOAD "https://github.com/conan-io/cmake-conan/raw/v0.16.1/conan.cmake" "${CMAKE_BINARY_DIR}/conan.cmake") + endif() + + include(${CMAKE_BINARY_DIR}/conan.cmake) + + conan_cmake_run( + REQUIRES + ${CONAN_EXTRA_REQUIRES} + catch2/2.13.6 + docopt.cpp/0.6.3 + fmt/7.1.3 + spdlog/1.8.5 + OPTIONS + ${CONAN_EXTRA_OPTIONS} + BASIC_SETUP + CMAKE_TARGETS # individual targets to link to + BUILD + missing) +endmacro() diff --git a/cmake/Doxygen.cmake b/cmake/Doxygen.cmake new file mode 100644 index 0000000..4dad807 --- /dev/null +++ b/cmake/Doxygen.cmake @@ -0,0 +1,11 @@ +function(enable_doxygen) + option(ENABLE_DOXYGEN "Enable doxygen doc builds of source" OFF) + if(ENABLE_DOXYGEN) + set(DOXYGEN_CALLER_GRAPH YES) + set(DOXYGEN_CALL_GRAPH YES) + set(DOXYGEN_EXTRACT_ALL YES) + find_package(Doxygen REQUIRED dot) + doxygen_add_docs(doxygen-docs ${PROJECT_SOURCE_DIR}) + + endif() +endfunction() diff --git a/cmake/PreventInSourceBuilds.cmake b/cmake/PreventInSourceBuilds.cmake new file mode 100644 index 0000000..57d9c59 --- /dev/null +++ b/cmake/PreventInSourceBuilds.cmake @@ -0,0 +1,18 @@ +# +# This function will prevent in-source builds +function(AssureOutOfSourceBuilds) + # make sure the user doesn't play dirty with symlinks + get_filename_component(srcdir "${CMAKE_SOURCE_DIR}" REALPATH) + get_filename_component(bindir "${CMAKE_BINARY_DIR}" REALPATH) + + # disallow in-source builds + if("${srcdir}" STREQUAL "${bindir}") + message("######################################################") + message("Warning: in-source builds are disabled") + message("Please create a separate build directory and run cmake from there") + message("######################################################") + message(FATAL_ERROR "Quitting configuration") + endif() +endfunction() + +assureoutofsourcebuilds() diff --git a/cmake/Sanitizers.cmake b/cmake/Sanitizers.cmake new file mode 100644 index 0000000..6c6ff8f --- /dev/null +++ b/cmake/Sanitizers.cmake @@ -0,0 +1,66 @@ +function(enable_sanitizers project_name) + + if(CMAKE_CXX_COMPILER_ID STREQUAL "GNU" OR CMAKE_CXX_COMPILER_ID MATCHES ".*Clang") + option(ENABLE_COVERAGE "Enable coverage reporting for gcc/clang" FALSE) + + if(ENABLE_COVERAGE) + target_compile_options(${project_name} INTERFACE --coverage -O0 -g) + target_link_libraries(${project_name} INTERFACE --coverage) + endif() + + set(SANITIZERS "") + + option(ENABLE_SANITIZER_ADDRESS "Enable address sanitizer" FALSE) + if(ENABLE_SANITIZER_ADDRESS) + list(APPEND SANITIZERS "address") + endif() + + option(ENABLE_SANITIZER_LEAK "Enable leak sanitizer" FALSE) + if(ENABLE_SANITIZER_LEAK) + list(APPEND SANITIZERS "leak") + endif() + + option(ENABLE_SANITIZER_UNDEFINED_BEHAVIOR "Enable undefined behavior sanitizer" FALSE) + if(ENABLE_SANITIZER_UNDEFINED_BEHAVIOR) + list(APPEND SANITIZERS "undefined") + endif() + + option(ENABLE_SANITIZER_THREAD "Enable thread sanitizer" FALSE) + if(ENABLE_SANITIZER_THREAD) + if("address" IN_LIST SANITIZERS OR "leak" IN_LIST SANITIZERS) + message(WARNING "Thread sanitizer does not work with Address and Leak sanitizer enabled") + else() + list(APPEND SANITIZERS "thread") + endif() + endif() + + option(ENABLE_SANITIZER_MEMORY "Enable memory sanitizer" FALSE) + if(ENABLE_SANITIZER_MEMORY AND CMAKE_CXX_COMPILER_ID MATCHES ".*Clang") + if("address" IN_LIST SANITIZERS + OR "thread" IN_LIST SANITIZERS + OR "leak" IN_LIST SANITIZERS) + message(WARNING "Memory sanitizer does not work with Address, Thread and Leak sanitizer enabled") + else() + list(APPEND SANITIZERS "memory") + endif() + endif() + + list( + JOIN + SANITIZERS + "," + LIST_OF_SANITIZERS) + + endif() + + if(LIST_OF_SANITIZERS) + if(NOT + "${LIST_OF_SANITIZERS}" + STREQUAL + "") + target_compile_options(${project_name} INTERFACE -fsanitize=${LIST_OF_SANITIZERS}) + target_link_options(${project_name} INTERFACE -fsanitize=${LIST_OF_SANITIZERS}) + endif() + endif() + +endfunction() diff --git a/cmake/StandardProjectSettings.cmake b/cmake/StandardProjectSettings.cmake new file mode 100644 index 0000000..76418c1 --- /dev/null +++ b/cmake/StandardProjectSettings.cmake @@ -0,0 +1,42 @@ +# Set a default build type if none was specified +if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES) + message(STATUS "Setting build type to 'RelWithDebInfo' as none was specified.") + set(CMAKE_BUILD_TYPE + RelWithDebInfo + CACHE STRING "Choose the type of build." FORCE) + # Set the possible values of build type for cmake-gui, ccmake + set_property( + CACHE CMAKE_BUILD_TYPE + PROPERTY STRINGS + "Debug" + "Release" + "MinSizeRel" + "RelWithDebInfo") +endif() + +# Generate compile_commands.json to make it easier to work with clang based tools +set(CMAKE_EXPORT_COMPILE_COMMANDS ON) + +option(ENABLE_IPO "Enable Interprocedural Optimization, aka Link Time Optimization (LTO)" OFF) + +if(ENABLE_IPO) + include(CheckIPOSupported) + check_ipo_supported( + RESULT + result + OUTPUT + output) + if(result) + set(CMAKE_INTERPROCEDURAL_OPTIMIZATION TRUE) + else() + message(SEND_ERROR "IPO is not supported: ${output}") + endif() +endif() +if(CMAKE_CXX_COMPILER_ID MATCHES ".*Clang") + add_compile_options(-fcolor-diagnostics) +elseif(CMAKE_CXX_COMPILER_ID STREQUAL "GNU") + add_compile_options(-fdiagnostics-color=always) +else() + message(STATUS "No colored compiler diagnostic set for '${CMAKE_CXX_COMPILER_ID}' compiler.") +endif() + diff --git a/cmake/StaticAnalyzers.cmake b/cmake/StaticAnalyzers.cmake new file mode 100644 index 0000000..4396444 --- /dev/null +++ b/cmake/StaticAnalyzers.cmake @@ -0,0 +1,37 @@ +option(ENABLE_CPPCHECK "Enable static analysis with cppcheck" OFF) +option(ENABLE_CLANG_TIDY "Enable static analysis with clang-tidy" OFF) +option(ENABLE_INCLUDE_WHAT_YOU_USE "Enable static analysis with include-what-you-use" OFF) + +if(ENABLE_CPPCHECK) + find_program(CPPCHECK cppcheck) + if(CPPCHECK) + set(CMAKE_CXX_CPPCHECK + ${CPPCHECK} + --suppress=missingInclude + --enable=all + --inline-suppr + --inconclusive + -i + ${CMAKE_SOURCE_DIR}/imgui/lib) + else() + message(SEND_ERROR "cppcheck requested but executable not found") + endif() +endif() + +if(ENABLE_CLANG_TIDY) + find_program(CLANGTIDY clang-tidy) + if(CLANGTIDY) + set(CMAKE_CXX_CLANG_TIDY ${CLANGTIDY} -extra-arg=-Wno-unknown-warning-option) + else() + message(SEND_ERROR "clang-tidy requested but executable not found") + endif() +endif() + +if(ENABLE_INCLUDE_WHAT_YOU_USE) + find_program(INCLUDE_WHAT_YOU_USE include-what-you-use) + if(INCLUDE_WHAT_YOU_USE) + set(CMAKE_CXX_INCLUDE_WHAT_YOU_USE ${INCLUDE_WHAT_YOU_USE}) + else() + message(SEND_ERROR "include-what-you-use requested but executable not found") + endif() +endif() diff --git a/src/main.cpp b/src/6502-c++.cpp similarity index 94% rename from src/main.cpp rename to src/6502-c++.cpp index 451f97b..90413ad 100644 --- a/src/main.cpp +++ b/src/6502-c++.cpp @@ -218,6 +218,9 @@ struct mos6502 : ASMLine case OpCode::bne: case OpCode::bmi: case OpCode::beq: + case OpCode::bpl: + case OpCode::bcs: + case OpCode::bcc: case OpCode::adc: case OpCode::sbc: case OpCode::rts: @@ -976,7 +979,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::sbiw: { - subtract_16_bit(instructions, o1_reg_num, atoi(o2.value.c_str())); + subtract_16_bit(instructions, o1_reg_num, static_cast(std::stoi(o2.value))); return; } @@ -1083,6 +1086,9 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(mos6502::OpCode::beq, o1); return; } + case AVR::OpCode::unknown: { + throw std::runtime_error("Could not translate 'unknown' instruction"); + } } @@ -1397,26 +1403,26 @@ void log(LogLevel ll, const int line_no, const std::string &line, const std::str } template -void to_mos6502(const FromArch &i, std::vector &instructions) +void to_mos6502(const FromArch &from_instruction, std::vector &instructions) { try { - switch (i.type) { + switch (from_instruction.type) { case ASMLine::Type::Label: - if (i.text == "0") { - instructions.emplace_back(i.type, "-memcpy_0"); + if (from_instruction.text == "0") { + instructions.emplace_back(from_instruction.type, "-memcpy_0"); } else { - instructions.emplace_back(i.type, i.text); + instructions.emplace_back(from_instruction.type, from_instruction.text); } return; case ASMLine::Type::Directive: - if (i.text.starts_with(".string")) { - instructions.emplace_back(ASMLine::Type::Directive, ".asc " + i.text.substr(7)); - } else if (i.text.starts_with(".zero")) { - const auto count = atoi(i.text.data() + 6); + if (from_instruction.text.starts_with(".string")) { + instructions.emplace_back(ASMLine::Type::Directive, ".asc " + from_instruction.text.substr(7)); + } else if (from_instruction.text.starts_with(".zero")) { + const auto count = std::stoull(&*std::next(from_instruction.text.begin(), 6), nullptr, 10); std::string zeros; - for (int i = 0; i < count; ++i) { - if ((i % 20) == 0) { + for (std::size_t i = 0; i < count; ++i) { + if ((i % 40) == 0) { if (!zeros.empty()) { instructions.emplace_back(ASMLine::Type::Directive, zeros); zeros.clear(); @@ -1432,30 +1438,30 @@ void to_mos6502(const FromArch &i, std::vector &instructions) } } else { - instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + i.text); + instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + from_instruction.text); } return; case ASMLine::Type::Instruction: const auto head = instructions.size(); try { - translate_instruction(instructions, i.opcode, i.operand1, i.operand2); + translate_instruction(instructions, from_instruction.opcode, from_instruction.operand1, from_instruction.operand2); } catch (const std::exception &e) { - instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + i.text + "' " + e.what()); - log(LogLevel::Error, i, e.what()); + instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + from_instruction.text + "' " + e.what()); + log(LogLevel::Error, from_instruction, e.what()); } - auto text = i.line_text; + auto text = from_instruction.line_text; if (text[0] == '\t') { text.erase(0, 1); } - for_each(std::next(instructions.begin(), head), instructions.end(), [text](auto &ins) { + for_each(std::next(instructions.begin(), static_cast(head)), instructions.end(), [text](auto &ins) { ins.comment = text; }); return; } } catch (const std::exception &e) { - log(LogLevel::Error, i, e.what()); + log(LogLevel::Error, from_instruction, e.what()); } } @@ -1515,6 +1521,10 @@ bool optimize(std::vector &instructions) // we just found a use of ourselves back, abort the search, there's probably something else going on break; } + if (instructions[next_op].opcode == mos6502::OpCode::lda && instructions[next_op].op.value != instructions[op].op.value) { + // someone just loaded lda with a different value, so we need to abort! + break; + } // abort at label if (instructions[next_op].type == ASMLine::Type::Label) { @@ -1609,39 +1619,26 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou const auto going_to = instructions[op].op.value; const auto new_pos = "patch_" + std::to_string(branch_patch_count); // uh-oh too long of a branch, have to convert this to a jump... - if (instructions[op].opcode == mos6502::OpCode::bne) { + + std::map branch_mapping; + + branch_mapping[mos6502::OpCode::bne] = mos6502::OpCode::beq; + branch_mapping[mos6502::OpCode::beq] = mos6502::OpCode::bne; + branch_mapping[mos6502::OpCode::bcc] = mos6502::OpCode::bcs; + branch_mapping[mos6502::OpCode::bcs] = mos6502::OpCode::bcc; + + const auto mapping = branch_mapping.find(instructions[op].opcode); + + if (mapping != branch_mapping.end()) { const auto comment = instructions[op].comment; - instructions[op] = mos6502(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_pos)); - instructions.insert(std::next(std::begin(instructions), op + 1), mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); - instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); + instructions[op] = mos6502(mapping->second, Operand(Operand::Type::literal, new_pos)); + instructions.insert(std::next(std::begin(instructions), static_cast(op + 1)), mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); + instructions.insert(std::next(std::begin(instructions), static_cast(op + 2)), mos6502(ASMLine::Type::Label, new_pos)); instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; return true; - } else if (instructions[op].opcode == mos6502::OpCode::beq) { - const auto comment = instructions[op].comment; - instructions[op] = mos6502(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_pos)); - instructions.insert(std::next(std::begin(instructions), op + 1), mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); - instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); - instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; - return true; - } else if (instructions[op].opcode == mos6502::OpCode::bcc) { - const auto comment = instructions[op].comment; - instructions[op] = mos6502(mos6502::OpCode::bcs, Operand(Operand::Type::literal, new_pos)); - instructions.insert(std::next(std::begin(instructions), op + 1), - mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); - instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); - instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; - return true; - } else if (instructions[op].opcode == mos6502::OpCode::bcs) { - const auto comment = instructions[op].comment; - instructions[op] = mos6502(mos6502::OpCode::bcc, Operand(Operand::Type::literal, new_pos)); - instructions.insert(std::next(std::begin(instructions), op + 1), - mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); - instructions.insert(std::next(std::begin(instructions), op + 2), mos6502(ASMLine::Type::Label, new_pos)); - instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; - return true; - } else { - throw std::runtime_error("Don't know how to reorg this branch: " + instructions[op].to_string()); } + + throw std::runtime_error("Don't know how to reorg this branch: " + instructions[op].to_string()); } } return false; @@ -1672,9 +1669,9 @@ bool fix_overwritten_flags(std::vector &instructions) if (instructions[op2].is_branch) { // insert a pull of processor status before the branch - instructions.insert(std::next(std::begin(instructions), op2), mos6502(mos6502::OpCode::plp)); + instructions.insert(std::next(std::begin(instructions), static_cast(op2)), mos6502(mos6502::OpCode::plp)); // insert a push of processor status after the comparison - instructions.insert(std::next(std::begin(instructions), op + 1), mos6502(mos6502::OpCode::php)); + instructions.insert(std::next(std::begin(instructions), static_cast(op + 1)), mos6502(mos6502::OpCode::php)); return true; } @@ -1860,7 +1857,7 @@ void run(std::istream &input) } - for (const auto i : new_instructions) { + for (const auto &i : new_instructions) { std::cout << i.to_string() << '\n'; } } @@ -1878,16 +1875,16 @@ int main([[maybe_unused]] const int argc, const char *argv[]) } }(); - const bool is_avr = [&]() { + const bool is_386 = [&]() { for (std::size_t index = 0; index < static_cast(argc); ++index) { - if (strstr(argv[index], "avr") != nullptr) { + if (strstr(argv[index], "x86") != nullptr) { return true; } } return false; }(); - if (is_avr) { + if (!is_386) { std::cout << "; AVR Mode\n"; run(input); } else { diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt new file mode 100644 index 0000000..4cec0fe --- /dev/null +++ b/src/CMakeLists.txt @@ -0,0 +1,17 @@ +option(CPP_STARTER_USE_SDL "Enable compilation of SDL sample" OFF) + +# sdl +if(CPP_STARTER_USE_SDL) + message("Using SDL2") + add_subdirectory(sdl) +endif() + +# Generic test that uses conan libs +add_executable(6502-c++ 6502-c++.cpp) +target_link_libraries( + 6502-c++ + PRIVATE project_options + project_warnings + CONAN_PKG::docopt.cpp + CONAN_PKG::fmt + CONAN_PKG::spdlog) diff --git a/test/CMakeLists.txt b/test/CMakeLists.txt new file mode 100644 index 0000000..a69c7c7 --- /dev/null +++ b/test/CMakeLists.txt @@ -0,0 +1,64 @@ +# Automatically enable catch2 to generate ctest targets +if(CONAN_CATCH2_ROOT_DEBUG) + include(${CONAN_CATCH2_ROOT_DEBUG}/lib/cmake/Catch2/Catch.cmake) +else() + include(${CONAN_CATCH2_ROOT}/lib/cmake/Catch2/Catch.cmake) +endif() + +add_library(catch_main STATIC catch_main.cpp) +target_link_libraries(catch_main PUBLIC CONAN_PKG::catch2) +target_link_libraries(catch_main PRIVATE project_options) + +add_executable(tests tests.cpp) +target_link_libraries(tests PRIVATE project_warnings project_options catch_main) + +# automatically discover tests that are defined in catch based test files you can modify the unittests. Set TEST_PREFIX +# to whatever you want, or use different for different binaries +catch_discover_tests( + tests + TEST_PREFIX + "unittests." + REPORTER + xml + OUTPUT_DIR + . + OUTPUT_PREFIX + "unittests." + OUTPUT_SUFFIX + .xml) + +# Add a file containing a set of constexpr tests +add_executable(constexpr_tests constexpr_tests.cpp) +target_link_libraries(constexpr_tests PRIVATE project_options project_warnings catch_main) + +catch_discover_tests( + constexpr_tests + TEST_PREFIX + "constexpr." + REPORTER + xml + OUTPUT_DIR + . + OUTPUT_PREFIX + "constexpr." + OUTPUT_SUFFIX + .xml) + +# Disable the constexpr portion of the test, and build again this allows us to have an executable that we can debug when +# things go wrong with the constexpr testing +add_executable(relaxed_constexpr_tests constexpr_tests.cpp) +target_link_libraries(relaxed_constexpr_tests PRIVATE project_options project_warnings catch_main) +target_compile_definitions(relaxed_constexpr_tests PRIVATE -DCATCH_CONFIG_RUNTIME_STATIC_REQUIRE) + +catch_discover_tests( + relaxed_constexpr_tests + TEST_PREFIX + "relaxed_constexpr." + REPORTER + xml + OUTPUT_DIR + . + OUTPUT_PREFIX + "relaxed_constexpr." + OUTPUT_SUFFIX + .xml) diff --git a/test/catch_main.cpp b/test/catch_main.cpp new file mode 100644 index 0000000..d8d2eca --- /dev/null +++ b/test/catch_main.cpp @@ -0,0 +1,5 @@ +#define CATCH_CONFIG_MAIN // This tells the catch header to generate a main + +#include + + diff --git a/test/constexpr_tests.cpp b/test/constexpr_tests.cpp new file mode 100644 index 0000000..2bb5ea5 --- /dev/null +++ b/test/constexpr_tests.cpp @@ -0,0 +1,14 @@ +#include + +constexpr unsigned int Factorial(unsigned int number) +{ + return number <= 1 ? number : Factorial(number - 1) * number; +} + +TEST_CASE("Factorials are computed with constexpr", "[factorial]") +{ + STATIC_REQUIRE(Factorial(1) == 1); + STATIC_REQUIRE(Factorial(2) == 2); + STATIC_REQUIRE(Factorial(3) == 6); + STATIC_REQUIRE(Factorial(10) == 3628800); +} diff --git a/test/tests.cpp b/test/tests.cpp new file mode 100644 index 0000000..9c40b28 --- /dev/null +++ b/test/tests.cpp @@ -0,0 +1,14 @@ +#include + +unsigned int Factorial(unsigned int number) +{ + return number <= 1 ? number : Factorial(number - 1) * number; +} + +TEST_CASE("Factorials are computed", "[factorial]") +{ + REQUIRE(Factorial(1) == 1); + REQUIRE(Factorial(2) == 2); + REQUIRE(Factorial(3) == 6); + REQUIRE(Factorial(10) == 3628800); +} From f0caf81299d8187a24453c52528b34cda985e099 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 14:12:16 -0600 Subject: [PATCH 16/27] Remove i386 which was lagging very far behind now --- src/6502-c++.cpp | 527 ++--------------------------------------------- 1 file changed, 13 insertions(+), 514 deletions(-) diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 90413ad..4e800d2 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -356,201 +356,6 @@ struct mos6502 : ASMLine bool is_comparison = false; }; -struct i386 : ASMLine -{ - enum class OpCode { - unknown, - movzbl, - movzwl, - shrb, - shrl, - xorl, - andl, - andb, - addb, - ret, - movb, - cmpb, - movl, - jmp, - jne, - je, - js, - testb, - incl, - incb, - decl, - decb, - sarl, - addl, - subl, - subb, - sall, - orl, - orb, - rep, - pushl, - sbbb, - negb, - notb, - retl, - call - }; - - static Operand get_register(const int reg_num, const int offset = 0) - { - switch (reg_num) { - // http://sta.c64.org/cbm64mem.html - case 0x00: - return Operand(Operand::Type::literal, "$03");// unused, fp->int routine pointer - case 0x01: - return Operand(Operand::Type::literal, "$04"); - case 0x02: - return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer - case 0x03: - return Operand(Operand::Type::literal, "$06"); - case 0x04: - return Operand(Operand::Type::literal, "$fb");// unused - case 0x05: - return Operand(Operand::Type::literal, "$fc");// unused - case 0x06: - return Operand(Operand::Type::literal, "$fd");// unused - case 0x07: - return Operand(Operand::Type::literal, "$fe");// unused - case 0x08: - return Operand(Operand::Type::literal, "$22");// unused - case 0x09: - return Operand(Operand::Type::literal, "$23");// unused - case 0x0A: - return Operand(Operand::Type::literal, "$39");// Current BASIC line number - case 0x0B: - return Operand(Operand::Type::literal, "$3a");// Current BASIC line number - case 0x10: - return get_register(0x00 + offset); - case 0x11: - return get_register(0x02 + offset); - case 0x12: - return get_register(0x04 + offset); - case 0x13: - return get_register(0x06 + offset); - case 0x14: - return get_register(0x08 + offset); - case 0x15: - return get_register(0x0A + offset); - }; - throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); - } - - - static OpCode parse_opcode(Type t, const std::string &o) - { - switch (t) { - case Type::Label: - return OpCode::unknown; - case Type::Directive: - return OpCode::unknown; - case Type::Instruction: { - if (o == "movzwl") return OpCode::movzwl; - if (o == "movzbl") return OpCode::movzbl; - if (o == "shrb") return OpCode::shrb; - if (o == "shrl") return OpCode::shrl; - if (o == "xorl") return OpCode::xorl; - if (o == "andl") return OpCode::andl; - if (o == "ret") return OpCode::ret; - if (o == "movb") return OpCode::movb; - if (o == "cmpb") return OpCode::cmpb; - if (o == "movl") return OpCode::movl; - if (o == "jmp") return OpCode::jmp; - if (o == "testb") return OpCode::testb; - if (o == "incl") return OpCode::incl; - if (o == "sarl") return OpCode::sarl; - if (o == "decl") return OpCode::decl; - if (o == "jne") return OpCode::jne; - if (o == "je") return OpCode::je; - if (o == "js") return OpCode::js; - if (o == "subl") return OpCode::subl; - if (o == "subb") return OpCode::subb; - if (o == "addl") return OpCode::addl; - if (o == "addb") return OpCode::addb; - if (o == "sall") return OpCode::sall; - if (o == "orl") return OpCode::orl; - if (o == "andb") return OpCode::andb; - if (o == "orb") return OpCode::orb; - if (o == "decb") return OpCode::decb; - if (o == "incb") return OpCode::incb; - if (o == "rep") return OpCode::rep; - if (o == "notb") return OpCode::notb; - if (o == "negb") return OpCode::negb; - if (o == "sbbb") return OpCode::sbbb; - if (o == "pushl") return OpCode::pushl; - if (o == "retl") return OpCode::retl; - if (o == "call") return OpCode::call; - if (o == "calll") return OpCode::call; - } - } - throw std::runtime_error("Unknown opcode: " + o); - } - - static Operand parse_operand(std::string o) - { - if (o.empty()) { - return Operand(); - } - - if (o[0] == '%') { - if (o == "%al") { - return Operand(Operand::Type::reg, 0x00); - } else if (o == "%ah") { - return Operand(Operand::Type::reg, 0x01); - } else if (o == "%bl") { - return Operand(Operand::Type::reg, 0x02); - } else if (o == "%bh") { - return Operand(Operand::Type::reg, 0x03); - } else if (o == "%cl") { - return Operand(Operand::Type::reg, 0x04); - } else if (o == "%ch") { - return Operand(Operand::Type::reg, 0x05); - } else if (o == "%dl") { - return Operand(Operand::Type::reg, 0x06); - } else if (o == "%dh") { - return Operand(Operand::Type::reg, 0x07); - } else if (o == "%sil") { - return Operand(Operand::Type::reg, 0x08); - } else if (o == "%dil") { - return Operand(Operand::Type::reg, 0x0A); - } else if (o == "%ax" || o == "%eax") { - return Operand(Operand::Type::reg, 0x10); - } else if (o == "%bx" || o == "%ebx") { - return Operand(Operand::Type::reg, 0x11); - } else if (o == "%cx" || o == "%ecx") { - return Operand(Operand::Type::reg, 0x12); - } else if (o == "%dx" || o == "%edx") { - return Operand(Operand::Type::reg, 0x13); - } else if (o == "%si" || o == "%esi") { - return Operand(Operand::Type::reg, 0x14); - } else if (o == "%di" || o == "%edi") { - return Operand(Operand::Type::reg, 0x15); - } else { - throw std::runtime_error("Unknown register operand: '" + o + "'"); - } - } else { - return Operand(Operand::Type::literal, std::move(o)); - } - } - - i386(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1 = "", std::string o2 = "") - : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), - opcode(parse_opcode(t, t_opcode)), operand1(parse_operand(o1)), operand2(parse_operand(o2)) - { - } - - int line_num; - std::string line_text; - OpCode opcode; - Operand operand1; - Operand operand2; -}; - struct AVR : ASMLine { @@ -1079,7 +884,6 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode instructions.emplace_back(mos6502::OpCode::bcs, o1); return; } - } case AVR::OpCode::breq: { @@ -1089,291 +893,11 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode case AVR::OpCode::unknown: { throw std::runtime_error("Could not translate 'unknown' instruction"); } - } throw std::runtime_error("Could not translate unhandled instruction"); } -void translate_instruction(std::vector &instructions, const i386::OpCode op, const Operand &o1, const Operand &o2) -{ - switch (op) { - case i386::OpCode::ret: - instructions.emplace_back(mos6502::OpCode::rts); - break; - case i386::OpCode::retl: - /// \todo I don't know if this is completely correct for retl translation - instructions.emplace_back(mos6502::OpCode::rts); - break; - case i386::OpCode::movl: - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); - } else { - throw std::runtime_error("Cannot translate movl instruction"); - } - break; - case i386::OpCode::xorl: - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg - && o1.reg_num == o2.reg_num) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1)); - } else { - throw std::runtime_error("Cannot translate xorl instruction"); - } - break; - case i386::OpCode::movb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else { - throw std::runtime_error("Cannot translate movb instruction"); - } - break; - case i386::OpCode::orb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::ORA, o2); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else { - throw std::runtime_error("Cannot translate orb instruction"); - } - break; - - case i386::OpCode::movzbl: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, o1); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else { - throw std::runtime_error("Cannot translate movzbl instruction"); - } - break; - case i386::OpCode::shrb: - if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { - const auto do_shift = [&instructions](const int reg_num) { - instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num)); - }; - - if (o1.type == Operand::Type::literal) { - const auto count = parse_8bit_literal(o1.value); - for (int i = 0; i < count; ++i) { - do_shift(o2.reg_num); - } - } else { - do_shift(o1.reg_num); - } - } else { - throw std::runtime_error("Cannot translate shrb instruction"); - } - break; - case i386::OpCode::shrl: - if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) { - const auto do_shift = [&instructions](const int reg_num) { - instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::ror, i386::get_register(reg_num)); - }; - - if (o1.type == Operand::Type::literal) { - const auto count = parse_8bit_literal(o1.value); - for (int i = 0; i < count; ++i) { - do_shift(o2.reg_num); - } - } else { - do_shift(o1.reg_num); - } - } else { - throw std::runtime_error("Cannot translate shrl instruction"); - } - break; - case i386::OpCode::testb: - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) { - // this just tests the register for 0 - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - // instructions.emplace_back(mos6502::OpCode::bit, Operand(Operand::Type::literal, "#$00")); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) { - // ands the values - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - // ands the values - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - // ands the values - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::bit, o2); - } else { - throw std::runtime_error("Cannot translate testb instruction"); - } - break; - case i386::OpCode::decb: - if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::dec, i386::get_register(o1.reg_num)); - } else { - instructions.emplace_back(mos6502::OpCode::dec, o1); - } - break; - case i386::OpCode::incb: - if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); - } else { - instructions.emplace_back(mos6502::OpCode::inc, o1); - } - break; - case i386::OpCode::jne: - instructions.emplace_back(mos6502::OpCode::bne, o1); - break; - case i386::OpCode::je: - instructions.emplace_back(mos6502::OpCode::beq, o1); - break; - case i386::OpCode::js: - instructions.emplace_back(mos6502::OpCode::bmi, o1); - break; - case i386::OpCode::jmp: - instructions.emplace_back(mos6502::OpCode::jmp, o1); - break; - case i386::OpCode::addb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num)); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::adc, o2); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::adc, o2); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else { - throw std::runtime_error("Cannot translate addb instruction"); - } - break; - case i386::OpCode::cmpb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num)); - instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value))); - } else { - throw std::runtime_error("Cannot translate cmpb instruction"); - } - break; - case i386::OpCode::andb: - if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) { - const auto reg = i386::get_register(o2.reg_num); - instructions.emplace_back(mos6502::OpCode::lda, reg); - instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, reg); - } else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) { - const auto reg = i386::get_register(o2.reg_num); - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value))); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else { - throw std::runtime_error("Cannot translate andb instruction"); - } - break; - case i386::OpCode::negb: - if (o1.type == Operand::Type::reg) { - // perform a two's complement of the register location - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num)); - } else { - throw std::runtime_error("Cannot translate negb instruction"); - } - break; - case i386::OpCode::notb: - if (o1.type == Operand::Type::reg) { - // exclusive or against 0xff to perform a logical not - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff")); - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num)); - } else { - throw std::runtime_error("Cannot translate notb instruction"); - } - break; - case i386::OpCode::subb: - // DEST <- DEST - SRC - // o2 = o2 - o1 - // Ensure that we set the carry flag before performing the subtraction - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) { - instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::sbc, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, o2); - } else { - throw std::runtime_error("Cannot translate subb instruction"); - } - break; - case i386::OpCode::pushl: - if (o1.type == Operand::Type::reg) { - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num)); - instructions.emplace_back(mos6502::OpCode::pha); - instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1)); - instructions.emplace_back(mos6502::OpCode::pha); - } else { - throw std::runtime_error("Cannot translate pushl instruction"); - } - break; - - case i386::OpCode::sbbb: - // DEST <- (DEST – (SRC + CF)) - // o2 <- (o2 - (o1 + cf)) - // if o1 and o2 are the same we get - // o2 <- (o2 - (o2 + cf)) - // o2 <- -cf - if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg - && o1.reg_num == o2.reg_num) { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00"));// reset a - instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#$00"));// subtract out the carry flag - instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff"));// invert the bits - instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));// place the value - } else { - throw std::runtime_error("Cannot translate sbbb instruction"); - } - break; - - case i386::OpCode::call: - instructions.emplace_back(mos6502::OpCode::jsr, o1); - break; - - default: - throw std::runtime_error("Cannot translate unhandled instruction"); - } -} - enum class LogLevel { Warning, Error @@ -1391,8 +915,7 @@ std::string to_string(const LogLevel ll) } -template -void log(LogLevel ll, const FromArch &i, const std::string &message) +void log(LogLevel ll, const AVR &i, const std::string &message) { std::cerr << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n"; } @@ -1402,8 +925,7 @@ void log(LogLevel ll, const int line_no, const std::string &line, const std::str std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; } -template -void to_mos6502(const FromArch &from_instruction, std::vector &instructions) +void to_mos6502(const AVR &from_instruction, std::vector &instructions) { try { switch (from_instruction.type) { @@ -1483,9 +1005,8 @@ bool optimize(std::vector &instructions) // it might make sense in the future to only insert these if determined they are needed? for (size_t op = 10; op < instructions.size(); ++op) { if (instructions[op].opcode == mos6502::OpCode::lda) { - if (instructions[op-1].text == "; END remove if next is lda") - { - for (size_t inner_op = op-1; inner_op > 1; --inner_op) { + if (instructions[op - 1].text == "; END remove if next is lda") { + for (size_t inner_op = op - 1; inner_op > 1; --inner_op) { instructions[inner_op] = mos6502(ASMLine::Type::Directive, "; removed unused flag fix-up: " + instructions[inner_op].to_string()); @@ -1501,11 +1022,10 @@ bool optimize(std::vector &instructions) // look for redundant load of lda after a tax for (size_t op = 0; op < instructions.size() - 3; ++op) { if (instructions[op].opcode == mos6502::OpCode::sta - && instructions[op+1].opcode == mos6502::OpCode::tax - && instructions[op+2].opcode == mos6502::OpCode::lda - && instructions[op].op.value == instructions[op+2].op.value) - { - instructions[op+2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op+2].to_string()); + && instructions[op + 1].opcode == mos6502::OpCode::tax + && instructions[op + 2].opcode == mos6502::OpCode::lda + && instructions[op].op.value == instructions[op + 2].op.value) { + instructions[op + 2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string()); return true; } } @@ -1514,8 +1034,7 @@ bool optimize(std::vector &instructions) for (size_t op = 0; op < instructions.size(); ++op) { // todo, make sure this is in the register map if (instructions[op].opcode == mos6502::OpCode::sta - && instructions[op].op.value.size() == 3) - { + && instructions[op].op.value.size() == 3) { for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) { if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) { // we just found a use of ourselves back, abort the search, there's probably something else going on @@ -1532,7 +1051,7 @@ bool optimize(std::vector &instructions) } if (instructions[next_op].opcode == mos6502::OpCode::sta - && instructions[next_op].op.value == instructions[op].op.value) { + && instructions[next_op].op.value == instructions[op].op.value) { // looks like we found a redundant store, remove the first one instructions[op] = mos6502(ASMLine::Type::Directive, "; removed redundant sta: " + instructions[op].to_string()); @@ -1540,7 +1059,6 @@ bool optimize(std::vector &instructions) } } } - } for (size_t op = 0; op < instructions.size() - 1; ++op) { @@ -1689,12 +1207,6 @@ void setup_target_cpu_state([[maybe_unused]] const std::vector &instruction new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1)); } - -void setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, [[maybe_unused]] std::vector &new_instructions) -{ -} - -template void run(std::istream &input) { std::regex Comment(R"(\s*\#.*)"); @@ -1707,7 +1219,7 @@ void run(std::istream &input) int lineno = 0; - std::vector instructions; + std::vector instructions; while (input.good()) { std::string line; @@ -1875,19 +1387,6 @@ int main([[maybe_unused]] const int argc, const char *argv[]) } }(); - const bool is_386 = [&]() { - for (std::size_t index = 0; index < static_cast(argc); ++index) { - if (strstr(argv[index], "x86") != nullptr) { - return true; - } - } - return false; - }(); - - if (!is_386) { - std::cout << "; AVR Mode\n"; - run(input); - } else { - run(input); - } + std::cout << "; AVR Mode\n"; + run(input); } From 7a5926b5fd0793a3c001777e3ea09831c08c2a94 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 16:49:33 -0600 Subject: [PATCH 17/27] Move start address and make c64 auto-startable --- src/6502-c++.cpp | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 4e800d2..7686d64 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -1200,13 +1200,6 @@ bool fix_overwritten_flags(std::vector &instructions) return false; } -void setup_target_cpu_state([[maybe_unused]] const std::vector &instructions, std::vector &new_instructions) -{ - // set __zero_reg__ (reg 1 on AVR) to 0 - new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1)); -} - void run(std::istream &input) { std::regex Comment(R"(\s*\#.*)"); @@ -1320,11 +1313,16 @@ void run(std::istream &input) } } + constexpr static auto start_address = 0x0801; std::vector new_instructions; - new_instructions.emplace_back(ASMLine::Type::Directive, ".word $1000"); - new_instructions.emplace_back(ASMLine::Type::Directive, "* = $1000"); - setup_target_cpu_state(instructions, new_instructions); + new_instructions.emplace_back(ASMLine::Type::Directive, ".word " + std::to_string(start_address)); + new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address)); + new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC"); + new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); + // set __zero_reg__ (reg 1 on AVR) to 0 + new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); + new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1)); new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); From 3f9fd795860de3fdc476c483587539c3b08b89ea Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 17:50:36 -0600 Subject: [PATCH 18/27] Start to cleanup layout and code --- .clang-format | 18 +-- src/6502-c++.cpp | 411 +++++++++++++++++++++++++---------------------- 2 files changed, 227 insertions(+), 202 deletions(-) diff --git a/.clang-format b/.clang-format index 4ede542..46229dd 100644 --- a/.clang-format +++ b/.clang-format @@ -1,25 +1,25 @@ AccessModifierOffset: -2 AlignAfterOpenBracket: DontAlign -AlignConsecutiveAssignments: false -AlignConsecutiveDeclarations: false +AlignConsecutiveAssignments: Consecutive +AlignConsecutiveDeclarations: Consecutive AlignEscapedNewlines: Left AlignOperands: true AlignTrailingComments: false AllowAllParametersOfDeclarationOnNextLine: false -AllowShortBlocksOnASingleLine: true -AllowShortCaseLabelsOnASingleLine: false +AllowShortBlocksOnASingleLine: Always +AllowShortCaseLabelsOnASingleLine: true AllowShortFunctionsOnASingleLine: All -AllowShortIfStatementsOnASingleLine: true +AllowShortIfStatementsOnASingleLine: WithoutElse AllowShortLoopsOnASingleLine: true AlwaysBreakAfterDefinitionReturnType: None AlwaysBreakAfterReturnType: None AlwaysBreakBeforeMultilineStrings: true -AlwaysBreakTemplateDeclarations: false +AlwaysBreakTemplateDeclarations: MultiLine BinPackArguments: false BinPackParameters: false BraceWrapping: + AfterCaseLabel: false AfterClass: true - AfterControlStatement: false AfterEnum: false AfterFunction: true AfterNamespace: false @@ -79,7 +79,7 @@ ObjCSpaceAfterProperty: true ObjCSpaceBeforeProtocolList: false PointerAlignment: Right ReflowComments: true -SortIncludes: false +SortIncludes: CaseInsensitive SortUsingDeclarations: false SpaceAfterCStyleCast: false SpaceAfterTemplateKeyword: false @@ -92,7 +92,7 @@ SpacesInCStyleCastParentheses: false SpacesInContainerLiterals: true SpacesInParentheses: false SpacesInSquareBrackets: false -Standard: Cpp11 +Standard: c++20 TabWidth: 8 UseTab: Never diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 7686d64..d49b362 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -1,12 +1,13 @@ -#include -#include -#include -#include -#include #include -#include #include #include +#include +#include +#include +#include +#include +#include +#include struct ASMLine { @@ -18,7 +19,7 @@ struct ASMLine ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {} - Type type; + Type type; std::string text; }; @@ -72,8 +73,8 @@ struct Operand reg /*ister*/ }; - Type type = Type::empty; - int reg_num = 0; + Type type = Type::empty; + int reg_num = 0; std::string value; Operand() = default; @@ -101,43 +102,56 @@ struct mos6502 : ASMLine { enum class OpCode { unknown, - lda, + + adc, + AND, asl, - rol, - ldy, - tay, - tya, - tax, - txa, + + bcc, + bcs, + beq, + bit, + bmi, + bne, + bpl, + cpy, + cmp, + clc, + + dec, + eor, + + inc, + + jmp, + jsr, + + lda, + ldy, + lsr, + + ORA, + + pha, + php, + pla, + plp, + + rol, + ror, + rts, + + sbc, + sec, sta, sty, - pha, - pla, - php, - plp, - lsr, - ror, - AND, - inc, - dec, - ORA, - cmp, - bne, - beq, - bmi, - bpl, - jmp, - adc, - sbc, - rts, - clc, - sec, - bit, - jsr, - bcc, - bcs + + tax, + tay, + txa, + tya, }; static bool get_is_branch(const OpCode o) @@ -150,37 +164,38 @@ struct mos6502 : ASMLine case OpCode::bcc: case OpCode::bcs: return true; - case OpCode::lda: - case OpCode::ldy: - case OpCode::tay: - case OpCode::tya: - case OpCode::tax: - case OpCode::txa: - case OpCode::cpy: - case OpCode::eor: - case OpCode::sta: - case OpCode::sty: - case OpCode::pha: - case OpCode::pla: - case OpCode::php: - case OpCode::plp: - case OpCode::lsr: - case OpCode::ror: + case OpCode::adc: case OpCode::AND: - case OpCode::inc: - case OpCode::dec: - case OpCode::ORA: + case OpCode::asl: + case OpCode::bit: + case OpCode::cpy: case OpCode::cmp: + case OpCode::clc: + case OpCode::dec: + case OpCode::eor: + case OpCode::inc: case OpCode::jmp: case OpCode::jsr: - case OpCode::adc: - case OpCode::sbc: - case OpCode::rts: - case OpCode::clc: - case OpCode::sec: - case OpCode::bit: - case OpCode::asl: + case OpCode::lda: + case OpCode::ldy: + case OpCode::lsr: + case OpCode::ORA: + case OpCode::pha: + case OpCode::php: + case OpCode::pla: + case OpCode::plp: case OpCode::rol: + case OpCode::ror: + case OpCode::rts: + case OpCode::sbc: + case OpCode::sec: + case OpCode::sta: + case OpCode::sty: + case OpCode::tax: + case OpCode::tay: + case OpCode::txa: + case OpCode::tya: + case OpCode::unknown: break; } @@ -190,44 +205,44 @@ struct mos6502 : ASMLine static bool get_is_comparison(const OpCode o) { switch (o) { + case OpCode::bit: case OpCode::cmp: case OpCode::cpy: - case OpCode::bit: return true; - case OpCode::lda: - case OpCode::ldy: - case OpCode::tay: - case OpCode::tya: - case OpCode::tax: - case OpCode::txa: - case OpCode::eor: - case OpCode::sta: - case OpCode::sty: - case OpCode::pha: - case OpCode::pla: - case OpCode::php: - case OpCode::plp: - case OpCode::lsr: - case OpCode::ror: + case OpCode::adc: case OpCode::AND: - case OpCode::inc: - case OpCode::dec: - case OpCode::ORA: - case OpCode::jmp: - case OpCode::jsr: + case OpCode::asl: + case OpCode::beq: case OpCode::bne: case OpCode::bmi: - case OpCode::beq: case OpCode::bpl: - case OpCode::bcs: case OpCode::bcc: - case OpCode::adc: - case OpCode::sbc: - case OpCode::rts: + case OpCode::bcs: case OpCode::clc: - case OpCode::sec: + case OpCode::dec: + case OpCode::eor: + case OpCode::inc: + case OpCode::jmp: + case OpCode::jsr: + case OpCode::lda: + case OpCode::ldy: + case OpCode::lsr: + case OpCode::ORA: + case OpCode::pha: + case OpCode::php: + case OpCode::pla: + case OpCode::plp: case OpCode::rol: - case OpCode::asl: + case OpCode::ror: + case OpCode::rts: + case OpCode::sbc: + case OpCode::sec: + case OpCode::sta: + case OpCode::sty: + case OpCode::tax: + case OpCode::tay: + case OpCode::txa: + case OpCode::tya: case OpCode::unknown: break; } @@ -236,7 +251,7 @@ struct mos6502 : ASMLine explicit mos6502(const OpCode o) - : ASMLine(Type::Instruction, to_string(o)), opcode(o), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) + : ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) { } @@ -246,11 +261,11 @@ struct mos6502 : ASMLine } mos6502(const OpCode o, Operand t_o) - : ASMLine(Type::Instruction, to_string(o)), opcode(o), op(std::move(t_o)), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) + : ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), op(std::move(t_o)), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) { } - static std::string to_string(const OpCode o) + constexpr static std::string_view to_string(const OpCode o) { switch (o) { case OpCode::lda: @@ -329,12 +344,12 @@ struct mos6502 : ASMLine return "bcs"; case OpCode::unknown: return ""; - }; + } return ""; } - std::string to_string() const + [[nodiscard]] std::string to_string() const { switch (type) { case ASMLine::Type::Label: @@ -349,11 +364,11 @@ struct mos6502 : ASMLine } - OpCode opcode = OpCode::unknown; - Operand op; + OpCode opcode = OpCode::unknown; + Operand op; std::string comment; - bool is_branch = false; - bool is_comparison = false; + bool is_branch = false; + bool is_comparison = false; }; @@ -361,86 +376,95 @@ struct AVR : ASMLine { enum class OpCode { unknown, - ldi, - sts, - ret, - mov, - lsl, - rol, - rcall, - ld, - subi, - sbci, - st, - lds, - lsr, + + adc, + add, andi, + + breq, + brlo, + brne, + brsh, + + clr, + com, + cpc, + cpi, + cpse, + dec, + eor, + + ld, + ldi, + lds, + lsl, + lsr, + + mov, + + pop, + push, + + rcall, + ret, + rjmp, + rol, + + sbci, + sbiw, sbrc, sbrs, - brne, - rjmp, - dec, - sbiw, - push, - pop, - com, + st, + sts, + subi, swap, - clr, - cpse, - cpi, - brlo, - add, - adc, - cpc, - brsh, - breq }; - static OpCode parse_opcode(Type t, const std::string &o) + [[nodiscard]] static constexpr OpCode parse_opcode(Type t, std::string_view o) { switch (t) { case Type::Label: case Type::Directive: return OpCode::unknown; case Type::Instruction: { - if (o == "ldi") return OpCode::ldi; - if (o == "sts") return OpCode::sts; - if (o == "ret") return OpCode::ret; - if (o == "mov") return OpCode::mov; - if (o == "lsl") return OpCode::lsl; - if (o == "rol") return OpCode::rol; - if (o == "rcall") return OpCode::rcall; - if (o == "ld") return OpCode::ld; - if (o == "subi") return OpCode::subi; - if (o == "sbci") return OpCode::sbci; - if (o == "st") return OpCode::st; - if (o == "lds") return OpCode::lds; - if (o == "lsr") return OpCode::lsr; - if (o == "andi") return OpCode::andi; - if (o == "eor") return OpCode::eor; - if (o == "sbrc") return OpCode::sbrc; - if (o == "rjmp") return OpCode::rjmp; - if (o == "sbrs") return OpCode::sbrs; - if (o == "brne") return OpCode::brne; - if (o == "dec") return OpCode::dec; - if (o == "sbiw") return OpCode::sbiw; - if (o == "push") return OpCode::push; - if (o == "pop") return OpCode::pop; - if (o == "com") return OpCode::com; - if (o == "swap") return OpCode::swap; - if (o == "clr") return OpCode::clr; - if (o == "cpse") return OpCode::cpse; - if (o == "cpi") return OpCode::cpi; - if (o == "brlo") return OpCode::brlo; - if (o == "add") return OpCode::add; - if (o == "adc") return OpCode::adc; - if (o == "cpc") return OpCode::cpc; - if (o == "brsh") return OpCode::brsh; - if (o == "breq") return OpCode::breq; + if (o == "ldi") { return OpCode::ldi; } + if (o == "sts") { return OpCode::sts; } + if (o == "ret") { return OpCode::ret; } + if (o == "mov") { return OpCode::mov; } + if (o == "lsl") { return OpCode::lsl; } + if (o == "rol") { return OpCode::rol;} + if (o == "rcall") { return OpCode::rcall;} + if (o == "ld") { return OpCode::ld;} + if (o == "subi") { return OpCode::subi;} + if (o == "sbci") { return OpCode::sbci;} + if (o == "st") { return OpCode::st;} + if (o == "lds") { return OpCode::lds;} + if (o == "lsr") { return OpCode::lsr;} + if (o == "andi") { return OpCode::andi;} + if (o == "eor") { return OpCode::eor;} + if (o == "sbrc") { return OpCode::sbrc;} + if (o == "rjmp") { return OpCode::rjmp;} + if (o == "sbrs") { return OpCode::sbrs;} + if (o == "brne") { return OpCode::brne;} + if (o == "dec") { return OpCode::dec;} + if (o == "sbiw") { return OpCode::sbiw;} + if (o == "push") { return OpCode::push;} + if (o == "pop") { return OpCode::pop;} + if (o == "com") { return OpCode::com;} + if (o == "swap") { return OpCode::swap;} + if (o == "clr") { return OpCode::clr;} + if (o == "cpse") { return OpCode::cpse;} + if (o == "cpi") { return OpCode::cpi;} + if (o == "brlo") { return OpCode::brlo;} + if (o == "add") { return OpCode::add;} + if (o == "adc") { return OpCode::adc;} + if (o == "cpc") { return OpCode::cpc;} + if (o == "brsh") { return OpCode::brsh;} + if (o == "breq") { return OpCode::breq;} } } - throw std::runtime_error("Unknown opcode: " + o); + throw std::runtime_error(fmt::format("Unknown opcode: {}")); } static int get_register_number(const char reg_name) @@ -536,7 +560,7 @@ struct AVR : ASMLine } - static Operand parse_operand(std::string o) + static Operand parse_operand(std::string_view o) { if (o.empty()) { return Operand(); @@ -545,21 +569,21 @@ struct AVR : ASMLine if (o[0] == 'r' && o.size() > 1) { return Operand(Operand::Type::reg, atoi(&o[1])); } else { - return Operand(Operand::Type::literal, std::move(o)); + return Operand(Operand::Type::literal, std::string{ o }); } } - AVR(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1 = "", std::string o2 = "") - : ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)), + AVR(const int t_line_num, std::string_view t_line_text, Type t, std::string_view t_opcode, std::string_view o1 = "", std::string_view o2 = "") + : ASMLine(t, std::string(t_opcode)), line_num(t_line_num), line_text(std::string(t_line_text)), opcode(parse_opcode(t, t_opcode)), operand1(parse_operand(o1)), operand2(parse_operand(o2)) { } - int line_num; + int line_num; std::string line_text; - OpCode opcode; - Operand operand1; - Operand operand2; + OpCode opcode; + Operand operand1; + Operand operand2; }; void indirect_load(std::vector &instructions, const std::string &from_address_low_byte, const std::string &to_address) @@ -920,7 +944,7 @@ void log(LogLevel ll, const AVR &i, const std::string &message) std::cerr << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n"; } -void log(LogLevel ll, const int line_no, const std::string &line, const std::string &message) +void log(LogLevel ll, const std::size_t line_no, const std::string &line, const std::string &message) { std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; } @@ -1105,7 +1129,7 @@ bool optimize(std::vector &instructions) if (instructions[op].opcode == mos6502::OpCode::lda && instructions[op].op.type == Operand::Type::literal) { const auto operand = instructions[op].op; - auto op2 = op + 1; + auto op2 = op + 1; // look for multiple stores of the same value while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) { ++op2; @@ -1135,7 +1159,7 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou if (instructions[op].is_branch && std::abs(static_cast(labels[instructions[op].op.value]) - static_cast(op)) * 3 > 255) { ++branch_patch_count; const auto going_to = instructions[op].op.value; - const auto new_pos = "patch_" + std::to_string(branch_patch_count); + const auto new_pos = "patch_" + std::to_string(branch_patch_count); // uh-oh too long of a branch, have to convert this to a jump... std::map branch_mapping; @@ -1149,7 +1173,7 @@ bool fix_long_branches(std::vector &instructions, int &branch_patch_cou if (mapping != branch_mapping.end()) { const auto comment = instructions[op].comment; - instructions[op] = mos6502(mapping->second, Operand(Operand::Type::literal, new_pos)); + instructions[op] = mos6502(mapping->second, Operand(Operand::Type::literal, new_pos)); instructions.insert(std::next(std::begin(instructions), static_cast(op + 1)), mos6502(mos6502::OpCode::jmp, Operand(Operand::Type::literal, going_to))); instructions.insert(std::next(std::begin(instructions), static_cast(op + 2)), mos6502(ASMLine::Type::Label, new_pos)); instructions[op].comment = instructions[op + 1].comment = instructions[op + 2].comment = comment; @@ -1209,7 +1233,7 @@ void run(std::istream &input) std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+))"); std::regex Instruction(R"(^\s+(\S+))"); - int lineno = 0; + std::size_t lineno = 0; std::vector instructions; @@ -1220,18 +1244,19 @@ void run(std::istream &input) try { std::smatch match; if (std::regex_match(line, match, Label)) { - instructions.emplace_back(lineno, line, ASMLine::Type::Label, match[1]); + instructions.emplace_back(lineno, line, ASMLine::Type::Label, match[1].str()); } else if (std::regex_match(line, match, Comment)) { // don't care about comments } else if (std::regex_match(line, match, Directive)) { - instructions.emplace_back(lineno, line, ASMLine::Type::Directive, match[1]); + instructions.emplace_back(lineno, line, ASMLine::Type::Directive, match[1].str()); } else if (std::regex_match(line, match, BinaryInstruction)) { - instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1], match[2], match[3]); + instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1].str(), match[2].str(), match[3].str()); } else if (std::regex_match(line, match, UnaryInstruction)) { - instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1], match[2]); + instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1].str(), match[2].str()); } else if (std::regex_match(line, match, Instruction)) { - instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1]); - } else if (line == "") { + instructions.emplace_back(lineno, line, ASMLine::Type::Instruction, match[1].str()); + } else if (line.empty()) { + // skip empty lines } } catch (const std::exception &e) { log(LogLevel::Error, lineno, line, e.what()); @@ -1296,7 +1321,7 @@ void run(std::istream &input) if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8(")) { const auto potential_label = strip_lo_hi(i.operand2.value); - const auto itr1 = new_labels.find(potential_label); + const auto itr1 = new_labels.find(potential_label); if (itr1 != new_labels.end()) { i.operand2.value.replace(4, potential_label.size(), itr1->second); } @@ -1326,13 +1351,13 @@ void run(std::istream &input) new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); - int instructions_to_skip = 0; + int instructions_to_skip = 0; std::string next_label_name; for (const auto &i : instructions) { to_mos6502(i, new_instructions); // intentionally copy so we don't invalidate the reference - const auto last_instruction = new_instructions.back(); + const auto last_instruction = new_instructions.back(); const auto last_instruction_loc = new_instructions.size() - 1; if (instructions_to_skip == 1) { @@ -1343,12 +1368,12 @@ void run(std::istream &input) if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_instruction")) { instructions_to_skip = 1; - next_label_name = last_instruction.text; + next_label_name = last_instruction.text; new_instructions.erase(std::next(new_instructions.begin(), static_cast(last_instruction_loc))); } if (last_instruction.type == ASMLine::Type::Directive && last_instruction.text.starts_with("skip_next_2_instructions")) { instructions_to_skip = 2; - next_label_name = last_instruction.text; + next_label_name = last_instruction.text; new_instructions.erase(std::next(new_instructions.begin(), static_cast(last_instruction_loc))); } } From afcbe05bff6f23e48c5770ec9ddc72fae7802177 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 21:43:03 -0600 Subject: [PATCH 19/27] Some reorg and start to move to ctre --- .clang-tidy | 2 +- cmake/Conan.cmake | 1 + src/6502-c++.cpp | 622 ++++++++++++++++++++++----------------------- src/CMakeLists.txt | 1 + 4 files changed, 307 insertions(+), 319 deletions(-) diff --git a/.clang-tidy b/.clang-tidy index f95f74f..4db910d 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -1,5 +1,5 @@ --- -Checks: '*,-fuchsia-*,-google-*,-zircon-*,-abseil-*,-modernize-use-trailing-return-type,-llvm*' +Checks: '*,-fuchsia-*,-google-*,-zircon-*,-abseil-*,-modernize-use-trailing-return-type,-llvm*,-altera*,-misc-non-private-member-variables-in-classes,-readability-else-after-return' WarningsAsErrors: '*' HeaderFilterRegex: '' FormatStyle: none diff --git a/cmake/Conan.cmake b/cmake/Conan.cmake index a514b15..d885b50 100644 --- a/cmake/Conan.cmake +++ b/cmake/Conan.cmake @@ -14,6 +14,7 @@ macro(run_conan) docopt.cpp/0.6.3 fmt/7.1.3 spdlog/1.8.5 + ctre/3.3.4 OPTIONS ${CONAN_EXTRA_OPTIONS} BASIC_SETUP diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index d49b362..28a64b4 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -1,5 +1,7 @@ #include #include +#include +#include #include #include #include @@ -7,63 +9,6 @@ #include #include #include -#include - -struct ASMLine -{ - enum class Type { - Label, - Instruction, - Directive - }; - - ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {} - - Type type; - std::string text; -}; - -int parse_8bit_literal(const std::string &s) -{ - return std::stoi(std::string(std::next(std::begin(s)), std::end(s))); -} - - -std::string strip_lo_hi(const std::string &s) -{ - if ((s.starts_with("lo8(") || s.starts_with("hi8(")) - && s.ends_with(")")) { - return s.substr(4, s.size() - 5); - } - - return s; -} - -std::string fixup_8bit_literal(const std::string &s) -{ - if (s[0] == '$') { - return "#" + std::to_string(static_cast(parse_8bit_literal(s))); - } - - if (s.starts_with("0x")) { - return "#$" + s.substr(2); - } - - if (s.starts_with("lo8(") && s.ends_with(")")) { - return "#<" + strip_lo_hi(s); - } - if (s.starts_with("hi8(") && s.ends_with(")")) { - return "#>" + strip_lo_hi(s); - } - - const auto is_num = std::all_of(begin(s), end(s), [](const auto c) { return (c >= '0' && c <= '9') || c == '-'; }); - - if (is_num) { - return "#<" + s; - } - - return s; -} struct Operand { @@ -87,7 +32,6 @@ struct Operand Operand(const Type t, std::string v) : type(t), value(std::move(v)) { - assert(type == Type::literal); } @@ -98,6 +42,164 @@ struct Operand } }; +struct mos6502; + +class Personality +{ +public: + virtual void insert_autostart_sequence(std::vector &new_instructions) const = 0; + [[nodiscard]] virtual Operand get_register(const int reg_num) const = 0; + + virtual ~Personality() = default; + Personality(const Personality &) = delete; + Personality(Personality &&) = delete; + Personality &operator=(const Personality &) = delete; + Personality &operator=(Personality &&) = delete; + +protected: + Personality() = default; +}; + +struct ASMLine +{ + enum class Type { + Label, + Instruction, + Directive + }; + + ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {} + + Type type; + std::string text; +}; + +struct C64 : Personality +{ + + void insert_autostart_sequence(std::vector &new_instructions) const override { + new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC"); + new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); + } + + [[nodiscard]] Operand get_register(const int reg_num) const override + { + switch (reg_num) { + // http://sta.c64.org/cbm64mem.html + case 0: + return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232 + case 1: + return Operand(Operand::Type::literal, "$a8");// counter for rs232 + case 2: + return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer + case 3: + return Operand(Operand::Type::literal, "$06"); + case 4: + return Operand(Operand::Type::literal, "$fb");// unused + case 5: + return Operand(Operand::Type::literal, "$fc");// unused + case 6: + return Operand(Operand::Type::literal, "$fd");// unused + case 7: + return Operand(Operand::Type::literal, "$fe");// unused + case 8: + return Operand(Operand::Type::literal, "$22");// unused + case 9: + return Operand(Operand::Type::literal, "$23");// unused + case 10: + return Operand(Operand::Type::literal, "$39");// Current BASIC line number + case 11: + return Operand(Operand::Type::literal, "$3a");// Current BASIC line number + case 12: + return Operand(Operand::Type::literal, "$61");// arithmetic register #1 + case 13: + return Operand(Operand::Type::literal, "$62"); + case 14: + return Operand(Operand::Type::literal, "$63"); + case 15: + return Operand(Operand::Type::literal, "$64"); + case 16: + return Operand(Operand::Type::literal, "$65"); + case 17: + return Operand(Operand::Type::literal, "$69");// arithmetic register #2 + case 18: + return Operand(Operand::Type::literal, "$6a"); + case 19: + return Operand(Operand::Type::literal, "$6b"); + case 20: + return Operand(Operand::Type::literal, "$6c"); + case 21: + return Operand(Operand::Type::literal, "$6d"); + case 22: + return Operand(Operand::Type::literal, "$57");// arithmetic register #3 + case 23: + return Operand(Operand::Type::literal, "$58"); + case 24: + return Operand(Operand::Type::literal, "$59"); + case 25: + return Operand(Operand::Type::literal, "$5a"); + case 26: + return Operand(Operand::Type::literal, "$5b"); + case 27: + return Operand(Operand::Type::literal, "$5c");// arithmetic register #4 + case 28: + return Operand(Operand::Type::literal, "$5d"); + case 29: + return Operand(Operand::Type::literal, "$5e"); + case 30: + return Operand(Operand::Type::literal, "$5f"); + case 31: + return Operand(Operand::Type::literal, "$60"); + } + throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); + } +}; + + +int parse_8bit_literal(const std::string &s) +{ + return std::stoi(std::string(std::next(std::begin(s)), std::end(s))); +} + + +std::string_view strip_lo_hi(std::string_view s) +{ + const auto matcher = ctre::match; + + if (const auto results = matcher(s); results) { + return results.get<2>(); + } + + return s; +} + +std::string fixup_8bit_literal(const std::string &s) +{ + if (s[0] == '$') { + return "#" + std::to_string(static_cast(parse_8bit_literal(s))); + } + + if (s.starts_with("0x")) { + return "#$" + s.substr(2); + } + + if (s.starts_with("lo8(")) { + return fmt::format("#<{}", strip_lo_hi(s)); + } + if (s.starts_with("hi8(")) { + return fmt::format("#>{}", strip_lo_hi(s)); + } + + const auto is_num = std::all_of(begin(s), end(s), [](const auto c) { return (c >= '0' && c <= '9') || c == '-'; }); + + if (is_num) { + return "#<" + s; + } + + return s; +} + + struct mos6502 : ASMLine { enum class OpCode { @@ -268,82 +370,44 @@ struct mos6502 : ASMLine constexpr static std::string_view to_string(const OpCode o) { switch (o) { - case OpCode::lda: - return "lda"; - case OpCode::asl: - return "asl"; - case OpCode::rol: - return "rol"; - case OpCode::ldy: - return "ldy"; - case OpCode::tay: - return "tay"; - case OpCode::tya: - return "tya"; - case OpCode::tax: - return "tax"; - case OpCode::txa: - return "txa"; - case OpCode::cpy: - return "cpy"; - case OpCode::eor: - return "eor"; - case OpCode::sta: - return "sta"; - case OpCode::sty: - return "sty"; - case OpCode::pha: - return "pha"; - case OpCode::pla: - return "pla"; - case OpCode::php: - return "php"; - case OpCode::plp: - return "plp"; - case OpCode::lsr: - return "lsr"; - case OpCode::ror: - return "ror"; - case OpCode::AND: - return "and"; - case OpCode::inc: - return "inc"; - case OpCode::dec: - return "dec"; - case OpCode::ORA: - return "ora"; - case OpCode::cmp: - return "cmp"; - case OpCode::bne: - return "bne"; - case OpCode::bmi: - return "bmi"; - case OpCode::beq: - return "beq"; - case OpCode::jmp: - return "jmp"; - case OpCode::adc: - return "adc"; - case OpCode::sbc: - return "sbc"; - case OpCode::rts: - return "rts"; - case OpCode::clc: - return "clc"; - case OpCode::sec: - return "sec"; - case OpCode::bit: - return "bit"; - case OpCode::jsr: - return "jsr"; - case OpCode::bpl: - return "bpl"; - case OpCode::bcc: - return "bcc"; - case OpCode::bcs: - return "bcs"; - case OpCode::unknown: - return ""; + case OpCode::lda: return "lda"; + case OpCode::asl: return "asl"; + case OpCode::rol: return "rol"; + case OpCode::ldy: return "ldy"; + case OpCode::tay: return "tay"; + case OpCode::tya: return "tya"; + case OpCode::tax: return "tax"; + case OpCode::txa: return "txa"; + case OpCode::cpy: return "cpy"; + case OpCode::eor: return "eor"; + case OpCode::sta: return "sta"; + case OpCode::sty: return "sty"; + case OpCode::pha: return "pha"; + case OpCode::pla: return "pla"; + case OpCode::php: return "php"; + case OpCode::plp: return "plp"; + case OpCode::lsr: return "lsr"; + case OpCode::ror: return "ror"; + case OpCode::AND: return "and"; + case OpCode::inc: return "inc"; + case OpCode::dec: return "dec"; + case OpCode::ORA: return "ora"; + case OpCode::cmp: return "cmp"; + case OpCode::bne: return "bne"; + case OpCode::bmi: return "bmi"; + case OpCode::beq: return "beq"; + case OpCode::jmp: return "jmp"; + case OpCode::adc: return "adc"; + case OpCode::sbc: return "sbc"; + case OpCode::rts: return "rts"; + case OpCode::clc: return "clc"; + case OpCode::sec: return "sec"; + case OpCode::bit: return "bit"; + case OpCode::jsr: return "jsr"; + case OpCode::bpl: return "bpl"; + case OpCode::bcc: return "bcc"; + case OpCode::bcs: return "bcs"; + case OpCode::unknown: return ""; } return ""; @@ -356,10 +420,9 @@ struct mos6502 : ASMLine return text;// + ':'; case ASMLine::Type::Directive: case ASMLine::Type::Instruction: { - const std::string line = '\t' + text + ' ' + op.value; - return line + std::string(static_cast(std::max(15 - static_cast(line.size()), 1)), ' ') + "; " + comment; + return fmt::format("\t{} {:15}; {}", text, op.value, comment); + } } - }; throw std::runtime_error("Unable to render: " + text); } @@ -433,35 +496,35 @@ struct AVR : ASMLine if (o == "ret") { return OpCode::ret; } if (o == "mov") { return OpCode::mov; } if (o == "lsl") { return OpCode::lsl; } - if (o == "rol") { return OpCode::rol;} - if (o == "rcall") { return OpCode::rcall;} - if (o == "ld") { return OpCode::ld;} - if (o == "subi") { return OpCode::subi;} - if (o == "sbci") { return OpCode::sbci;} - if (o == "st") { return OpCode::st;} - if (o == "lds") { return OpCode::lds;} - if (o == "lsr") { return OpCode::lsr;} - if (o == "andi") { return OpCode::andi;} - if (o == "eor") { return OpCode::eor;} - if (o == "sbrc") { return OpCode::sbrc;} - if (o == "rjmp") { return OpCode::rjmp;} - if (o == "sbrs") { return OpCode::sbrs;} - if (o == "brne") { return OpCode::brne;} - if (o == "dec") { return OpCode::dec;} - if (o == "sbiw") { return OpCode::sbiw;} - if (o == "push") { return OpCode::push;} - if (o == "pop") { return OpCode::pop;} - if (o == "com") { return OpCode::com;} - if (o == "swap") { return OpCode::swap;} - if (o == "clr") { return OpCode::clr;} - if (o == "cpse") { return OpCode::cpse;} - if (o == "cpi") { return OpCode::cpi;} - if (o == "brlo") { return OpCode::brlo;} - if (o == "add") { return OpCode::add;} - if (o == "adc") { return OpCode::adc;} - if (o == "cpc") { return OpCode::cpc;} - if (o == "brsh") { return OpCode::brsh;} - if (o == "breq") { return OpCode::breq;} + if (o == "rol") { return OpCode::rol; } + if (o == "rcall") { return OpCode::rcall; } + if (o == "ld") { return OpCode::ld; } + if (o == "subi") { return OpCode::subi; } + if (o == "sbci") { return OpCode::sbci; } + if (o == "st") { return OpCode::st; } + if (o == "lds") { return OpCode::lds; } + if (o == "lsr") { return OpCode::lsr; } + if (o == "andi") { return OpCode::andi; } + if (o == "eor") { return OpCode::eor; } + if (o == "sbrc") { return OpCode::sbrc; } + if (o == "rjmp") { return OpCode::rjmp; } + if (o == "sbrs") { return OpCode::sbrs; } + if (o == "brne") { return OpCode::brne; } + if (o == "dec") { return OpCode::dec; } + if (o == "sbiw") { return OpCode::sbiw; } + if (o == "push") { return OpCode::push; } + if (o == "pop") { return OpCode::pop; } + if (o == "com") { return OpCode::com; } + if (o == "swap") { return OpCode::swap; } + if (o == "clr") { return OpCode::clr; } + if (o == "cpse") { return OpCode::cpse; } + if (o == "cpi") { return OpCode::cpi; } + if (o == "brlo") { return OpCode::brlo; } + if (o == "add") { return OpCode::add; } + if (o == "adc") { return OpCode::adc; } + if (o == "cpc") { return OpCode::cpc; } + if (o == "brsh") { return OpCode::brsh; } + if (o == "breq") { return OpCode::breq; } } } throw std::runtime_error(fmt::format("Unknown opcode: {}")); @@ -482,84 +545,6 @@ struct AVR : ASMLine throw std::runtime_error("Unknown register name"); } - static Operand get_register(const char reg_name, const int byte = 0) - { - return get_register(get_register_number(reg_name), byte); - } - - static Operand get_register(const int reg_num, [[maybe_unused]] const int offset = 0) - { - switch (reg_num) { - // http://sta.c64.org/cbm64mem.html - case 0: - return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232 - case 1: - return Operand(Operand::Type::literal, "$a8");// counter for rs232 - case 2: - return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer - case 3: - return Operand(Operand::Type::literal, "$06"); - case 4: - return Operand(Operand::Type::literal, "$fb");// unused - case 5: - return Operand(Operand::Type::literal, "$fc");// unused - case 6: - return Operand(Operand::Type::literal, "$fd");// unused - case 7: - return Operand(Operand::Type::literal, "$fe");// unused - case 8: - return Operand(Operand::Type::literal, "$22");// unused - case 9: - return Operand(Operand::Type::literal, "$23");// unused - case 10: - return Operand(Operand::Type::literal, "$39");// Current BASIC line number - case 11: - return Operand(Operand::Type::literal, "$3a");// Current BASIC line number - case 12: - return Operand(Operand::Type::literal, "$61");// arithmetic register #1 - case 13: - return Operand(Operand::Type::literal, "$62"); - case 14: - return Operand(Operand::Type::literal, "$63"); - case 15: - return Operand(Operand::Type::literal, "$64"); - case 16: - return Operand(Operand::Type::literal, "$65"); - case 17: - return Operand(Operand::Type::literal, "$69");// arithmetic register #2 - case 18: - return Operand(Operand::Type::literal, "$6a"); - case 19: - return Operand(Operand::Type::literal, "$6b"); - case 20: - return Operand(Operand::Type::literal, "$6c"); - case 21: - return Operand(Operand::Type::literal, "$6d"); - case 22: - return Operand(Operand::Type::literal, "$57");// arithmetic register #3 - case 23: - return Operand(Operand::Type::literal, "$58"); - case 24: - return Operand(Operand::Type::literal, "$59"); - case 25: - return Operand(Operand::Type::literal, "$5a"); - case 26: - return Operand(Operand::Type::literal, "$5b"); - case 27: - return Operand(Operand::Type::literal, "$5c");// arithmetic register #4 - case 28: - return Operand(Operand::Type::literal, "$5d"); - case 29: - return Operand(Operand::Type::literal, "$5e"); - case 30: - return Operand(Operand::Type::literal, "$5f"); - case 31: - return Operand(Operand::Type::literal, "$60"); - } - throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); - } - - static Operand parse_operand(std::string_view o) { if (o.empty()) { @@ -623,33 +608,33 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) } -void subtract_16_bit(std::vector &instructions, int reg, const std::uint16_t value) +void subtract_16_bit(const Personality &personality, std::vector &instructions, int reg, const std::uint16_t value) { //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); instructions.emplace_back(mos6502::OpCode::sec); - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg)); - instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string(value & 0xFF))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg)); - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg + 1)); - instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8) & 0xFF))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value & 0xFFu)))); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8u) & 0xFFu))); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg + 1)); instructions.emplace_back(mos6502::OpCode::tax); fixup_16_bit_N_Z_flags(instructions); } -void increment_16_bit(std::vector &instructions, int reg) +void increment_16_bit(const Personality &personality, std::vector &instructions, int reg) { //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg)); instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#1")); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg)); - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg + 1)); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#0")); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg + 1)); } -void translate_instruction(std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) +void translate_instruction(const Personality &personality, std::vector &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2) { const auto translate_register_number = [](const Operand ®) { if (reg.value == "__zero_reg__") { @@ -666,40 +651,40 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode switch (op) { case AVR::OpCode::dec: - instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::dec, personality.get_register(o1_reg_num)); return; case AVR::OpCode::ldi: instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; case AVR::OpCode::sts: - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o2_reg_num)); instructions.emplace_back(mos6502::OpCode::sta, Operand(o1.type, o1.value)); return; case AVR::OpCode::ret: instructions.emplace_back(mos6502::OpCode::rts); return; case AVR::OpCode::mov: - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; case AVR::OpCode::lsl: - instructions.emplace_back(mos6502::OpCode::asl, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::asl, personality.get_register(o1_reg_num)); return; case AVR::OpCode::rol: - instructions.emplace_back(mos6502::OpCode::rol, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::rol, personality.get_register(o1_reg_num)); return; case AVR::OpCode::rcall: instructions.emplace_back(mos6502::OpCode::jsr, o1); return; case AVR::OpCode::ld: { if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { - indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); + indirect_load(instructions, personality.get_register(o2.value[0]).value, personality.get_register(o1_reg_num).value); return; } if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") { - indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1_reg_num).value); - increment_16_bit(instructions, AVR::get_register_number(o2.value[0])); + indirect_load(instructions, personality.get_register(o2.value[0]).value, personality.get_register(o1_reg_num).value); + increment_16_bit(personality, instructions, AVR::get_register_number(o2.value[0])); return; } throw std::runtime_error("Unhandled ld to non-Z"); @@ -707,9 +692,9 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode case AVR::OpCode::sbci: { // we want to utilize the carry flag, however it was set previously // (it's really a borrow flag on the 6502) - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); fixup_16_bit_N_Z_flags(instructions); return; } @@ -718,19 +703,19 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode // if |x| < |y| -> x-y +carry // for these special cases with -(1) and -(-(1)) if (o2.value == "lo8(-(-1))") { - instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::dec, personality.get_register(o1_reg_num)); return; } if (o2.value == "lo8(-(1))") { - instructions.emplace_back(mos6502::OpCode::inc, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::inc, personality.get_register(o1_reg_num)); return; } - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); // have to set carry flag, since it gets inverted by sbc instructions.emplace_back(mos6502::OpCode::sec); instructions.emplace_back(mos6502::OpCode::sbc, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); // temporarily store lower order (not carried substraction) byte into Y for checking // later if this is a two byte subtraction operation instructions.emplace_back(mos6502::OpCode::tax); @@ -738,40 +723,40 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::st: { if (o1.value == "Z" || o1.value == "Y" || o1.value == "X") { - indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); + indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(o1.value[0]).value); return; } if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") { - indirect_store(instructions, AVR::get_register(o2_reg_num).value, AVR::get_register(o1.value[0]).value); - increment_16_bit(instructions, AVR::get_register_number(o1.value[0])); + indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(o1.value[0]).value); + increment_16_bit(personality, instructions, AVR::get_register_number(o1.value[0])); return; } throw std::runtime_error("Unhandled st"); } case AVR::OpCode::lds: { instructions.emplace_back(mos6502::OpCode::lda, o2); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::lsr: { - instructions.emplace_back(mos6502::OpCode::lsr, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lsr, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::andi: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::AND, Operand(o2.type, fixup_8bit_literal(o2.value))); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::eor: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::eor, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::eor, personality.get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::cpse: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, personality.get_register(o2_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); instructions.emplace_back(ASMLine::Type::Directive, new_label_name); @@ -779,7 +764,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::sbrc: { instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, personality.get_register(o1_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); instructions.emplace_back(ASMLine::Type::Directive, new_label_name); @@ -787,7 +772,7 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::sbrs: { instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); - instructions.emplace_back(mos6502::OpCode::bit, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::bit, personality.get_register(o1_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); instructions.emplace_back(ASMLine::Type::Directive, new_label_name); @@ -808,36 +793,36 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode } case AVR::OpCode::sbiw: { - subtract_16_bit(instructions, o1_reg_num, static_cast(std::stoi(o2.value))); + subtract_16_bit(personality, instructions, o1_reg_num, static_cast(std::stoi(o2.value))); return; } case AVR::OpCode::push: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::pha); return; } case AVR::OpCode::pop: { instructions.emplace_back(mos6502::OpCode::pla); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::com: { // We're doing this in the same way the AVR does it, to make sure the C flag is set properly instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$FF")); - instructions.emplace_back(mos6502::OpCode::sbc, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::clr: { instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::cpi: { // note that this will leave the C flag in the 6502 borrow state, not normal carry state - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::cmp, Operand(o2.type, fixup_8bit_literal(o2.value))); return; } @@ -863,28 +848,28 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode // ADC #$80 // ROL A - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); instructions.emplace_back(mos6502::OpCode::asl); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); instructions.emplace_back(mos6502::OpCode::rol); instructions.emplace_back(mos6502::OpCode::asl); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#$80")); instructions.emplace_back(mos6502::OpCode::rol); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::add: { instructions.emplace_back(mos6502::OpCode::clc); - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::adc, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::adc, personality.get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::adc: { - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::adc, AVR::get_register(o2_reg_num)); - instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::adc, personality.get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } case AVR::OpCode::cpc: { @@ -893,8 +878,8 @@ void translate_instruction(std::vector &instructions, const AVR::OpCode // the carry flag here, and assume that it's set how the 6502 wants it to be // set from the previous operation - instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sbc, AVR::get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o2_reg_num)); return; } case AVR::OpCode::brsh: { @@ -949,7 +934,7 @@ void log(LogLevel ll, const std::size_t line_no, const std::string &line, const std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; } -void to_mos6502(const AVR &from_instruction, std::vector &instructions) +void to_mos6502(const Personality &personality, const AVR &from_instruction, std::vector &instructions) { try { switch (from_instruction.type) { @@ -991,7 +976,7 @@ void to_mos6502(const AVR &from_instruction, std::vector &instructions) const auto head = instructions.size(); try { - translate_instruction(instructions, from_instruction.opcode, from_instruction.operand1, from_instruction.operand2); + translate_instruction(personality, instructions, from_instruction.opcode, from_instruction.operand1, from_instruction.operand2); } catch (const std::exception &e) { instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + from_instruction.text + "' " + e.what()); log(LogLevel::Error, from_instruction, e.what()); @@ -1224,7 +1209,7 @@ bool fix_overwritten_flags(std::vector &instructions) return false; } -void run(std::istream &input) +void run(const Personality &personality, std::istream &input) { std::regex Comment(R"(\s*\#.*)"); std::regex Label(R"(^\s*(\S+):.*)"); @@ -1278,7 +1263,7 @@ void run(std::istream &input) for (const auto &i : instructions) { if (i.type == ASMLine::Type::Instruction) { - const auto check_label = [&](const auto &value) { + const auto check_label = [&](const std::string &value) { if (labels.count(value) != 0) { used_labels.insert(value); } @@ -1286,8 +1271,8 @@ void run(std::istream &input) check_label(i.operand1.value); check_label(i.operand2.value); - check_label(strip_lo_hi(i.operand1.value)); - check_label(strip_lo_hi(i.operand2.value)); + check_label(std::string{ strip_lo_hi(i.operand1.value) }); + check_label(std::string{ strip_lo_hi(i.operand2.value) }); } } @@ -1321,7 +1306,7 @@ void run(std::istream &input) if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8(")) { const auto potential_label = strip_lo_hi(i.operand2.value); - const auto itr1 = new_labels.find(potential_label); + const auto itr1 = new_labels.find(std::string{ potential_label }); if (itr1 != new_labels.end()) { i.operand2.value.replace(4, potential_label.size(), itr1->second); } @@ -1343,18 +1328,17 @@ void run(std::istream &input) std::vector new_instructions; new_instructions.emplace_back(ASMLine::Type::Directive, ".word " + std::to_string(start_address)); new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address)); - new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC"); - new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); - // set __zero_reg__ (reg 1 on AVR) to 0 + personality.insert_autostart_sequence(new_instructions); + // set __zero_reg__ (reg 1 on AVR) to 0 new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); - new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1)); + new_instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(1)); new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); int instructions_to_skip = 0; std::string next_label_name; for (const auto &i : instructions) { - to_mos6502(i, new_instructions); + to_mos6502(personality, i, new_instructions); // intentionally copy so we don't invalidate the reference const auto last_instruction = new_instructions.back(); @@ -1397,7 +1381,7 @@ void run(std::istream &input) } } -int main([[maybe_unused]] const int argc, const char *argv[]) +int main(const int argc, const char **argv) { std::ifstream input_file; @@ -1410,6 +1394,8 @@ int main([[maybe_unused]] const int argc, const char *argv[]) } }(); + C64 personality; + std::cout << "; AVR Mode\n"; - run(input); + run(personality, input); } diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index 4cec0fe..c097665 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -12,6 +12,7 @@ target_link_libraries( 6502-c++ PRIVATE project_options project_warnings + CONAN_PKG::ctre CONAN_PKG::docopt.cpp CONAN_PKG::fmt CONAN_PKG::spdlog) From e6040763ebc56a56f0f2eaeb20431e82d93c6b63 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Thu, 6 May 2021 23:11:12 -0600 Subject: [PATCH 20/27] Some code organization and splitting up --- .clang-tidy | 2 +- include/6502.hpp | 240 ++++++++++++++++ include/assembly.hpp | 51 ++++ include/optimizer.hpp | 142 +++++++++ include/personalities/c64.hpp | 93 ++++++ include/personality.hpp | 23 ++ src/6502-c++.cpp | 527 +--------------------------------- src/CMakeLists.txt | 2 +- 8 files changed, 558 insertions(+), 522 deletions(-) create mode 100644 include/6502.hpp create mode 100644 include/assembly.hpp create mode 100644 include/optimizer.hpp create mode 100644 include/personalities/c64.hpp create mode 100644 include/personality.hpp diff --git a/.clang-tidy b/.clang-tidy index 4db910d..cc98825 100644 --- a/.clang-tidy +++ b/.clang-tidy @@ -1,6 +1,6 @@ --- Checks: '*,-fuchsia-*,-google-*,-zircon-*,-abseil-*,-modernize-use-trailing-return-type,-llvm*,-altera*,-misc-non-private-member-variables-in-classes,-readability-else-after-return' -WarningsAsErrors: '*' +WarningsAsErrors: '' HeaderFilterRegex: '' FormatStyle: none diff --git a/include/6502.hpp b/include/6502.hpp new file mode 100644 index 0000000..e14cfdb --- /dev/null +++ b/include/6502.hpp @@ -0,0 +1,240 @@ +#ifndef INC_6502_CPP_6502_HPP +#define INC_6502_CPP_6502_HPP + +#include "assembly.hpp" + +struct mos6502 : ASMLine +{ + enum class OpCode { + unknown, + + adc, + AND, + asl, + + bcc, + bcs, + beq, + bit, + bmi, + bne, + bpl, + + cpy, + cmp, + clc, + + dec, + + eor, + + inc, + + jmp, + jsr, + + lda, + ldy, + lsr, + + ORA, + + pha, + php, + pla, + plp, + + rol, + ror, + rts, + + sbc, + sec, + sta, + sty, + + tax, + tay, + txa, + tya, + }; + + static bool get_is_branch(const OpCode o) + { + switch (o) { + case OpCode::beq: + case OpCode::bne: + case OpCode::bmi: + case OpCode::bpl: + case OpCode::bcc: + case OpCode::bcs: + return true; + case OpCode::adc: + case OpCode::AND: + case OpCode::asl: + case OpCode::bit: + case OpCode::cpy: + case OpCode::cmp: + case OpCode::clc: + case OpCode::dec: + case OpCode::eor: + case OpCode::inc: + case OpCode::jmp: + case OpCode::jsr: + case OpCode::lda: + case OpCode::ldy: + case OpCode::lsr: + case OpCode::ORA: + case OpCode::pha: + case OpCode::php: + case OpCode::pla: + case OpCode::plp: + case OpCode::rol: + case OpCode::ror: + case OpCode::rts: + case OpCode::sbc: + case OpCode::sec: + case OpCode::sta: + case OpCode::sty: + case OpCode::tax: + case OpCode::tay: + case OpCode::txa: + case OpCode::tya: + + case OpCode::unknown: + break; + } + return false; + } + + static bool get_is_comparison(const OpCode o) + { + switch (o) { + case OpCode::bit: + case OpCode::cmp: + case OpCode::cpy: + return true; + case OpCode::adc: + case OpCode::AND: + case OpCode::asl: + case OpCode::beq: + case OpCode::bne: + case OpCode::bmi: + case OpCode::bpl: + case OpCode::bcc: + case OpCode::bcs: + case OpCode::clc: + case OpCode::dec: + case OpCode::eor: + case OpCode::inc: + case OpCode::jmp: + case OpCode::jsr: + case OpCode::lda: + case OpCode::ldy: + case OpCode::lsr: + case OpCode::ORA: + case OpCode::pha: + case OpCode::php: + case OpCode::pla: + case OpCode::plp: + case OpCode::rol: + case OpCode::ror: + case OpCode::rts: + case OpCode::sbc: + case OpCode::sec: + case OpCode::sta: + case OpCode::sty: + case OpCode::tax: + case OpCode::tay: + case OpCode::txa: + case OpCode::tya: + case OpCode::unknown: + break; + } + return false; + } + + + explicit mos6502(const OpCode o) + : ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) + { + } + + mos6502(const Type t, std::string s) + : ASMLine(t, std::move(s)) + { + } + + mos6502(const OpCode o, Operand t_o) + : ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), op(std::move(t_o)), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) + { + } + + constexpr static std::string_view to_string(const OpCode o) + { + switch (o) { + case OpCode::lda: return "lda"; + case OpCode::asl: return "asl"; + case OpCode::rol: return "rol"; + case OpCode::ldy: return "ldy"; + case OpCode::tay: return "tay"; + case OpCode::tya: return "tya"; + case OpCode::tax: return "tax"; + case OpCode::txa: return "txa"; + case OpCode::cpy: return "cpy"; + case OpCode::eor: return "eor"; + case OpCode::sta: return "sta"; + case OpCode::sty: return "sty"; + case OpCode::pha: return "pha"; + case OpCode::pla: return "pla"; + case OpCode::php: return "php"; + case OpCode::plp: return "plp"; + case OpCode::lsr: return "lsr"; + case OpCode::ror: return "ror"; + case OpCode::AND: return "and"; + case OpCode::inc: return "inc"; + case OpCode::dec: return "dec"; + case OpCode::ORA: return "ora"; + case OpCode::cmp: return "cmp"; + case OpCode::bne: return "bne"; + case OpCode::bmi: return "bmi"; + case OpCode::beq: return "beq"; + case OpCode::jmp: return "jmp"; + case OpCode::adc: return "adc"; + case OpCode::sbc: return "sbc"; + case OpCode::rts: return "rts"; + case OpCode::clc: return "clc"; + case OpCode::sec: return "sec"; + case OpCode::bit: return "bit"; + case OpCode::jsr: return "jsr"; + case OpCode::bpl: return "bpl"; + case OpCode::bcc: return "bcc"; + case OpCode::bcs: return "bcs"; + case OpCode::unknown: return ""; + } + + return ""; + } + + [[nodiscard]] std::string to_string() const + { + switch (type) { + case ASMLine::Type::Label: + return text;// + ':'; + case ASMLine::Type::Directive: + case ASMLine::Type::Instruction: { + return fmt::format("\t{} {:15}; {}", text, op.value, comment); + } + } + throw std::runtime_error("Unable to render: " + text); + } + + + OpCode opcode = OpCode::unknown; + Operand op; + std::string comment; + bool is_branch = false; + bool is_comparison = false; +}; + +#endif//INC_6502_CPP_6502_HPP diff --git a/include/assembly.hpp b/include/assembly.hpp new file mode 100644 index 0000000..3a5a107 --- /dev/null +++ b/include/assembly.hpp @@ -0,0 +1,51 @@ +#ifndef INC_6502_CPP_ASSEMBLY_HPP +#define INC_6502_CPP_ASSEMBLY_HPP + +struct Operand +{ + enum class Type { + empty, + literal, + reg /*ister*/ + }; + + Type type = Type::empty; + int reg_num = 0; + std::string value; + + Operand() = default; + + bool operator==(const Operand &other) const + { + return type == other.type && reg_num == other.reg_num && value == other.value; + } + + Operand(const Type t, std::string v) + : type(t), value(std::move(v)) + { + assert(type == Type::literal); + } + + Operand(const Type t, const int num) + : type(t), reg_num(num) + { + assert(type == Type::reg); + } +}; + + +struct ASMLine +{ + enum class Type { + Label, + Instruction, + Directive + }; + + ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {} + + Type type; + std::string text; +}; + +#endif//INC_6502_CPP_ASSEMBLY_HPP diff --git a/include/optimizer.hpp b/include/optimizer.hpp new file mode 100644 index 0000000..dd442de --- /dev/null +++ b/include/optimizer.hpp @@ -0,0 +1,142 @@ +#ifndef INC_6502_CPP_OPTIMIZER_HPP +#define INC_6502_CPP_OPTIMIZER_HPP + +#include "6502.hpp" +#include + +bool optimize(std::vector &instructions) +{ + if (instructions.size() < 2) { + return false; + } + + const auto next_instruction = [&instructions](auto i) { + do { + ++i; + } while (i < instructions.size() && instructions[i].type == ASMLine::Type::Directive); + return i; + }; + + + // remove unused flag-fix-up blocks + // it might make sense in the future to only insert these if determined they are needed? + for (size_t op = 10; op < instructions.size(); ++op) { + if (instructions[op].opcode == mos6502::OpCode::lda) { + if (instructions[op - 1].text == "; END remove if next is lda") { + for (size_t inner_op = op - 1; inner_op > 1; --inner_op) { + instructions[inner_op] = mos6502(ASMLine::Type::Directive, + "; removed unused flag fix-up: " + instructions[inner_op].to_string()); + + if (instructions[inner_op].text.find("; BEGIN") != std::string::npos) { + return true; + } + } + } + } + } + + + // look for redundant load of lda after a tax + for (size_t op = 0; op < instructions.size() - 3; ++op) { + if (instructions[op].opcode == mos6502::OpCode::sta + && instructions[op + 1].opcode == mos6502::OpCode::tax + && instructions[op + 2].opcode == mos6502::OpCode::lda + && instructions[op].op.value == instructions[op + 2].op.value) { + instructions[op + 2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string()); + return true; + } + } + + // look for redundant stores to 0-page registers with sta + for (size_t op = 0; op < instructions.size(); ++op) { + // todo, make sure this is in the register map + if (instructions[op].opcode == mos6502::OpCode::sta + && instructions[op].op.value.size() == 3) { + for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) { + if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) { + // we just found a use of ourselves back, abort the search, there's probably something else going on + break; + } + if (instructions[next_op].opcode == mos6502::OpCode::lda && instructions[next_op].op.value != instructions[op].op.value) { + // someone just loaded lda with a different value, so we need to abort! + break; + } + + // abort at label + if (instructions[next_op].type == ASMLine::Type::Label) { + break; + } + + if (instructions[next_op].opcode == mos6502::OpCode::sta + && instructions[next_op].op.value == instructions[op].op.value) { + // looks like we found a redundant store, remove the first one + instructions[op] = mos6502(ASMLine::Type::Directive, + "; removed redundant sta: " + instructions[op].to_string()); + return true; + } + } + } + } + + for (size_t op = 0; op < instructions.size() - 1; ++op) { + // look for a transfer of Y -> A immediately followed by A -> Y + if (instructions[op].opcode == mos6502::OpCode::tya) { + next_instruction(op); + if (instructions[op].opcode == mos6502::OpCode::tay) { + instructions[op] = mos6502(ASMLine::Type::Directive, + "; removed redundant tay: " + instructions[op].to_string()); + return true; + } + } + } + + for (size_t op = 0; op < instructions.size() - 1; ++op) { + // look for a store A -> loc immediately followed by loc -> A + if (instructions[op].opcode == mos6502::OpCode::sta) { + const auto next = next_instruction(op); + if (instructions[next].opcode == mos6502::OpCode::lda + && instructions[next].op == instructions[op].op) { + instructions[next] = mos6502(ASMLine::Type::Directive, + "; removed redundant lda: " + instructions[next].to_string()); + return true; + } + } + } + + for (size_t op = 0; op < instructions.size() - 1; ++op) { + if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) { + auto op2 = op + 1; + + while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)) { + // while inside this label + if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == instructions[op].op.value) { + instructions[op2] = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string()); + return true; + } + ++op2; + } + } + } + + for (size_t op = 0; op < instructions.size() - 1; ++op) { + if (instructions[op].opcode == mos6502::OpCode::lda + && instructions[op].op.type == Operand::Type::literal) { + const auto operand = instructions[op].op; + auto op2 = op + 1; + // look for multiple stores of the same value + while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) { + ++op2; + } + if (instructions[op2].opcode == mos6502::OpCode::lda + && operand == instructions[op2].op) { + instructions[op2] = mos6502(ASMLine::Type::Directive, + "; removed redundant lda: " + instructions[op2].to_string()); + return true; + } + } + } + + return false; +} + +#endif//INC_6502_CPP_OPTIMIZER_HPP diff --git a/include/personalities/c64.hpp b/include/personalities/c64.hpp new file mode 100644 index 0000000..28080ac --- /dev/null +++ b/include/personalities/c64.hpp @@ -0,0 +1,93 @@ +#ifndef INC_6502_C_C64_HPP +#define INC_6502_C_C64_HPP + +#include "../personality.hpp" + +struct C64 : Personality +{ + + void insert_autostart_sequence(std::vector &new_instructions) const override + { + constexpr static auto start_address = 0x0801; + + // first 2 bytes is the load address for a PRG file. + new_instructions.emplace_back(ASMLine::Type::Directive, ".word " + std::to_string(start_address)); + new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address)); + new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC"); + new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); + } + + [[nodiscard]] Operand get_register(const int reg_num) const override + { + switch (reg_num) { + // http://sta.c64.org/cbm64mem.html + case 0: + return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232 + case 1: + return Operand(Operand::Type::literal, "$a8");// counter for rs232 + case 2: + return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer + case 3: + return Operand(Operand::Type::literal, "$06"); + case 4: + return Operand(Operand::Type::literal, "$fb");// unused + case 5: + return Operand(Operand::Type::literal, "$fc");// unused + case 6: + return Operand(Operand::Type::literal, "$fd");// unused + case 7: + return Operand(Operand::Type::literal, "$fe");// unused + case 8: + return Operand(Operand::Type::literal, "$22");// unused + case 9: + return Operand(Operand::Type::literal, "$23");// unused + case 10: + return Operand(Operand::Type::literal, "$39");// Current BASIC line number + case 11: + return Operand(Operand::Type::literal, "$3a");// Current BASIC line number + case 12: + return Operand(Operand::Type::literal, "$61");// arithmetic register #1 + case 13: + return Operand(Operand::Type::literal, "$62"); + case 14: + return Operand(Operand::Type::literal, "$63"); + case 15: + return Operand(Operand::Type::literal, "$64"); + case 16: + return Operand(Operand::Type::literal, "$65"); + case 17: + return Operand(Operand::Type::literal, "$69");// arithmetic register #2 + case 18: + return Operand(Operand::Type::literal, "$6a"); + case 19: + return Operand(Operand::Type::literal, "$6b"); + case 20: + return Operand(Operand::Type::literal, "$6c"); + case 21: + return Operand(Operand::Type::literal, "$6d"); + case 22: + return Operand(Operand::Type::literal, "$57");// arithmetic register #3 + case 23: + return Operand(Operand::Type::literal, "$58"); + case 24: + return Operand(Operand::Type::literal, "$59"); + case 25: + return Operand(Operand::Type::literal, "$5a"); + case 26: + return Operand(Operand::Type::literal, "$5b"); + case 27: + return Operand(Operand::Type::literal, "$5c");// arithmetic register #4 + case 28: + return Operand(Operand::Type::literal, "$5d"); + case 29: + return Operand(Operand::Type::literal, "$5e"); + case 30: + return Operand(Operand::Type::literal, "$5f"); + case 31: + return Operand(Operand::Type::literal, "$60"); + } + throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); + } +}; + +#endif//INC_6502_C_C64_HPP diff --git a/include/personality.hpp b/include/personality.hpp new file mode 100644 index 0000000..b684002 --- /dev/null +++ b/include/personality.hpp @@ -0,0 +1,23 @@ +#ifndef INC_6502_CPP_PERSONALITY_HPP +#define INC_6502_CPP_PERSONALITY_HPP + +#include +#include "6502.hpp" + +class Personality +{ +public: + virtual void insert_autostart_sequence(std::vector &new_instructions) const = 0; + [[nodiscard]] virtual Operand get_register(const int reg_num) const = 0; + + virtual ~Personality() = default; + Personality(const Personality &) = delete; + Personality(Personality &&) = delete; + Personality &operator=(const Personality &) = delete; + Personality &operator=(Personality &&) = delete; + +protected: + Personality() = default; +}; + +#endif//INC_6502_CPP_PERSONALITY_HPP diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 28a64b4..739aba4 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -10,151 +10,10 @@ #include #include -struct Operand -{ - enum class Type { - empty, - literal, - reg /*ister*/ - }; - - Type type = Type::empty; - int reg_num = 0; - std::string value; - - Operand() = default; - - bool operator==(const Operand &other) const - { - return type == other.type && reg_num == other.reg_num && value == other.value; - } - - Operand(const Type t, std::string v) - : type(t), value(std::move(v)) - { - assert(type == Type::literal); - } - - Operand(const Type t, const int num) - : type(t), reg_num(num) - { - assert(type == Type::reg); - } -}; - -struct mos6502; - -class Personality -{ -public: - virtual void insert_autostart_sequence(std::vector &new_instructions) const = 0; - [[nodiscard]] virtual Operand get_register(const int reg_num) const = 0; - - virtual ~Personality() = default; - Personality(const Personality &) = delete; - Personality(Personality &&) = delete; - Personality &operator=(const Personality &) = delete; - Personality &operator=(Personality &&) = delete; - -protected: - Personality() = default; -}; - -struct ASMLine -{ - enum class Type { - Label, - Instruction, - Directive - }; - - ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {} - - Type type; - std::string text; -}; - -struct C64 : Personality -{ - - void insert_autostart_sequence(std::vector &new_instructions) const override { - new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC"); - new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); - } - - [[nodiscard]] Operand get_register(const int reg_num) const override - { - switch (reg_num) { - // http://sta.c64.org/cbm64mem.html - case 0: - return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232 - case 1: - return Operand(Operand::Type::literal, "$a8");// counter for rs232 - case 2: - return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer - case 3: - return Operand(Operand::Type::literal, "$06"); - case 4: - return Operand(Operand::Type::literal, "$fb");// unused - case 5: - return Operand(Operand::Type::literal, "$fc");// unused - case 6: - return Operand(Operand::Type::literal, "$fd");// unused - case 7: - return Operand(Operand::Type::literal, "$fe");// unused - case 8: - return Operand(Operand::Type::literal, "$22");// unused - case 9: - return Operand(Operand::Type::literal, "$23");// unused - case 10: - return Operand(Operand::Type::literal, "$39");// Current BASIC line number - case 11: - return Operand(Operand::Type::literal, "$3a");// Current BASIC line number - case 12: - return Operand(Operand::Type::literal, "$61");// arithmetic register #1 - case 13: - return Operand(Operand::Type::literal, "$62"); - case 14: - return Operand(Operand::Type::literal, "$63"); - case 15: - return Operand(Operand::Type::literal, "$64"); - case 16: - return Operand(Operand::Type::literal, "$65"); - case 17: - return Operand(Operand::Type::literal, "$69");// arithmetic register #2 - case 18: - return Operand(Operand::Type::literal, "$6a"); - case 19: - return Operand(Operand::Type::literal, "$6b"); - case 20: - return Operand(Operand::Type::literal, "$6c"); - case 21: - return Operand(Operand::Type::literal, "$6d"); - case 22: - return Operand(Operand::Type::literal, "$57");// arithmetic register #3 - case 23: - return Operand(Operand::Type::literal, "$58"); - case 24: - return Operand(Operand::Type::literal, "$59"); - case 25: - return Operand(Operand::Type::literal, "$5a"); - case 26: - return Operand(Operand::Type::literal, "$5b"); - case 27: - return Operand(Operand::Type::literal, "$5c");// arithmetic register #4 - case 28: - return Operand(Operand::Type::literal, "$5d"); - case 29: - return Operand(Operand::Type::literal, "$5e"); - case 30: - return Operand(Operand::Type::literal, "$5f"); - case 31: - return Operand(Operand::Type::literal, "$60"); - } - throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); - } -}; - +#include "../include/assembly.hpp" +#include "../include/6502.hpp" +#include "../include/optimizer.hpp" +#include "../include/personalities/c64.hpp" int parse_8bit_literal(const std::string &s) { @@ -200,240 +59,6 @@ std::string fixup_8bit_literal(const std::string &s) } -struct mos6502 : ASMLine -{ - enum class OpCode { - unknown, - - adc, - AND, - asl, - - bcc, - bcs, - beq, - bit, - bmi, - bne, - bpl, - - cpy, - cmp, - clc, - - dec, - - eor, - - inc, - - jmp, - jsr, - - lda, - ldy, - lsr, - - ORA, - - pha, - php, - pla, - plp, - - rol, - ror, - rts, - - sbc, - sec, - sta, - sty, - - tax, - tay, - txa, - tya, - }; - - static bool get_is_branch(const OpCode o) - { - switch (o) { - case OpCode::beq: - case OpCode::bne: - case OpCode::bmi: - case OpCode::bpl: - case OpCode::bcc: - case OpCode::bcs: - return true; - case OpCode::adc: - case OpCode::AND: - case OpCode::asl: - case OpCode::bit: - case OpCode::cpy: - case OpCode::cmp: - case OpCode::clc: - case OpCode::dec: - case OpCode::eor: - case OpCode::inc: - case OpCode::jmp: - case OpCode::jsr: - case OpCode::lda: - case OpCode::ldy: - case OpCode::lsr: - case OpCode::ORA: - case OpCode::pha: - case OpCode::php: - case OpCode::pla: - case OpCode::plp: - case OpCode::rol: - case OpCode::ror: - case OpCode::rts: - case OpCode::sbc: - case OpCode::sec: - case OpCode::sta: - case OpCode::sty: - case OpCode::tax: - case OpCode::tay: - case OpCode::txa: - case OpCode::tya: - - case OpCode::unknown: - break; - } - return false; - } - - static bool get_is_comparison(const OpCode o) - { - switch (o) { - case OpCode::bit: - case OpCode::cmp: - case OpCode::cpy: - return true; - case OpCode::adc: - case OpCode::AND: - case OpCode::asl: - case OpCode::beq: - case OpCode::bne: - case OpCode::bmi: - case OpCode::bpl: - case OpCode::bcc: - case OpCode::bcs: - case OpCode::clc: - case OpCode::dec: - case OpCode::eor: - case OpCode::inc: - case OpCode::jmp: - case OpCode::jsr: - case OpCode::lda: - case OpCode::ldy: - case OpCode::lsr: - case OpCode::ORA: - case OpCode::pha: - case OpCode::php: - case OpCode::pla: - case OpCode::plp: - case OpCode::rol: - case OpCode::ror: - case OpCode::rts: - case OpCode::sbc: - case OpCode::sec: - case OpCode::sta: - case OpCode::sty: - case OpCode::tax: - case OpCode::tay: - case OpCode::txa: - case OpCode::tya: - case OpCode::unknown: - break; - } - return false; - } - - - explicit mos6502(const OpCode o) - : ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) - { - } - - mos6502(const Type t, std::string s) - : ASMLine(t, std::move(s)) - { - } - - mos6502(const OpCode o, Operand t_o) - : ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), op(std::move(t_o)), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o)) - { - } - - constexpr static std::string_view to_string(const OpCode o) - { - switch (o) { - case OpCode::lda: return "lda"; - case OpCode::asl: return "asl"; - case OpCode::rol: return "rol"; - case OpCode::ldy: return "ldy"; - case OpCode::tay: return "tay"; - case OpCode::tya: return "tya"; - case OpCode::tax: return "tax"; - case OpCode::txa: return "txa"; - case OpCode::cpy: return "cpy"; - case OpCode::eor: return "eor"; - case OpCode::sta: return "sta"; - case OpCode::sty: return "sty"; - case OpCode::pha: return "pha"; - case OpCode::pla: return "pla"; - case OpCode::php: return "php"; - case OpCode::plp: return "plp"; - case OpCode::lsr: return "lsr"; - case OpCode::ror: return "ror"; - case OpCode::AND: return "and"; - case OpCode::inc: return "inc"; - case OpCode::dec: return "dec"; - case OpCode::ORA: return "ora"; - case OpCode::cmp: return "cmp"; - case OpCode::bne: return "bne"; - case OpCode::bmi: return "bmi"; - case OpCode::beq: return "beq"; - case OpCode::jmp: return "jmp"; - case OpCode::adc: return "adc"; - case OpCode::sbc: return "sbc"; - case OpCode::rts: return "rts"; - case OpCode::clc: return "clc"; - case OpCode::sec: return "sec"; - case OpCode::bit: return "bit"; - case OpCode::jsr: return "jsr"; - case OpCode::bpl: return "bpl"; - case OpCode::bcc: return "bcc"; - case OpCode::bcs: return "bcs"; - case OpCode::unknown: return ""; - } - - return ""; - } - - [[nodiscard]] std::string to_string() const - { - switch (type) { - case ASMLine::Type::Label: - return text;// + ':'; - case ASMLine::Type::Directive: - case ASMLine::Type::Instruction: { - return fmt::format("\t{} {:15}; {}", text, op.value, comment); - } - } - throw std::runtime_error("Unable to render: " + text); - } - - - OpCode opcode = OpCode::unknown; - Operand op; - std::string comment; - bool is_branch = false; - bool is_comparison = false; -}; - struct AVR : ASMLine { @@ -872,6 +497,7 @@ void translate_instruction(const Personality &personality, std::vector instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } + case AVR::OpCode::cpc: { // this instruction seems to need to be used in the case after a sbc operation, where the // carry flag is set to the appropriate borrow state, so I'm going to not invert @@ -882,6 +508,7 @@ void translate_instruction(const Personality &personality, std::vector instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o2_reg_num)); return; } + case AVR::OpCode::brsh: { if (o1.value == ".+2") { // assumes 6502 'borrow' for Carry flag instead of carry, so bcs instead of bcc @@ -996,140 +623,6 @@ void to_mos6502(const Personality &personality, const AVR &from_instruction, std } } -bool optimize(std::vector &instructions) -{ - if (instructions.size() < 2) { - return false; - } - - const auto next_instruction = [&instructions](auto i) { - do { - ++i; - } while (i < instructions.size() && instructions[i].type == ASMLine::Type::Directive); - return i; - }; - - - // remove unused flag-fix-up blocks - // it might make sense in the future to only insert these if determined they are needed? - for (size_t op = 10; op < instructions.size(); ++op) { - if (instructions[op].opcode == mos6502::OpCode::lda) { - if (instructions[op - 1].text == "; END remove if next is lda") { - for (size_t inner_op = op - 1; inner_op > 1; --inner_op) { - instructions[inner_op] = mos6502(ASMLine::Type::Directive, - "; removed unused flag fix-up: " + instructions[inner_op].to_string()); - - if (instructions[inner_op].text.find("; BEGIN") != std::string::npos) { - return true; - } - } - } - } - } - - - // look for redundant load of lda after a tax - for (size_t op = 0; op < instructions.size() - 3; ++op) { - if (instructions[op].opcode == mos6502::OpCode::sta - && instructions[op + 1].opcode == mos6502::OpCode::tax - && instructions[op + 2].opcode == mos6502::OpCode::lda - && instructions[op].op.value == instructions[op + 2].op.value) { - instructions[op + 2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string()); - return true; - } - } - - // look for redundant stores to 0-page registers with sta - for (size_t op = 0; op < instructions.size(); ++op) { - // todo, make sure this is in the register map - if (instructions[op].opcode == mos6502::OpCode::sta - && instructions[op].op.value.size() == 3) { - for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) { - if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) { - // we just found a use of ourselves back, abort the search, there's probably something else going on - break; - } - if (instructions[next_op].opcode == mos6502::OpCode::lda && instructions[next_op].op.value != instructions[op].op.value) { - // someone just loaded lda with a different value, so we need to abort! - break; - } - - // abort at label - if (instructions[next_op].type == ASMLine::Type::Label) { - break; - } - - if (instructions[next_op].opcode == mos6502::OpCode::sta - && instructions[next_op].op.value == instructions[op].op.value) { - // looks like we found a redundant store, remove the first one - instructions[op] = mos6502(ASMLine::Type::Directive, - "; removed redundant sta: " + instructions[op].to_string()); - return true; - } - } - } - } - - for (size_t op = 0; op < instructions.size() - 1; ++op) { - // look for a transfer of Y -> A immediately followed by A -> Y - if (instructions[op].opcode == mos6502::OpCode::tya) { - next_instruction(op); - if (instructions[op].opcode == mos6502::OpCode::tay) { - instructions[op] = mos6502(ASMLine::Type::Directive, - "; removed redundant tay: " + instructions[op].to_string()); - return true; - } - } - } - - for (size_t op = 0; op < instructions.size() - 1; ++op) { - // look for a store A -> loc immediately followed by loc -> A - if (instructions[op].opcode == mos6502::OpCode::sta) { - const auto next = next_instruction(op); - if (instructions[next].opcode == mos6502::OpCode::lda - && instructions[next].op == instructions[op].op) { - instructions[next] = mos6502(ASMLine::Type::Directive, - "; removed redundant lda: " + instructions[next].to_string()); - return true; - } - } - } - - for (size_t op = 0; op < instructions.size() - 1; ++op) { - if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) { - auto op2 = op + 1; - - while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)) { - // while inside this label - if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == instructions[op].op.value) { - instructions[op2] = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string()); - return true; - } - ++op2; - } - } - } - - for (size_t op = 0; op < instructions.size() - 1; ++op) { - if (instructions[op].opcode == mos6502::OpCode::lda - && instructions[op].op.type == Operand::Type::literal) { - const auto operand = instructions[op].op; - auto op2 = op + 1; - // look for multiple stores of the same value - while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) { - ++op2; - } - if (instructions[op2].opcode == mos6502::OpCode::lda - && operand == instructions[op2].op) { - instructions[op2] = mos6502(ASMLine::Type::Directive, - "; removed redundant lda: " + instructions[op2].to_string()); - return true; - } - } - } - - return false; -} bool fix_long_branches(std::vector &instructions, int &branch_patch_count) { @@ -1290,13 +783,9 @@ void run(const Personality &personality, std::istream &input) }(); - for (const auto &l : new_labels) { - std::clog << "Label: '" << l.first << "': '" << l.second << "'\n"; - } for (auto &i : instructions) { if (i.type == ASMLine::Type::Label) { - std::clog << "Looking up Label: '" << i.text << "'\n"; if (i.text == "0") { i.text = "-memcpy_0"; } else { @@ -1323,11 +812,9 @@ void run(const Personality &personality, std::istream &input) } } - constexpr static auto start_address = 0x0801; std::vector new_instructions; - new_instructions.emplace_back(ASMLine::Type::Directive, ".word " + std::to_string(start_address)); - new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address)); + personality.insert_autostart_sequence(new_instructions); // set __zero_reg__ (reg 1 on AVR) to 0 new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); diff --git a/src/CMakeLists.txt b/src/CMakeLists.txt index c097665..c0103c0 100644 --- a/src/CMakeLists.txt +++ b/src/CMakeLists.txt @@ -7,7 +7,7 @@ if(CPP_STARTER_USE_SDL) endif() # Generic test that uses conan libs -add_executable(6502-c++ 6502-c++.cpp) +add_executable(6502-c++ 6502-c++.cpp ../include/optimizer.hpp ../include/assembly.hpp ../include/6502.hpp ../include/personality.hpp ../include/personalities/c64.hpp) target_link_libraries( 6502-c++ PRIVATE project_options From f79a189a128f9c9d52b9b8b1af838fc732140e16 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sat, 8 May 2021 16:01:25 -0600 Subject: [PATCH 21/27] Fix lookup of X,Y,Z registers --- src/6502-c++.cpp | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 739aba4..c0f4672 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -304,11 +304,11 @@ void translate_instruction(const Personality &personality, std::vector return; case AVR::OpCode::ld: { if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { - indirect_load(instructions, personality.get_register(o2.value[0]).value, personality.get_register(o1_reg_num).value); + indirect_load(instructions, personality.get_register(AVR::get_register_number(o2.value[0])).value, personality.get_register(o1_reg_num).value); return; } if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") { - indirect_load(instructions, personality.get_register(o2.value[0]).value, personality.get_register(o1_reg_num).value); + indirect_load(instructions, personality.get_register(AVR::get_register_number(o2.value[0])).value, personality.get_register(o1_reg_num).value); increment_16_bit(personality, instructions, AVR::get_register_number(o2.value[0])); return; } @@ -348,11 +348,11 @@ void translate_instruction(const Personality &personality, std::vector } case AVR::OpCode::st: { if (o1.value == "Z" || o1.value == "Y" || o1.value == "X") { - indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(o1.value[0]).value); + indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(AVR::get_register_number(o1.value[0])).value); return; } if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") { - indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(o1.value[0]).value); + indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(AVR::get_register_number(o1.value[0])).value); increment_16_bit(personality, instructions, AVR::get_register_number(o1.value[0])); return; } From d2241528e5c2cc446f8f6b6799ee350c90a6e437 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sat, 8 May 2021 17:58:14 -0600 Subject: [PATCH 22/27] Implement a bunch more instructions --- include/personalities/c64.hpp | 9 ++ include/personality.hpp | 2 + src/6502-c++.cpp | 157 ++++++++++++++++++++++++---------- 3 files changed, 123 insertions(+), 45 deletions(-) diff --git a/include/personalities/c64.hpp b/include/personalities/c64.hpp index 28080ac..2379222 100644 --- a/include/personalities/c64.hpp +++ b/include/personalities/c64.hpp @@ -17,6 +17,15 @@ struct C64 : Personality new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); } + [[nodiscard]] std::string_view stack_low_address() const override + { + return "$02"; + } + [[nodiscard]] std::string_view stack_high_address() const override + { + return "$03"; + } + [[nodiscard]] Operand get_register(const int reg_num) const override { switch (reg_num) { diff --git a/include/personality.hpp b/include/personality.hpp index b684002..2586eb7 100644 --- a/include/personality.hpp +++ b/include/personality.hpp @@ -9,6 +9,8 @@ class Personality public: virtual void insert_autostart_sequence(std::vector &new_instructions) const = 0; [[nodiscard]] virtual Operand get_register(const int reg_num) const = 0; + [[nodiscard]] virtual std::string_view stack_low_address() const = 0; + [[nodiscard]] virtual std::string_view stack_high_address() const= 0; virtual ~Personality() = default; Personality(const Personality &) = delete; diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index c0f4672..6dd1dbf 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -9,17 +9,25 @@ #include #include #include +#include +#include #include "../include/assembly.hpp" #include "../include/6502.hpp" #include "../include/optimizer.hpp" #include "../include/personalities/c64.hpp" -int parse_8bit_literal(const std::string &s) -{ - return std::stoi(std::string(std::next(std::begin(s)), std::end(s))); + +int to_int(const std::string_view sv) { + int result{}; + std::from_chars(sv.begin(), sv.end(), result); + return result; } +int parse_8bit_literal(const std::string_view s) +{ + return to_int(s.substr(1)); +} std::string_view strip_lo_hi(std::string_view s) { @@ -66,6 +74,7 @@ struct AVR : ASMLine unknown, adc, + adiw, add, andi, @@ -76,6 +85,7 @@ struct AVR : ASMLine clr, com, + cp, cpc, cpi, cpse, @@ -83,7 +93,10 @@ struct AVR : ASMLine eor, + in, + ld, + ldd, ldi, lds, lsl, @@ -99,12 +112,15 @@ struct AVR : ASMLine rjmp, rol, + sbc, sbci, sbiw, sbrc, sbrs, st, + std, sts, + sub, subi, swap, }; @@ -124,9 +140,13 @@ struct AVR : ASMLine if (o == "rol") { return OpCode::rol; } if (o == "rcall") { return OpCode::rcall; } if (o == "ld") { return OpCode::ld; } + if (o == "sub") { return OpCode::subi; } if (o == "subi") { return OpCode::subi; } + if (o == "sbc") { return OpCode::sbci; } if (o == "sbci") { return OpCode::sbci; } if (o == "st") { return OpCode::st; } + if (o == "std") { return OpCode::std; } + if (o == "ldd") { return OpCode::ldd; } if (o == "lds") { return OpCode::lds; } if (o == "lsr") { return OpCode::lsr; } if (o == "andi") { return OpCode::andi; } @@ -136,6 +156,7 @@ struct AVR : ASMLine if (o == "sbrs") { return OpCode::sbrs; } if (o == "brne") { return OpCode::brne; } if (o == "dec") { return OpCode::dec; } + if (o == "adiw") { return OpCode::adiw; } if (o == "sbiw") { return OpCode::sbiw; } if (o == "push") { return OpCode::push; } if (o == "pop") { return OpCode::pop; } @@ -148,11 +169,13 @@ struct AVR : ASMLine if (o == "add") { return OpCode::add; } if (o == "adc") { return OpCode::adc; } if (o == "cpc") { return OpCode::cpc; } + if (o == "cp") { return OpCode::cp; } if (o == "brsh") { return OpCode::brsh; } if (o == "breq") { return OpCode::breq; } + if (o == "in") { return OpCode::in; } } } - throw std::runtime_error(fmt::format("Unknown opcode: {}")); + throw std::runtime_error(fmt::format("Unknown opcode: {}", o)); } static int get_register_number(const char reg_name) @@ -177,7 +200,7 @@ struct AVR : ASMLine } if (o[0] == 'r' && o.size() > 1) { - return Operand(Operand::Type::reg, atoi(&o[1])); + return Operand(Operand::Type::reg, to_int(o.substr(1))); } else { return Operand(Operand::Type::literal, std::string{ o }); } @@ -196,17 +219,17 @@ struct AVR : ASMLine Operand operand2; }; -void indirect_load(std::vector &instructions, const std::string &from_address_low_byte, const std::string &to_address) +void indirect_load(std::vector &instructions, const std::string &from_address_low_byte, const std::string &to_address, const int offset = 0) { - instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, fmt::format("#{}", offset))); instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "(" + from_address_low_byte + "), Y")); instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, to_address)); } -void indirect_store(std::vector &instructions, const std::string &from_address, const std::string &to_address_low_byte) +void indirect_store(std::vector &instructions, const std::string &from_address, const std::string &to_address_low_byte, const int offset = 0) { instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, from_address)); - instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0")); + instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, fmt::format("#{}", offset))); instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, "(" + to_address_low_byte + "), Y")); } @@ -232,6 +255,19 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) instructions.emplace_back(ASMLine::Type::Directive, "; END remove if next is lda"); } +void add_16_bit(const Personality &personality, std::vector &instructions, int reg, const std::uint16_t value) +{ + //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#" + std::to_string((value & 0xFFu)))); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8u) & 0xFFu))); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg + 1)); + instructions.emplace_back(mos6502::OpCode::tax); + fixup_16_bit_N_Z_flags(instructions); +} void subtract_16_bit(const Personality &personality, std::vector &instructions, int reg, const std::uint16_t value) { @@ -312,7 +348,34 @@ void translate_instruction(const Personality &personality, std::vector increment_16_bit(personality, instructions, AVR::get_register_number(o2.value[0])); return; } - throw std::runtime_error("Unhandled ld to non-Z"); + throw std::runtime_error("Unknown ld indexing"); + } + case AVR::OpCode::ldd: { + indirect_load(instructions, personality.get_register(AVR::get_register_number(o2.value[0])).value, personality.get_register(o1_reg_num).value, to_int(o2.value.substr(1))); + return; + } + case AVR::OpCode::std: { + indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(AVR::get_register_number(o1.value[0])).value, to_int(o2.value.substr(1))); + return; + } + case AVR::OpCode::sub: { + // we want to utilize the carry flag, however it was set previously + // (it's really a borrow flag on the 6502) + instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); + fixup_16_bit_N_Z_flags(instructions); + return; + } + case AVR::OpCode::sbc: { + // we want to utilize the carry flag, however it was set previously + // (it's really a borrow flag on the 6502) + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); + fixup_16_bit_N_Z_flags(instructions); + return; } case AVR::OpCode::sbci: { // we want to utilize the carry flag, however it was set previously @@ -388,7 +451,7 @@ void translate_instruction(const Personality &personality, std::vector return; } case AVR::OpCode::sbrc: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (to_int(o2.value)))))); instructions.emplace_back(mos6502::OpCode::bit, personality.get_register(o1_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); @@ -396,7 +459,7 @@ void translate_instruction(const Personality &personality, std::vector return; } case AVR::OpCode::sbrs: { - instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (atoi(o2.value.c_str())))))); + instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal("$" + std::to_string(1 << (to_int(o2.value.c_str())))))); instructions.emplace_back(mos6502::OpCode::bit, personality.get_register(o1_reg_num)); std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); @@ -418,7 +481,12 @@ void translate_instruction(const Personality &personality, std::vector } case AVR::OpCode::sbiw: { - subtract_16_bit(personality, instructions, o1_reg_num, static_cast(std::stoi(o2.value))); + subtract_16_bit(personality, instructions, o1_reg_num, static_cast(to_int(o2.value))); + return; + } + + case AVR::OpCode::adiw: { + add_16_bit(personality, instructions, o1_reg_num, static_cast(to_int(o2.value))); return; } @@ -497,7 +565,12 @@ void translate_instruction(const Personality &personality, std::vector instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } - + case AVR::OpCode::cp: { + // note that this will leave the C flag in the 6502 borrow state, not normal carry state + instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::cmp, personality.get_register(o2_reg_num)); + return; + } case AVR::OpCode::cpc: { // this instruction seems to need to be used in the case after a sbc operation, where the // carry flag is set to the appropriate borrow state, so I'm going to not invert @@ -522,6 +595,22 @@ void translate_instruction(const Personality &personality, std::vector } } + case AVR::OpCode::in: { + if (o2.value == "__SP_L__") { + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{personality.stack_low_address()})); + instructions.emplace_back(mos6502::OpCode::sta, o1); + return; + } + + if (o2.value == "__SP_H__") { + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{ personality.stack_high_address() })); + instructions.emplace_back(mos6502::OpCode::sta, o1); + return; + } + + throw std::runtime_error("Could not translate unknown 'in' instruction"); + } + case AVR::OpCode::breq: { instructions.emplace_back(mos6502::OpCode::beq, o1); return; @@ -534,33 +623,6 @@ void translate_instruction(const Personality &personality, std::vector throw std::runtime_error("Could not translate unhandled instruction"); } -enum class LogLevel { - Warning, - Error -}; - -std::string to_string(const LogLevel ll) -{ - switch (ll) { - case LogLevel::Warning: - return "warning"; - case LogLevel::Error: - return "error"; - } - return "unknown"; -} - - -void log(LogLevel ll, const AVR &i, const std::string &message) -{ - std::cerr << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n"; -} - -void log(LogLevel ll, const std::size_t line_no, const std::string &line, const std::string &message) -{ - std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n"; -} - void to_mos6502(const Personality &personality, const AVR &from_instruction, std::vector &instructions) { try { @@ -606,7 +668,7 @@ void to_mos6502(const Personality &personality, const AVR &from_instruction, std translate_instruction(personality, instructions, from_instruction.opcode, from_instruction.operand1, from_instruction.operand2); } catch (const std::exception &e) { instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + from_instruction.text + "' " + e.what()); - log(LogLevel::Error, from_instruction, e.what()); + spdlog::error("[{}]: Unhandled instruction: '{}': {}", from_instruction.line_num, from_instruction.line_text, e.what()); } auto text = from_instruction.line_text; @@ -619,7 +681,7 @@ void to_mos6502(const Personality &personality, const AVR &from_instruction, std return; } } catch (const std::exception &e) { - log(LogLevel::Error, from_instruction, e.what()); + spdlog::error("[{}]: Unhandled instruction: '{}': {}", from_instruction.line_num, from_instruction.line_text, e.what()); } } @@ -737,7 +799,7 @@ void run(const Personality &personality, std::istream &input) // skip empty lines } } catch (const std::exception &e) { - log(LogLevel::Error, lineno, line, e.what()); + spdlog::error("[{}]: parse exception with '{}': {}", lineno, line, e.what()); } ++lineno; @@ -789,7 +851,12 @@ void run(const Personality &personality, std::istream &input) if (i.text == "0") { i.text = "-memcpy_0"; } else { - i.text = new_labels.at(i.text); + try { + i.text = new_labels.at(i.text); + } catch (...) { + spdlog::error("Error looking up label name: '{}'", i.text); + throw; + } } } From baf9c092eaeaf1ff35393b9d3428cd2e9b41f81f Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sat, 8 May 2021 21:15:21 -0600 Subject: [PATCH 23/27] Add some (broken) stack handling. Need to move to -mtiny-stack --- include/personalities/c64.hpp | 9 +++ src/6502-c++.cpp | 104 +++++++++++++++++++++++++--------- 2 files changed, 86 insertions(+), 27 deletions(-) diff --git a/include/personalities/c64.hpp b/include/personalities/c64.hpp index 2379222..bd52036 100644 --- a/include/personalities/c64.hpp +++ b/include/personalities/c64.hpp @@ -15,6 +15,12 @@ struct C64 : Personality new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address)); new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC"); new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00"); + + // load start of stack space into stack address pointers + new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$FF")); + new_instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, std::string{stack_low_address()})); + new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$CF")); + new_instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, std::string{ stack_high_address() })); } [[nodiscard]] std::string_view stack_low_address() const override @@ -94,6 +100,9 @@ struct C64 : Personality return Operand(Operand::Type::literal, "$5f"); case 31: return Operand(Operand::Type::literal, "$60"); + case 32: + // 32 is the "Stack Pointer", because I decided so, I mean, it makes sense + return Operand(Operand::Type::literal, std::string{stack_low_address()}); } throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); } diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 6dd1dbf..e9fa100 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -1,5 +1,6 @@ #include #include +#include #include #include #include @@ -7,18 +8,18 @@ #include #include #include +#include #include #include -#include -#include -#include "../include/assembly.hpp" #include "../include/6502.hpp" +#include "../include/assembly.hpp" #include "../include/optimizer.hpp" #include "../include/personalities/c64.hpp" -int to_int(const std::string_view sv) { +int to_int(const std::string_view sv) +{ int result{}; std::from_chars(sv.begin(), sv.end(), result); return result; @@ -31,7 +32,7 @@ int parse_8bit_literal(const std::string_view s) std::string_view strip_lo_hi(std::string_view s) { - const auto matcher = ctre::match; + const auto matcher = ctre::match; if (const auto results = matcher(s); results) { return results.get<2>(); @@ -40,6 +41,18 @@ std::string_view strip_lo_hi(std::string_view s) return s; } +std::string_view strip_negate(std::string_view s) +{ + const auto matcher = ctre::match; + + if (const auto results = matcher(s); results) { + return results.get<1>(); + } + + return s; +} + + std::string fixup_8bit_literal(const std::string &s) { if (s[0] == '$') { @@ -67,7 +80,6 @@ std::string fixup_8bit_literal(const std::string &s) } - struct AVR : ASMLine { enum class OpCode { @@ -140,9 +152,9 @@ struct AVR : ASMLine if (o == "rol") { return OpCode::rol; } if (o == "rcall") { return OpCode::rcall; } if (o == "ld") { return OpCode::ld; } - if (o == "sub") { return OpCode::subi; } + if (o == "sub") { return OpCode::sub; } if (o == "subi") { return OpCode::subi; } - if (o == "sbc") { return OpCode::sbci; } + if (o == "sbc") { return OpCode::sbc; } if (o == "sbci") { return OpCode::sbci; } if (o == "st") { return OpCode::st; } if (o == "std") { return OpCode::std; } @@ -336,7 +348,10 @@ void translate_instruction(const Personality &personality, std::vector instructions.emplace_back(mos6502::OpCode::rol, personality.get_register(o1_reg_num)); return; case AVR::OpCode::rcall: - instructions.emplace_back(mos6502::OpCode::jsr, o1); + if (o1.value != ".") { + instructions.emplace_back(mos6502::OpCode::jsr, o1); + } + return; case AVR::OpCode::ld: { if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") { @@ -351,12 +366,20 @@ void translate_instruction(const Personality &personality, std::vector throw std::runtime_error("Unknown ld indexing"); } case AVR::OpCode::ldd: { - indirect_load(instructions, personality.get_register(AVR::get_register_number(o2.value[0])).value, personality.get_register(o1_reg_num).value, to_int(o2.value.substr(1))); - return; + if (o2.value[1] == '+') { + indirect_load(instructions, personality.get_register(AVR::get_register_number(o2.value[0])).value, personality.get_register(o1_reg_num).value, to_int(o2.value.substr(2))); + return; + } + + throw std::runtime_error("Unhandled 'ldd'"); } case AVR::OpCode::std: { - indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(AVR::get_register_number(o1.value[0])).value, to_int(o2.value.substr(1))); - return; + if (o1.value[1] == '+') { + indirect_store(instructions, personality.get_register(o2_reg_num).value, personality.get_register(AVR::get_register_number(o1.value[0])).value, to_int(o1.value.substr(2))); + return; + } + + throw std::runtime_error("Unhandled 'std'"); } case AVR::OpCode::sub: { // we want to utilize the carry flag, however it was set previously @@ -469,10 +492,19 @@ void translate_instruction(const Personality &personality, std::vector case AVR::OpCode::brne: { if (o1.value == "0b") { instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, "memcpy_0")); + return; + } else if (o1.value == ".+2") { + // assumes 6502 'borrow' for Carry flag instead of carry, so bcc instead of bcs + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; } else { instructions.emplace_back(mos6502::OpCode::bne, o1); + return; } - return; + + throw std::runtime_error("Unhanled brne format"); } case AVR::OpCode::rjmp: { @@ -597,14 +629,14 @@ void translate_instruction(const Personality &personality, std::vector case AVR::OpCode::in: { if (o2.value == "__SP_L__") { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{personality.stack_low_address()})); - instructions.emplace_back(mos6502::OpCode::sta, o1); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{ personality.stack_low_address() })); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } if (o2.value == "__SP_H__") { instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{ personality.stack_high_address() })); - instructions.emplace_back(mos6502::OpCode::sta, o1); + instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } @@ -612,8 +644,17 @@ void translate_instruction(const Personality &personality, std::vector } case AVR::OpCode::breq: { - instructions.emplace_back(mos6502::OpCode::beq, o1); - return; + if (o1.value == ".+2") + { + // assumes 6502 'borrow' for Carry flag instead of carry, so bcc instead of bcs + std::string new_label_name = "skip_next_instruction_" + std::to_string(instructions.size()); + instructions.emplace_back(mos6502::OpCode::beq, Operand(Operand::Type::literal, new_label_name)); + instructions.emplace_back(ASMLine::Type::Directive, new_label_name); + return; + } else { + instructions.emplace_back(mos6502::OpCode::beq, o1); + return; + } } case AVR::OpCode::unknown: { throw std::runtime_error("Could not translate 'unknown' instruction"); @@ -637,6 +678,8 @@ void to_mos6502(const Personality &personality, const AVR &from_instruction, std case ASMLine::Type::Directive: if (from_instruction.text.starts_with(".string")) { instructions.emplace_back(ASMLine::Type::Directive, ".asc " + from_instruction.text.substr(7)); + } else if (from_instruction.text.starts_with(".byte")) { + instructions.emplace_back(ASMLine::Type::Directive, ".byt " + from_instruction.text.substr(5)); } else if (from_instruction.text.starts_with(".zero")) { const auto count = std::stoull(&*std::next(from_instruction.text.begin(), 6), nullptr, 10); @@ -826,8 +869,8 @@ void run(const Personality &personality, std::istream &input) check_label(i.operand1.value); check_label(i.operand2.value); - check_label(std::string{ strip_lo_hi(i.operand1.value) }); - check_label(std::string{ strip_lo_hi(i.operand2.value) }); + check_label(std::string{ strip_negate(strip_lo_hi(i.operand1.value)) }); + check_label(std::string{ strip_negate(strip_lo_hi(i.operand2.value)) }); } } @@ -835,16 +878,23 @@ void run(const Personality &personality, std::istream &input) [&used_labels]() { std::map result; for (const auto &l : used_labels) { - auto newl = l; - std::transform(newl.begin(), newl.end(), newl.begin(), [](const auto c) { return std::tolower(c); }); - newl.erase(std::remove_if(newl.begin(), newl.end(), [](const auto c) { return !std::isalnum(c); }), std::end(newl)); +// auto newl = l; +// std::transform(newl.begin(), newl.end(), newl.begin(), [](const auto c) { return std::tolower(c); }); +// newl.erase(std::remove_if(newl.begin(), newl.end(), [](const auto c) { return !std::isalnum(c); }), std::end(newl)); - result.emplace(std::make_pair(l, newl)); + // strip just first \. + if (l[0] == '.') { + result.emplace(std::make_pair(l, l.substr(1))); + } else { + result.emplace(std::make_pair(l, l)); + } } return result; }(); - + for (const auto &label : new_labels) { + spdlog::trace("used label: '{}':'{}'", label.first, label.second); + } for (auto &i : instructions) { if (i.type == ASMLine::Type::Label) { @@ -883,7 +933,7 @@ void run(const Personality &personality, std::istream &input) std::vector new_instructions; personality.insert_autostart_sequence(new_instructions); - // set __zero_reg__ (reg 1 on AVR) to 0 + // set __zero_reg__ (reg 1 on AVR) to 0 new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00")); new_instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(1)); new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main")); From a4edf7194e4d10e0e5c879223b9de1dd1790846b Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sat, 8 May 2021 22:58:55 -0600 Subject: [PATCH 24/27] Better stack handling. We now require -mtiny-stack from GCC --- compile.sh | 2 +- include/6502.hpp | 16 ++++++++++++++++ include/optimizer.hpp | 8 +++++++- include/personalities/c64.hpp | 3 --- src/6502-c++.cpp | 33 +++++++++++++++++++++++++-------- 5 files changed, 49 insertions(+), 13 deletions(-) diff --git a/compile.sh b/compile.sh index d75d0d5..c8c0fcc 100755 --- a/compile.sh +++ b/compile.sh @@ -1 +1 @@ -avr-gcc $1 -Wall -Wextra -c -o- -S -O3 -I ~/avr-libstdcpp/include/ -std=c++20 | tee $1.asm | ./avr-to-6502 | tee $1.asm && xa -O PETSCREEN -M $1.prg +avr-gcc $1 -Wall -Wextra -mtiny-stack -c -o- -S -O3 -I ~/avr-libstdcpp/include/ -std=c++20 | tee $1.asm | ./avr-to-6502 | tee $1.asm && xa -O PETSCREEN -M $1.prg diff --git a/include/6502.hpp b/include/6502.hpp index e14cfdb..cc8914e 100644 --- a/include/6502.hpp +++ b/include/6502.hpp @@ -34,6 +34,7 @@ struct mos6502 : ASMLine jsr, lda, + ldx, ldy, lsr, @@ -51,11 +52,14 @@ struct mos6502 : ASMLine sbc, sec, sta, + stx, sty, tax, tay, + tsx, txa, + txs, tya, }; @@ -82,6 +86,7 @@ struct mos6502 : ASMLine case OpCode::jmp: case OpCode::jsr: case OpCode::lda: + case OpCode::ldx: case OpCode::ldy: case OpCode::lsr: case OpCode::ORA: @@ -96,9 +101,12 @@ struct mos6502 : ASMLine case OpCode::sec: case OpCode::sta: case OpCode::sty: + case OpCode::stx: case OpCode::tax: case OpCode::tay: + case OpCode::tsx: case OpCode::txa: + case OpCode::txs: case OpCode::tya: case OpCode::unknown: @@ -130,6 +138,7 @@ struct mos6502 : ASMLine case OpCode::jmp: case OpCode::jsr: case OpCode::lda: + case OpCode::ldx: case OpCode::ldy: case OpCode::lsr: case OpCode::ORA: @@ -143,10 +152,13 @@ struct mos6502 : ASMLine case OpCode::sbc: case OpCode::sec: case OpCode::sta: + case OpCode::stx: case OpCode::sty: case OpCode::tax: case OpCode::tay: + case OpCode::tsx: case OpCode::txa: + case OpCode::txs: case OpCode::tya: case OpCode::unknown: break; @@ -176,15 +188,19 @@ struct mos6502 : ASMLine case OpCode::lda: return "lda"; case OpCode::asl: return "asl"; case OpCode::rol: return "rol"; + case OpCode::ldx: return "ldx"; case OpCode::ldy: return "ldy"; case OpCode::tay: return "tay"; case OpCode::tya: return "tya"; case OpCode::tax: return "tax"; + case OpCode::tsx: return "tsx"; case OpCode::txa: return "txa"; + case OpCode::txs: return "txs"; case OpCode::cpy: return "cpy"; case OpCode::eor: return "eor"; case OpCode::sta: return "sta"; case OpCode::sty: return "sty"; + case OpCode::stx: return "stx"; case OpCode::pha: return "pha"; case OpCode::pla: return "pla"; case OpCode::php: return "php"; diff --git a/include/optimizer.hpp b/include/optimizer.hpp index dd442de..69fc036 100644 --- a/include/optimizer.hpp +++ b/include/optimizer.hpp @@ -103,6 +103,10 @@ bool optimize(std::vector &instructions) } } + // todo: fix this ldy redundant move, right now it doesn't + // take into account if Y has been used + + /* for (size_t op = 0; op < instructions.size() - 1; ++op) { if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) { auto op2 = op + 1; @@ -116,7 +120,9 @@ bool optimize(std::vector &instructions) ++op2; } } - } + } + */ + for (size_t op = 0; op < instructions.size() - 1; ++op) { if (instructions[op].opcode == mos6502::OpCode::lda diff --git a/include/personalities/c64.hpp b/include/personalities/c64.hpp index bd52036..2863579 100644 --- a/include/personalities/c64.hpp +++ b/include/personalities/c64.hpp @@ -100,9 +100,6 @@ struct C64 : Personality return Operand(Operand::Type::literal, "$5f"); case 31: return Operand(Operand::Type::literal, "$60"); - case 32: - // 32 is the "Stack Pointer", because I decided so, I mean, it makes sense - return Operand(Operand::Type::literal, std::string{stack_low_address()}); } throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num)); } diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index e9fa100..41f163a 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -116,6 +116,8 @@ struct AVR : ASMLine mov, + out, + pop, push, @@ -185,6 +187,7 @@ struct AVR : ASMLine if (o == "brsh") { return OpCode::brsh; } if (o == "breq") { return OpCode::breq; } if (o == "in") { return OpCode::in; } + if (o == "out") { return OpCode::out; } } } throw std::runtime_error(fmt::format("Unknown opcode: {}", o)); @@ -249,7 +252,7 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) { // need to get both Z and N set appropriately - // assuming A contains higher order byte and Y contains lower order byte + // assuming A contains higher order byte and X contains lower order byte instructions.emplace_back(ASMLine::Type::Directive, "; BEGIN remove if next is lda"); instructions.emplace_back(ASMLine::Type::Directive, "; set CPU flags assuming A holds the higher order byte already"); std::string set_flag_label = "flags_set_after_16_bit_op_" + std::to_string(instructions.size()); @@ -269,29 +272,29 @@ void fixup_16_bit_N_Z_flags(std::vector &instructions) void add_16_bit(const Personality &personality, std::vector &instructions, int reg, const std::uint16_t value) { - //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); instructions.emplace_back(mos6502::OpCode::clc); instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg)); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#" + std::to_string((value & 0xFFu)))); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::tax); instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg + 1)); instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8u) & 0xFFu))); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg + 1)); - instructions.emplace_back(mos6502::OpCode::tax); + fixup_16_bit_N_Z_flags(instructions); } void subtract_16_bit(const Personality &personality, std::vector &instructions, int reg, const std::uint16_t value) { - //instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte)); instructions.emplace_back(mos6502::OpCode::sec); instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg)); instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value & 0xFFu)))); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg)); + instructions.emplace_back(mos6502::OpCode::tax); instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(reg + 1)); instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#" + std::to_string((value >> 8u) & 0xFFu))); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(reg + 1)); - instructions.emplace_back(mos6502::OpCode::tax); + fixup_16_bit_N_Z_flags(instructions); } @@ -626,16 +629,30 @@ void translate_instruction(const Personality &personality, std::vector return; } } + case AVR::OpCode::out: { + if (o1.value == "__SP_L__") { + instructions.emplace_back(mos6502::OpCode::ldx, personality.get_register(o2_reg_num)); + instructions.emplace_back(mos6502::OpCode::txs); + return; + } + + if (o1.value == "__SP_H__") { + // officially nothing to do - we cannot change the high byte of the SP on 6502 + return; + } + + throw std::runtime_error("Could not translate unknown 'out' instruction"); + } case AVR::OpCode::in: { if (o2.value == "__SP_L__") { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{ personality.stack_low_address() })); - instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::tsx); + instructions.emplace_back(mos6502::OpCode::stx, personality.get_register(o1_reg_num)); return; } if (o2.value == "__SP_H__") { - instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, std::string{ personality.stack_high_address() })); + instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "$01")); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); return; } From 9fe26641b777dacc02e57973c8e5d1d1d9c6c85b Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sun, 9 May 2021 08:39:55 -0600 Subject: [PATCH 25/27] Add additional example --- .../16bit_counter_with_map_and_strings.cpp | 214 ++++++++++++++++++ 1 file changed, 214 insertions(+) create mode 100644 examples/16bit_counter_with_map_and_strings.cpp diff --git a/examples/16bit_counter_with_map_and_strings.cpp b/examples/16bit_counter_with_map_and_strings.cpp new file mode 100644 index 0000000..634607f --- /dev/null +++ b/examples/16bit_counter_with_map_and_strings.cpp @@ -0,0 +1,214 @@ +#include +#include +#include +#include +#include + +enum Colors : uint8_t { WHITE = 0x01 }; + +static volatile uint8_t &memory_loc(const uint16_t loc) { + return *reinterpret_cast(loc); +} + +static void poke(const uint16_t loc, const uint8_t value) { + memory_loc(loc) = value; +} + +static std::uint8_t peek(const std::uint16_t loc) { return memory_loc(loc); } + +static void decrement_border_color() { --memory_loc(0xd020); } + +static void increment_border_color() { ++memory_loc(0xd020); } + +static bool joystick_down() { + uint8_t joystick_state = peek(0xDC00); + return (joystick_state & 2) == 0; +} + +void use_data(std::array &data); + +static void puts(uint8_t x, uint8_t y, std::string_view str) { + const auto start = 0x400 + (y * 40 + x); + + std::memcpy(const_cast(&memory_loc(start)), str.data(), + str.size()); +} + + +template +struct Graphic +{ + std::array data; + + static constexpr auto width() noexcept { + return Width; + } + + static constexpr auto height() noexcept { + return Height; + } + + constexpr Graphic() = default; + + constexpr Graphic(std::array data_) noexcept : data(data_) {} + constexpr Graphic(std::initializer_list data_) noexcept { + std::copy(begin(data_), end(data_), begin(data)); + } + + constexpr auto &operator()(const std::uint8_t x, const std::uint8_t y) noexcept { + return data[y * Width + x]; + } + + constexpr const auto &operator()(const std::uint8_t x, const std::uint8_t y) const noexcept { + return data[y * Width + x]; + } +}; + +static void putc(uint8_t x, uint8_t y, uint8_t c) { + const auto start = 0x400 + (y * 40 + x); + poke(start, c); +} + +static void put_hex(uint8_t x, uint8_t y, uint8_t value) { + const auto put_nibble = [](auto x, auto y, uint8_t nibble) { + if (nibble <= 9) { + putc(x, y, nibble + 48); + } else { + putc(x, y, nibble - 9); + } + }; + + put_nibble(x + 1, y, 0xF & value); + put_nibble(x, y, 0xF & (value >> 4)); +} + +static void put_hex(uint8_t x, uint8_t y, uint16_t value) { + put_hex(x+2,y, static_cast(0xFF & value)); + put_hex(x,y, static_cast(0xFF & (value >> 8))); +} + +static void put_graphic(uint8_t x, uint8_t y, const auto &graphic) +{ + for (uint8_t cur_y = 0; cur_y < graphic.height(); ++cur_y) { + for (uint8_t cur_x = 0; cur_x < graphic.width(); ++cur_x) { + putc(cur_x + x, cur_y + y, graphic(cur_x, cur_y)); + } + } +} + +struct Clock { + using milliseconds = std::chrono::duration; + + // return elapsed time since last restart + [[nodiscard]] milliseconds restart() { + // stop Timer A + poke(0xDC0E, 0b00000000); + + // last value + const auto previous_value = static_cast( + peek(0xDC04) | (static_cast(peek(0xDC05)) << 8)); + + // reset timer + poke(0xDC04, 0xFF); + poke(0xDC05, 0xFF); + + // restart timer A + poke(0xDC0E, 0b00010001); + + return milliseconds{0xFFFF - previous_value}; + } + + Clock() { [[maybe_unused]] const auto value = restart(); } +}; + +int main() { + + // static constexpr std::array data{0}; + // std::memcpy(const_cast(&memory_loc(0x400)), data.data(), + // data.size()); + + static constexpr auto pic = + Graphic<5,4>{ + 78,119,77,32,32, + 101,32,32,80,32, + 101,79,101,103,32, + 76,101,76,122,88 + }; + + static constexpr auto map1 = + Graphic<4, 2>{ + 1,0,1,0, + 1,1,1,1 + }; + + static constexpr auto map2 = + Graphic<6, 3>{ + 1,0,1,0,0,0, + 1,1,1,1,0,1, + 0,0,0,1,0,0 + }; + +/* + static constexpr auto map = + Graphic<10, 2>{ + 0,1,0,1,0,0,0,1,0,0, + 1,0,0,0,0,0,1,0,0,0, + }; +*/ + // put_graphic(10,10,pic); + + + const auto draw_map = [](const auto &map) { + for (std::uint8_t y=0; y < map.height(); ++y) { + for (std::uint8_t x = 0; x < map.width(); ++x) { + if (map(x, y) == 1) { + put_graphic(x*4, y*4, pic); + } + } + } + }; + + puts(5, 17, "timing history"); + puts(21, 17, "16bit counter"); + + +// draw_map(map1); + draw_map(map2); + + + Clock game_clock{}; + + + std::uint16_t counter = 0; + std::uint8_t y = 19; + + while (true) { + const auto us_elapsed = game_clock.restart().count(); + + put_hex(5, y, us_elapsed); + put_hex(21, y, counter); + + if (y++ == 24) { + y = 19; + } + + ++counter; + increment_border_color(); + } + + /* + const auto background_color = [](Colors col) { + memory_loc(0xd021) = static_cast(col); + }; + + background_color(Colors::WHITE); + + while(true) { + if (joystick_down()) { + increment_border_color(); + } else { + decrement_border_color(); + } + } + */ +} From eedec41b1e47f795a0219e497f3b276a9a1acf7f Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Sun, 9 May 2021 17:31:44 -0600 Subject: [PATCH 26/27] Fix handling of sbc/sub and enable parsing of -fverbose-asm --- include/optimizer.hpp | 2 ++ src/6502-c++.cpp | 23 ++++++++++++----------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/include/optimizer.hpp b/include/optimizer.hpp index 69fc036..74f836c 100644 --- a/include/optimizer.hpp +++ b/include/optimizer.hpp @@ -6,6 +6,8 @@ bool optimize(std::vector &instructions) { + // return false; + if (instructions.size() < 2) { return false; } diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 41f163a..324f3f5 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -385,11 +385,9 @@ void translate_instruction(const Personality &personality, std::vector throw std::runtime_error("Unhandled 'std'"); } case AVR::OpCode::sub: { - // we want to utilize the carry flag, however it was set previously - // (it's really a borrow flag on the 6502) - instructions.emplace_back(mos6502::OpCode::clc); + instructions.emplace_back(mos6502::OpCode::sec); instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o2_reg_num)); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); fixup_16_bit_N_Z_flags(instructions); return; @@ -398,7 +396,7 @@ void translate_instruction(const Personality &personality, std::vector // we want to utilize the carry flag, however it was set previously // (it's really a borrow flag on the 6502) instructions.emplace_back(mos6502::OpCode::lda, personality.get_register(o1_reg_num)); - instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o1_reg_num)); + instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o2_reg_num)); instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num)); fixup_16_bit_N_Z_flags(instructions); return; @@ -716,7 +714,9 @@ void to_mos6502(const Personality &personality, const AVR &from_instruction, std if (!zeros.empty()) { instructions.emplace_back(ASMLine::Type::Directive, zeros); } - + } else if (from_instruction.text[0] == ';') { + // it's a comment + instructions.emplace_back(ASMLine::Type::Directive, from_instruction.text); } else { instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + from_instruction.text); } @@ -826,12 +826,12 @@ bool fix_overwritten_flags(std::vector &instructions) void run(const Personality &personality, std::istream &input) { - std::regex Comment(R"(\s*\#.*)"); + std::regex Comment(R"(\s*(\#|;)(.*))"); std::regex Label(R"(^\s*(\S+):.*)"); std::regex Directive(R"(^\s*(\..+))"); - std::regex UnaryInstruction(R"(^\s+(\S+)\s+(\S+))"); - std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+))"); - std::regex Instruction(R"(^\s+(\S+))"); + std::regex UnaryInstruction(R"(^\s+(\S+)\s+(\S+).*)"); + std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+).*)"); + std::regex Instruction(R"(^\s+(\S+).*)"); std::size_t lineno = 0; @@ -846,7 +846,8 @@ void run(const Personality &personality, std::istream &input) if (std::regex_match(line, match, Label)) { instructions.emplace_back(lineno, line, ASMLine::Type::Label, match[1].str()); } else if (std::regex_match(line, match, Comment)) { - // don't care about comments + // save comments! + instructions.emplace_back(lineno, line, ASMLine::Type::Directive, "; " + match[2].str()); } else if (std::regex_match(line, match, Directive)) { instructions.emplace_back(lineno, line, ASMLine::Type::Directive, match[1].str()); } else if (std::regex_match(line, match, BinaryInstruction)) { From a1c596622bb61373def990e3e18f5355095b2bd9 Mon Sep 17 00:00:00 2001 From: Jason Turner Date: Tue, 11 May 2021 09:16:41 -0600 Subject: [PATCH 27/27] Disable a fixup, which might not be necessary now --- src/6502-c++.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/6502-c++.cpp b/src/6502-c++.cpp index 324f3f5..f06546e 100644 --- a/src/6502-c++.cpp +++ b/src/6502-c++.cpp @@ -984,9 +984,12 @@ void run(const Personality &personality, std::istream &input) } } - while (fix_overwritten_flags(new_instructions)) { + // it seems that with the move to AVR for the base, this + // fixup no longer makes sense, but I'm not going to remove it just yet + // until we have more complex C++ examples working +// while (fix_overwritten_flags(new_instructions)) { // do it however many times it takes - } +// } while (optimize(new_instructions)) { // do it however many times it takes