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https://github.com/lefticus/6502-cpp.git
synced 2024-06-02 02:41:33 +00:00
Ability to copy from .data section resources to RAM
This commit is contained in:
Jason Turner
parent
ad75dcdfef
commit
51c5767f0e
177
src/main.cpp
177
src/main.cpp
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@ -28,6 +28,17 @@ int parse_8bit_literal(const std::string &s)
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return std::stoi(std::string(std::next(std::begin(s)), std::end(s)));
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}
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std::string strip_lo_hi(const std::string &s)
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{
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if ((s.starts_with("lo8(") || s.starts_with("hi8("))
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&& s.ends_with(")")) {
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return s.substr(4, s.size() - 5);
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}
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return s;
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}
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std::string fixup_8bit_literal(const std::string &s)
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{
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if (s[0] == '$')
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@ -35,7 +46,13 @@ std::string fixup_8bit_literal(const std::string &s)
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return "#" + std::to_string(static_cast<uint8_t>(parse_8bit_literal(s)));
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} else {
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if (s.starts_with("lo8(") && s.ends_with(")")) {
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return "#<" + s.substr(4, s.size() - 5);
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return "#<" + strip_lo_hi(s);
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}
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if (s.starts_with("hi8(") && s.ends_with(")")) {
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return "#>" + strip_lo_hi(s);
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}
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if (s == "0") {
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return "#0";
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}
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return s;
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@ -511,7 +528,9 @@ struct AVR : ASMLine
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eor,
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sbrc,
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sbrs,
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rjmp
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brne,
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rjmp,
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dec
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};
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static OpCode parse_opcode(Type t, const std::string &o)
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@ -541,16 +560,38 @@ struct AVR : ASMLine
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if (o == "sbrc") return OpCode::sbrc;
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if (o == "rjmp") return OpCode::rjmp;
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if (o == "sbrs") return OpCode::sbrs;
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if (o == "brne") return OpCode::brne;
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if (o == "dec") return OpCode::dec;
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}
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}
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throw std::runtime_error("Unknown opcode: " + o);
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}
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static int get_register_number(const char reg_name)
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{
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if (reg_name == 'X') {
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return 26;
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}
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if (reg_name == 'Y') {
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return 28;
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}
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if (reg_name == 'Z') {
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return 30;
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}
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}
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static Operand get_register(const char reg_name, const int byte = 0) {
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return get_register(get_register_number(reg_name), byte);
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}
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static Operand get_register(const int reg_num, [[maybe_unused]] const int offset = 0) {
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switch (reg_num) {
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// http://sta.c64.org/cbm64mem.html
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case 0: return Operand(Operand::Type::literal, "$03"); // unused, fp->int routine pointer
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case 1: return Operand(Operand::Type::literal, "$04");
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case 0: return Operand(Operand::Type::literal, "$a7"); // bit buffer for rs232
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case 1: return Operand(Operand::Type::literal, "$a8"); // counter for rs232
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case 2: return Operand(Operand::Type::literal, "$05"); // unused, int->fp routine pointer
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case 3: return Operand(Operand::Type::literal, "$06");
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case 4: return Operand(Operand::Type::literal, "$fb"); // unused
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@ -612,10 +653,42 @@ static Operand get_register(const int reg_num, [[maybe_unused]] const int offset
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Operand operand2;
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};
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void indirect_load(std::vector<mos6502> &instructions, const std::string &from_address_low_byte, const std::string &to_address)
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{
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0"));
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal,
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"(" + from_address_low_byte + "), Y"));
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instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, to_address));
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}
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void indirect_store(std::vector<mos6502> &instructions, const std::string &from_address, const std::string &to_address_low_byte)
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{
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, from_address));
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0"));
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instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal,
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"(" + to_address_low_byte + "), Y") );
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}
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void increment_16_bit(std::vector<mos6502> & instructions, int reg) {
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//instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, address_low_byte));
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instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg));
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instructions.emplace_back(mos6502::OpCode::clc);
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instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#1"));
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instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg));
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instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(reg+1));
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instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#0"));
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instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(reg+1));
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}
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void translate_instruction(std::vector<mos6502> &instructions, const AVR::OpCode op, const Operand &o1, const Operand &o2)
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{
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switch(op)
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{
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case AVR::OpCode::dec:
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instructions.emplace_back(mos6502::OpCode::dec, AVR::get_register(o1.reg_num));
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return;
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case AVR::OpCode::ldi:
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o2.type, fixup_8bit_literal(o2.value)));
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instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num));
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@ -642,11 +715,13 @@ void translate_instruction(std::vector<mos6502> &instructions, const AVR::OpCode
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return;
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case AVR::OpCode::ld:
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{
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if (o2.value == "Z") {
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0"));
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal,
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"(" + AVR::get_register(30).value + "), Y"));
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instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(o1.reg_num));
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if (o2.value == "Z" || o2.value == "X" || o2.value == "Y") {
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indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1.reg_num).value);
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return;
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}
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if (o2.value == "Z+" || o2.value == "X+" || o2.value == "Y+") {
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indirect_load(instructions, AVR::get_register(o2.value[0]).value, AVR::get_register(o1.reg_num).value);
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increment_16_bit(instructions, AVR::get_register_number(o2.value[0]));
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return;
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}
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throw std::runtime_error("Unhandled ld to non-Z");
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@ -668,15 +743,16 @@ void translate_instruction(std::vector<mos6502> &instructions, const AVR::OpCode
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throw std::runtime_error("Unhandled subi sub case");
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}
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case AVR::OpCode::st: {
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if (o1.value == "Z") {
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instructions.emplace_back(mos6502::OpCode::lda, AVR::get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0"));
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instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal,
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"(" + AVR::get_register(30).value + "), Y"));
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if (o1.value == "Z" || o1.value == "Y"||o1.value == "X") {
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indirect_store(instructions, AVR::get_register(o2.reg_num).value, AVR::get_register(o1.value[0]).value);
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return;
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}
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throw std::runtime_error("Unhandled st with non-Z parameter");
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if (o1.value == "Z+" || o1.value == "Y+" || o1.value == "X+") {
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indirect_store(instructions, AVR::get_register(o2.reg_num).value, AVR::get_register(o1.value[0]).value);
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increment_16_bit(instructions, AVR::get_register_number(o1.value[0]));
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return;
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}
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throw std::runtime_error("Unhandled st");
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}
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case AVR::OpCode::lds: {
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instructions.emplace_back(mos6502::OpCode::lda, o2);
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@ -715,6 +791,15 @@ void translate_instruction(std::vector<mos6502> &instructions, const AVR::OpCode
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instructions.emplace_back(ASMLine::Type::Directive, new_label_name);
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return;
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}
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case AVR::OpCode::brne: {
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if (o1.value == "0b") {
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instructions.emplace_back(mos6502::OpCode::bne, Operand(Operand::Type::literal, "memcpy_0"));
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} else {
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instructions.emplace_back(mos6502::OpCode::bne, o1);
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}
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return;
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}
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case AVR::OpCode::rjmp: {
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instructions.emplace_back(mos6502::OpCode::jmp, o1);
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return;
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@ -1043,10 +1128,18 @@ void to_mos6502(const FromArch &i, std::vector<mos6502> &instructions)
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switch(i.type)
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{
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case ASMLine::Type::Label:
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instructions.emplace_back(i.type, i.text);
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if (i.text == "0") {
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instructions.emplace_back(i.type, "-memcpy_0");
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} else {
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instructions.emplace_back(i.type, i.text);
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}
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return;
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case ASMLine::Type::Directive:
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instructions.emplace_back(i.type, i.text);
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if (i.text.starts_with(".string")) {
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instructions.emplace_back(ASMLine::Type::Directive, ".asc " + i.text.substr(7));
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} else {
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instructions.emplace_back(ASMLine::Type::Directive, "; Unknown directive: " + i.text);
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}
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return;
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case ASMLine::Type::Instruction:
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const auto head = instructions.size();
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@ -1054,6 +1147,7 @@ void to_mos6502(const FromArch &i, std::vector<mos6502> &instructions)
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try {
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translate_instruction(instructions, i.opcode, i.operand1, i.operand2);
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} catch (const std::exception &e) {
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instructions.emplace_back(ASMLine::Type::Directive, "; Unhandled opcode: '" + i.text + "' " + e.what());
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log(LogLevel::Error, i, e.what());
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}
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@ -1218,7 +1312,7 @@ bool fix_overwritten_flags(std::vector<mos6502> &instructions)
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template<typename Arch>
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void run(std::istream &input) {
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std::regex Comment(R"(\s*\#.*)");
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std::regex Label(R"(^(\S+):.*)");
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std::regex Label(R"(^\s*(\S+):.*)");
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std::regex Directive(R"(^\s*(\..+))");
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std::regex UnaryInstruction(R"(^\s+(\S+)\s+(\S+))");
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std::regex BinaryInstruction(R"(^\s+(\S+)\s+(\S+),\s*(\S+))");
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@ -1273,26 +1367,35 @@ void run(std::istream &input) {
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{
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if (i.type == ASMLine::Type::Instruction)
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{
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if (labels.count(i.operand1.value) != 0) {
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used_labels.insert(i.operand1.value);
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used_labels.insert(i.operand2.value);
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}
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// if (labels.count(i.operand1.value) != 0) {
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used_labels.insert(strip_lo_hi(i.operand1.value));
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used_labels.insert(strip_lo_hi(i.operand2.value));
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// }
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}
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}
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used_labels.erase("X");
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used_labels.erase("X+");
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used_labels.erase("-X");
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used_labels.erase("Y");
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used_labels.erase("Y+");
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used_labels.erase("-Y");
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used_labels.erase("Z");
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used_labels.erase("Z+");
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used_labels.erase("-Z");
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// remove all labels and directives that we don't need
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instructions.erase(
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std::remove_if(std::begin(instructions), std::end(instructions),
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[&used_labels](const auto &i){
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if (i.type == ASMLine::Type::Label) {
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if (used_labels.count(i.text) == 0) {
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std::cout << "; removed label: '" << i.text << "'\n";
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// if (used_labels.count(i.text) == 0) {
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// std::cout << "; removed label: '" << i.text << "'\n";
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// remove all unused labels that aren't 'main'
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return true;
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}
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// return true;
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// }
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}
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if (i.type == ASMLine::Type::Directive) {
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return true;
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// return true;
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}
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return false;
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}
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@ -1305,24 +1408,39 @@ void run(std::istream &input) {
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const auto new_labels =
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[&used_labels](){
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std::map<std::string, std::string> result;
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// result.emplace(std::make_pair("0", "-memcpy_0"));
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for (const auto &l : used_labels) {
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auto newl = l;
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std::transform(newl.begin(), newl.end(), newl.begin(), [](const auto c) { return std::tolower(c); });
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newl.erase(std::remove_if(newl.begin(), newl.end(), [](const auto c){ return !std::isalnum(c); }), std::end(newl));
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result.emplace(std::make_pair(l, newl));
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}
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return result;
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}();
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for (const auto &l : new_labels) {
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std::clog << "Label: '" << l.first << "': '" << l.second << "'\n";
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}
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for (auto &i : instructions)
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{
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if (i.type == ASMLine::Type::Label)
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{
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std::clog << "Looking up Label: '" << i.text << "'\n";
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i.text = new_labels.at(i.text);
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}
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if (i.operand2.value.starts_with("lo8(") || i.operand2.value.starts_with("hi8("))
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{
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const auto potential_label = strip_lo_hi(i.operand2.value);
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const auto itr1 = new_labels.find(potential_label);
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if (itr1 != new_labels.end()) {
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i.operand2.value.replace(4, potential_label.size(), itr1->second);
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}
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}
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const auto itr1 = new_labels.find(i.operand1.value);
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if (itr1 != new_labels.end()) {
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i.operand1.value = itr1->second;
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@ -1338,6 +1456,7 @@ void run(std::istream &input) {
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std::vector<mos6502> new_instructions;
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new_instructions.emplace_back(ASMLine::Type::Directive, ".word $1000");
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new_instructions.emplace_back(ASMLine::Type::Directive, "* = $1000");
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new_instructions.emplace_back(mos6502::OpCode::jmp, Operand(Operand::Type::literal, "main"));
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bool skip_next_instruction = false;
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std::string next_label_name;
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