mirror of
https://github.com/lefticus/6502-cpp.git
synced 2024-06-26 00:29:30 +00:00
Support much more translation
* many opcodes added * more registers * bug fixes * parsing of clang output enabled
This commit is contained in:
Jason Turner
parent
6439a13113
commit
974c907a3b
226
src/main.cpp
226
src/main.cpp
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@ -22,11 +22,16 @@ struct ASMLine
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std::string text;
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};
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int parse_8bit_literal(const std::string &s)
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{
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return std::stoi(std::string(std::next(std::begin(s)), std::end(s)));
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}
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std::string fixup_8bit_literal(const std::string &s)
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{
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if (s[0] == '$')
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{
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return "#" + std::to_string(static_cast<uint8_t>(std::stoi(std::string(std::next(std::begin(s)), std::end(s)))));
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return "#" + std::to_string(static_cast<uint8_t>(parse_8bit_literal(s)));
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} else {
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return s;
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}
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@ -60,6 +65,15 @@ struct Operand
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}
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};
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Operand get_register(int reg_num) {
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switch (reg_num) {
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case 2: return Operand(Operand::Type::literal, "$fb");
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case 3: return Operand(Operand::Type::literal, "$fc");
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case 4: return Operand(Operand::Type::literal, "$fd");
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};
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throw std::runtime_error("Cannot translate instruction");
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}
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struct mos6502 : ASMLine
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{
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enum class OpCode
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@ -67,16 +81,25 @@ struct mos6502 : ASMLine
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unknown,
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lda,
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ldy,
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tay,
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tya,
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cpy,
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eor,
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sta,
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sty,
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pha,
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pla,
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php,
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plp,
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lsr,
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AND,
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inc,
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dec,
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ORA,
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cmp,
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bne,
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beq,
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bmi,
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jmp,
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adc,
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sbc,
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@ -87,16 +110,25 @@ struct mos6502 : ASMLine
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switch (o) {
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case OpCode::beq:
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case OpCode::bne:
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case OpCode::bmi:
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return true;
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case OpCode::lda:
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case OpCode::ldy:
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case OpCode::tay:
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case OpCode::tya:
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case OpCode::cpy:
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case OpCode::eor:
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case OpCode::sta:
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case OpCode::sty:
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case OpCode::pha:
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case OpCode::pla:
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case OpCode::php:
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case OpCode::plp:
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case OpCode::lsr:
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case OpCode::AND:
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case OpCode::inc:
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case OpCode::dec:
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case OpCode::ORA:
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case OpCode::cmp:
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case OpCode::jmp:
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case OpCode::adc:
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@ -111,18 +143,27 @@ struct mos6502 : ASMLine
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static bool get_is_comparison(const OpCode o) {
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switch (o) {
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case OpCode::cmp:
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case OpCode::cpy:
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return true;
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case OpCode::lda:
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case OpCode::ldy:
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case OpCode::tay:
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case OpCode::tya:
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case OpCode::eor:
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case OpCode::sta:
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case OpCode::sty:
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case OpCode::pha:
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case OpCode::pla:
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case OpCode::php:
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case OpCode::plp:
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case OpCode::lsr:
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case OpCode::AND:
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case OpCode::inc:
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case OpCode::dec:
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case OpCode::ORA:
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case OpCode::jmp:
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case OpCode::bne:
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case OpCode::bmi:
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case OpCode::beq:
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case OpCode::adc:
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case OpCode::sbc:
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@ -156,6 +197,12 @@ struct mos6502 : ASMLine
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return "lda";
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case OpCode::ldy:
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return "ldy";
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case OpCode::tay:
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return "tay";
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case OpCode::tya:
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return "tya";
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case OpCode::cpy:
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return "cpy";
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case OpCode::eor:
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return "eor";
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case OpCode::sta:
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@ -166,14 +213,26 @@ struct mos6502 : ASMLine
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return "pha";
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case OpCode::pla:
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return "pla";
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case OpCode::php:
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return "php";
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case OpCode::plp:
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return "plp";
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case OpCode::lsr:
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return "lsr";
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case OpCode::AND:
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return "and";
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case OpCode::inc:
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return "inc";
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case OpCode::dec:
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return "dec";
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case OpCode::ORA:
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return "ora";
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case OpCode::cmp:
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return "cmp";
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case OpCode::bne:
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return "bne";
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case OpCode::bmi:
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return "bmi";
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case OpCode::beq:
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return "beq";
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case OpCode::jmp:
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@ -222,6 +281,7 @@ struct i386 : ASMLine
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shrb,
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xorl,
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andl,
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andb,
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ret,
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movb,
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cmpb,
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@ -229,9 +289,20 @@ struct i386 : ASMLine
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jmp,
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jne,
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je,
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js,
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testb,
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incl,
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incb,
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decl,
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decb,
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sarl,
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addl,
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subl
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subl,
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sall,
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orl,
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orb,
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rep,
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pushl
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};
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static OpCode parse_opcode(Type t, const std::string &o)
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@ -255,10 +326,21 @@ struct i386 : ASMLine
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if (o == "movl") return OpCode::movl;
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if (o == "jmp") return OpCode::jmp;
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if (o == "testb") return OpCode::testb;
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if (o == "incl") return OpCode::incl;
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if (o == "sarl") return OpCode::sarl;
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if (o == "decl") return OpCode::decl;
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if (o == "jne") return OpCode::jne;
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if (o == "je") return OpCode::je;
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if (o == "js") return OpCode::js;
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if (o == "subl") return OpCode::subl;
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if (o == "addl") return OpCode::addl;
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if (o == "sall") return OpCode::sall;
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if (o == "orl") return OpCode::orl;
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if (o == "andb") return OpCode::andb;
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if (o == "orb") return OpCode::orb;
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if (o == "decb") return OpCode::decb;
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if (o == "incb") return OpCode::incb;
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if (o == "rep") return OpCode::rep;
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}
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}
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throw std::runtime_error("Unknown opcode: " + o);
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@ -281,6 +363,10 @@ struct i386 : ASMLine
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return Operand(Operand::Type::reg, 4);
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} else if (o == "%di") {
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return Operand(Operand::Type::reg, 6);
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} else if (o == "%cl" || o == "%ecx") {
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return Operand(Operand::Type::reg, 3);
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} else if (o == "%bl" || o == "%ebx") {
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return Operand(Operand::Type::reg, 2);
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} else {
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throw std::runtime_error("Unknown register operand: '" + o + "'");
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}
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@ -313,55 +399,125 @@ void translate_instruction(std::vector<mos6502> &instructions, const i386::OpCod
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::sty, o2);
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::lda, o1);
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::sty, get_register(o2.reg_num));
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} else if (o1.type == Operand::Type::reg && o1.reg_num == 1 && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num));
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} else if (o1.type == Operand::Type::reg && o1.reg_num == 1 && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::sta, o2);
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} else if (o1.type == Operand::Type::reg && o1.reg_num == 4 && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "$fb"));
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} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::ldy, get_register(o1.reg_num));
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instructions.emplace_back(mos6502::OpCode::sty, o2);
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} else {
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throw std::runtime_error("Cannot translate instruction");
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}
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break;
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case i386::OpCode::movl:
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if (o1.type == Operand::Type::reg && o1.reg_num == 1 && o2.type == Operand::Type::reg && o2.reg_num == 4) {
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instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, "$fb"));
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if (o1.type == Operand::Type::reg && o1.reg_num == 1 && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num));
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} else {
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throw std::runtime_error("Cannot translate instruction");
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}
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break;
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case i386::OpCode::orb:
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case i386::OpCode::orl:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::pha); // transfer memory through A register, pushing and popping around it
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::ORA, o2);
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instructions.emplace_back(mos6502::OpCode::sta, o2);
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instructions.emplace_back(mos6502::OpCode::pla);
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::ORA, Operand(o1.type, fixup_8bit_literal(o1.value)));
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} else {
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throw std::runtime_error("Cannot translate instruction");
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}
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break;
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case i386::OpCode::movzbl:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::lda, o1);
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 4) {
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::ldy, o1);
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instructions.emplace_back(mos6502::OpCode::sty, Operand(Operand::Type::literal, "$fb"));
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instructions.emplace_back(mos6502::OpCode::sty, get_register(o2.reg_num));
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} else {
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throw std::runtime_error("Cannot translate instruction");
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}
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break;
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case i386::OpCode::sarl:
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case i386::OpCode::shrb:
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if (o1.type == Operand::Type::reg && o1.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::lsr, Operand(Operand::Type::literal, "a"));
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} else if (o1.type == Operand::Type::reg && o1.reg_num == 4) {
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instructions.emplace_back(mos6502::OpCode::lsr, Operand(Operand::Type::literal, "$fb"));
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if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) {
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const auto do_shift = [&instructions](const int reg_num) {
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if (reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::lsr, Operand(Operand::Type::literal, "a"));
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} else {
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instructions.emplace_back(mos6502::OpCode::lsr, get_register(reg_num));
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}
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};
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if (o1.type == Operand::Type::literal) {
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const auto count = parse_8bit_literal(o1.value);
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for (int i = 0; i < count; ++i) {
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do_shift(o2.reg_num);
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}
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} else {
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do_shift(o1.reg_num);
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}
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} else {
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throw std::runtime_error("Cannot translate instruction");
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}
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break;
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case i386::OpCode::testb:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::pha);
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instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::cmp, Operand(Operand::Type::literal, "#$0"));
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instructions.emplace_back(mos6502::OpCode::tay);
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instructions.emplace_back(mos6502::OpCode::pla);
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instructions.emplace_back(mos6502::OpCode::cpy, Operand(Operand::Type::literal, "#0"));
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// instructions.emplace_back(mos6502::OpCode::cmp, Operand(Operand::Type::literal, "#$0"));
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} else if (o1.type == Operand::Type::reg && o1.reg_num == 1 && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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//transfer A to Y, to set the status flags appropriately
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instructions.emplace_back(mos6502::OpCode::tay);
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} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) {
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instructions.emplace_back(mos6502::OpCode::ldy, get_register(o1.reg_num));
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} else {
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throw std::runtime_error("Cannot translate instruction");
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}
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break;
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case i386::OpCode::decb:
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case i386::OpCode::decl:
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if (o1.type == Operand::Type::reg && o1.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#1"));
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} else if (o1.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::dec, get_register(o1.reg_num));
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} else {
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instructions.emplace_back(mos6502::OpCode::dec, o1);
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}
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break;
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case i386::OpCode::incb:
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case i386::OpCode::incl:
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if (o1.type == Operand::Type::reg && o1.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::adc, Operand(Operand::Type::literal, "#1"));
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} else if (o1.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::inc, get_register(o1.reg_num));
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} else {
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instructions.emplace_back(mos6502::OpCode::inc, o1);
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}
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break;
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case i386::OpCode::jne:
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instructions.emplace_back(mos6502::OpCode::bne, o1);
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break;
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case i386::OpCode::je:
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instructions.emplace_back(mos6502::OpCode::beq, o1);
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break;
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case i386::OpCode::js:
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instructions.emplace_back(mos6502::OpCode::bmi, o1);
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break;
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case i386::OpCode::jmp:
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instructions.emplace_back(mos6502::OpCode::jmp, o1);
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break;
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@ -370,12 +526,16 @@ void translate_instruction(std::vector<mos6502> &instructions, const i386::OpCod
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instructions.emplace_back(mos6502::OpCode::eor, Operand(o1.type, fixup_8bit_literal(o1.value)));
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} else if (o1.type == Operand::Type::reg && o2.reg_num == 1 && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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// cheater shortcut on x86 to 0 out a register
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "$fb"));
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 4) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#0"));
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} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) {
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// cheater shortcut on x86 to 0 out a register
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instructions.emplace_back(mos6502::OpCode::ldy, Operand(Operand::Type::literal, "#0"));
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instructions.emplace_back(mos6502::OpCode::sty, get_register(o1.reg_num));
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::pha); // transfer memory through A register, pushing and popping around it
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "$fb"));
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instructions.emplace_back(mos6502::OpCode::lda, get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::eor, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, "$fb"));
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instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::pla);
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} else {
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throw std::runtime_error("Cannot translate instruction");
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@ -384,11 +544,11 @@ void translate_instruction(std::vector<mos6502> &instructions, const i386::OpCod
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case i386::OpCode::addl:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
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instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value)));
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 4) {
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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||||
instructions.emplace_back(mos6502::OpCode::pha); // transfer memory through A register, pushing and popping around it
|
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "$fb"));
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||||
instructions.emplace_back(mos6502::OpCode::lda, get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value)));
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||||
instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, "$fb"));
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instructions.emplace_back(mos6502::OpCode::sta, get_register(o2.reg_num));
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||||
instructions.emplace_back(mos6502::OpCode::pla);
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||||
} else {
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throw std::runtime_error("Cannot translate instruction");
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||||
|
|
@ -396,22 +556,29 @@ void translate_instruction(std::vector<mos6502> &instructions, const i386::OpCod
|
|||
break;
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||||
case i386::OpCode::cmpb:
|
||||
if (o1.type == Operand::Type::reg && o1.reg_num == 1 && o2.type == Operand::Type::reg && o2.reg_num == 4) {
|
||||
instructions.emplace_back(mos6502::OpCode::cmp, Operand(Operand::Type::literal, "$fb"));
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||||
instructions.emplace_back(mos6502::OpCode::cmp, get_register(o2.reg_num));
|
||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
|
||||
instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
|
||||
instructions.emplace_back(mos6502::OpCode::ldy, o2);
|
||||
// if (o1.value != "$0") {
|
||||
instructions.emplace_back(mos6502::OpCode::cpy, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
||||
// }
|
||||
} else {
|
||||
throw std::runtime_error("Cannot translate instruction");
|
||||
}
|
||||
break;
|
||||
case i386::OpCode::andb:
|
||||
case i386::OpCode::andl:
|
||||
if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 1) {
|
||||
instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg && o2.reg_num == 4) {
|
||||
instructions.emplace_back(mos6502::OpCode::pha); // transfer memory through A register, pushing and popping around it
|
||||
instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
||||
instructions.emplace_back(mos6502::OpCode::AND, Operand(Operand::Type::literal, "$fb"));
|
||||
instructions.emplace_back(mos6502::OpCode::sta, Operand(Operand::Type::literal, "$fb"));
|
||||
instructions.emplace_back(mos6502::OpCode::pla); // transfer memory through A register, pushing and popping around it
|
||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
|
||||
const auto reg = get_register(o2.reg_num);
|
||||
instructions.emplace_back(mos6502::OpCode::tay); // transfer memory through A register, pushing and popping around it
|
||||
instructions.emplace_back(mos6502::OpCode::lda, reg);
|
||||
instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
||||
instructions.emplace_back(mos6502::OpCode::sta, reg);
|
||||
instructions.emplace_back(mos6502::OpCode::tya); // transfer memory through A register, pushing and popping around it
|
||||
} else {
|
||||
throw std::runtime_error("Cannot translate instruction");
|
||||
}
|
||||
|
|
@ -535,7 +702,8 @@ bool fix_overwritten_flags(std::vector<mos6502> &instructions)
|
|||
|
||||
int main()
|
||||
{
|
||||
std::regex Label(R"(^(\S+):)");
|
||||
std::regex Comment(R"(\s*\#.*)");
|
||||
std::regex Label(R"(^(\S+):.*)");
|
||||
std::regex Directive(R"(^\t(\..+))");
|
||||
std::regex UnaryInstruction(R"(^\t(\S+)\s+(\S+))");
|
||||
std::regex BinaryInstruction(R"(^\t(\S+)\s+(\S+),\s+(\S+))");
|
||||
|
|
@ -555,6 +723,8 @@ int main()
|
|||
if (std::regex_match(line, match, Label))
|
||||
{
|
||||
instructions.emplace_back(lineno, line, ASMLine::Type::Label, match[1]);
|
||||
} else if (std::regex_match(line, match, Comment)) {
|
||||
// don't care about comments
|
||||
} else if (std::regex_match(line, match, Directive)) {
|
||||
instructions.emplace_back(lineno, line, ASMLine::Type::Directive, match[1]);
|
||||
} else if (std::regex_match(line, match, UnaryInstruction)) {
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user