mirror of
https://github.com/lefticus/6502-cpp.git
synced 2024-12-30 07:31:38 +00:00
Completely revamp optimization algorithms for safety and ability
This commit is contained in:
Jason Turner
parent
a1806a4ae2
commit
af0a07b913
@ -24,21 +24,6 @@ static void puts(uint8_t x, uint8_t y, std::string_view str) {
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}
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int main() {
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std::uint8_t x = 0;
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std::uint8_t y = 0;
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while (true) {
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puts(x, y, "hello commodore!");
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x += 3;
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++y;
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if (x > 26) {
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x = 0;
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}
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if (y>25) {
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y = 0;
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}
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}
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puts(15, 10, "hello commodore!");
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}
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@ -20,15 +20,20 @@ struct mos6502 : ASMLine
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bne,
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bpl,
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cpx,
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cpy,
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cmp,
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clc,
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dec,
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dex,
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dey,
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eor,
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inc,
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inx,
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iny,
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jmp,
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jsr,
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@ -79,12 +84,17 @@ struct mos6502 : ASMLine
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case OpCode::AND:
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case OpCode::asl:
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case OpCode::bit:
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case OpCode::cpx:
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case OpCode::cpy:
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case OpCode::cmp:
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case OpCode::clc:
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case OpCode::dec:
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case OpCode::dex:
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case OpCode::eor:
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case OpCode::inc:
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case OpCode::inx:
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case OpCode::iny:
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case OpCode::dey:
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case OpCode::jmp:
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case OpCode::jsr:
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case OpCode::lda:
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@ -124,6 +134,7 @@ struct mos6502 : ASMLine
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case OpCode::bit:
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case OpCode::cmp:
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case OpCode::cpy:
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case OpCode::cpx:
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return true;
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case OpCode::adc:
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case OpCode::AND:
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@ -136,8 +147,12 @@ struct mos6502 : ASMLine
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case OpCode::bcs:
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case OpCode::clc:
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case OpCode::dec:
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case OpCode::dex:
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case OpCode::eor:
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case OpCode::inc:
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case OpCode::inx:
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case OpCode::iny:
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case OpCode::dey:
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case OpCode::jmp:
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case OpCode::jsr:
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case OpCode::lda:
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@ -231,6 +246,11 @@ struct mos6502 : ASMLine
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case OpCode::bcc: return "bcc";
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case OpCode::bcs: return "bcs";
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case OpCode::nop: return "nop";
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case OpCode::inx: return "inx";
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case OpCode::dex: return "dex";
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case OpCode::cpx: return "cpx";
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case OpCode::dey: return "dey";
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case OpCode::iny: return "iny";
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case OpCode::unknown: return "";
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}
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@ -3,21 +3,255 @@
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#include "6502.hpp"
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#include "personality.hpp"
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#include <span>
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#include <vector>
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bool optimize(std::vector<mos6502> &instructions, const Personality &personality)
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constexpr bool consume_directives(auto &begin, const auto &end)
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{
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// return false;
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if (begin != end && begin->type == ASMLine::Type::Directive) {
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++begin;
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return true;
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}
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return false;
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}
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if (instructions.size() < 2) { return false; }
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const auto next_instruction = [&instructions](auto i) {
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do {
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++i;
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} while (i < instructions.size() && instructions[i].type == ASMLine::Type::Directive);
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return i;
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constexpr bool consume_labels(auto &begin, const auto &end)
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{
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if (begin != end && begin->type == ASMLine::Type::Label) {
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++begin;
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return true;
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}
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return false;
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}
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constexpr bool is_opcode(const mos6502 &op, const auto... opcodes) { return ((op.opcode == opcodes) || ...); }
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constexpr bool is_end_of_block(const auto &begin)
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{
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if (begin->type == ASMLine::Type::Label) { return true; }
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return is_opcode(*begin,
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mos6502::OpCode::jsr,
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mos6502::OpCode::jmp,
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mos6502::OpCode::bcc,
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mos6502::OpCode::bcs,
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mos6502::OpCode::beq,
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mos6502::OpCode::bne,
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mos6502::OpCode::bpl);
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}
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constexpr bool consume_end_of_block(auto &begin, const auto &end)
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{
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if (begin != end && is_end_of_block(begin)) {
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++begin;
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return true;
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}
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return false;
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}
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static std::vector<std::span<mos6502>> get_optimizable_blocks(std::vector<mos6502> &statements)
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{
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std::vector<std::span<mos6502>> blocks;
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auto begin = std::begin(statements);
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auto end = std::end(statements);
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const auto find_end_of_block = [](auto &find_begin, const auto &find_end) {
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while (find_begin != find_end) {
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if (is_end_of_block(find_begin)) { return; }
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++find_begin;
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}
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};
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while (begin != end) {
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while (consume_end_of_block(begin, end) || consume_directives(begin, end) || consume_labels(begin, end)) {}
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const auto block_start = begin;
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find_end_of_block(begin, end);
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blocks.emplace_back(block_start, begin);
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}
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return blocks;
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}
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static bool is_virtual_register_op(const mos6502 &op, const Personality &personality)
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{
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for (int i = 0; i < 32; ++i) {
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if (personality.get_register(i).value == op.op.value) { return true; }
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}
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return false;
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}
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static bool optimize_dead_tax(std::span<mos6502> &block)
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{
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for (auto itr = block.begin(); itr != block.end(); ++itr) {
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if (is_opcode(*itr, mos6502::OpCode::tax, mos6502::OpCode::tsx, mos6502::OpCode::ldx)) {
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for (auto inner = std::next(itr); inner != block.end(); ++inner) {
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if (is_opcode(*inner,
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mos6502::OpCode::txa,
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mos6502::OpCode::txs,
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mos6502::OpCode::stx,
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mos6502::OpCode::inx,
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mos6502::OpCode::dex,
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mos6502::OpCode::cpx)) {
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break;
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}
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if (is_opcode(*inner, mos6502::OpCode::tax, mos6502::OpCode::tsx, mos6502::OpCode::ldx)) {
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// redundant store found
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*itr = mos6502(ASMLine::Type::Directive, "; removed dead load of X: " + itr->to_string());
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return true;
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}
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}
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}
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}
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return false;
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}
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bool optimize_dead_sta(std::span<mos6502> &block, const Personality &personality)
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{
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for (auto itr = block.begin(); itr != block.end(); ++itr) {
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if (itr->opcode == mos6502::OpCode::sta && is_virtual_register_op(*itr, personality)) {
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for (auto inner = std::next(itr); inner != block.end(); ++inner) {
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if (inner->op.value.find('(') != std::string::npos) {
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// this is an indexed operation, which is risky to optimize a sta around on the virtual registers,
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// so we'll skip this block
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break;
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}
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if (inner->op.value == itr->op.value) {
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if (is_opcode(*inner, mos6502::OpCode::sta)) {
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// redundant store found
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*itr = mos6502(ASMLine::Type::Directive, "; removed dead store of a: " + itr->to_string());
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return true;
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} else {
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// someone else is operating on us, time to abort
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break;
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}
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}
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}
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}
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}
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return false;
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}
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bool optimize_redundant_ldy(std::span<mos6502> &block)
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{
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for (auto itr = block.begin(); itr != block.end(); ++itr) {
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if (itr->opcode == mos6502::OpCode::ldy && itr->op.value.starts_with('#')) {
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for (auto inner = std::next(itr); inner != block.end(); ++inner) {
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if (is_opcode(*inner,
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mos6502::OpCode::cpy,
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mos6502::OpCode::tya,
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mos6502::OpCode::tay,
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mos6502::OpCode::sty,
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mos6502::OpCode::iny,
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mos6502::OpCode::dey)) {
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break;// break, these all operate on Y
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}
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// we found a matching ldy
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if (is_opcode(*inner, mos6502::OpCode::ldy)) {
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// with the same value
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// note: this operation is only safe because we know that our system only uses Y
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// for index operations and we don't rely (or even necessarily *want* the changes to N,Z)
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if (inner->op.value == itr->op.value) {
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*inner = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + inner->to_string());
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return true;
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} else {
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break;
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}
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}
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}
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}
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}
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return false;
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}
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bool optimize_redundant_lda(std::span<mos6502> &block, const Personality &personality)
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{
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// look for a literal or virtual register load into A
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// that is redundant later
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for (auto itr = block.begin(); itr != block.end(); ++itr) {
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if (itr->opcode == mos6502::OpCode::lda &&
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(itr->op.value.starts_with('#')
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|| is_virtual_register_op(*itr, personality))) {
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for (auto inner = std::next(itr); inner != block.end(); ++inner) {
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if (is_opcode(*inner,
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mos6502::OpCode::tay,
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mos6502::OpCode::tax,
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mos6502::OpCode::sta,
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mos6502::OpCode::pha,
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mos6502::OpCode::nop)) {
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continue;// OK to skip instructions that don't modify A or change flags
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}
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if (inner->type == ASMLine::Type::Directive) {
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continue;// OK to skip directives
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}
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if (is_opcode(*inner, mos6502::OpCode::lda)) {
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if (inner->op == itr->op) {
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// we found a matching lda, after an sta, we can remove it
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*inner = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + inner->to_string());
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return true;
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} else {
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break;
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}
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}
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break;// we can only optimize around tax and comments right now
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}
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}
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}
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return false;
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}
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bool optimize_redundant_lda_after_sta(std::span<mos6502> &block)
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{
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for (auto itr = block.begin(); itr != block.end(); ++itr) {
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if (itr->opcode == mos6502::OpCode::sta) {
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for (auto inner = std::next(itr); inner != block.end(); ++inner) {
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if (is_opcode(*inner,
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mos6502::OpCode::tax,
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mos6502::OpCode::tay,
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mos6502::OpCode::clc,
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mos6502::OpCode::sec,
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mos6502::OpCode::sta,
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mos6502::OpCode::pha,
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mos6502::OpCode::txs,
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mos6502::OpCode::php,
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mos6502::OpCode::sty,
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mos6502::OpCode::nop)) {
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continue;// OK to skip instructions that don't modify A or change flags
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}
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if (inner->type == ASMLine::Type::Directive) {
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continue;// OK to skip directives
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}
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if (is_opcode(*inner, mos6502::OpCode::lda)) {
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if (inner->op == itr->op) {
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// we found a matching lda, after a sta, we can remove it
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*inner = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + inner->to_string());
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return true;
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} else {
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break;
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}
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}
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break;// we can only optimize around tax and comments right now
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}
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}
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}
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return false;
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}
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bool optimize(std::vector<mos6502> &instructions, [[maybe_unused]] const Personality &personality)
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{
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// remove unused flag-fix-up blocks
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// it might make sense in the future to only insert these if determined they are needed?
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@ -37,153 +271,24 @@ bool optimize(std::vector<mos6502> &instructions, const Personality &personality
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}
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}
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// look for redundant load of lda after a tax
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for (size_t op = 0; op < instructions.size() - 3; ++op) {
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if (instructions[op].opcode == mos6502::OpCode::sta && instructions[op + 1].opcode == mos6502::OpCode::tax
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&& instructions[op + 2].opcode == mos6502::OpCode::lda
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&& instructions[op].op.value == instructions[op + 2].op.value) {
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instructions[op + 2] =
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mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string());
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return true;
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}
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}
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// look for redundant stores to 0-page registers with sta
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for (size_t op = 0; op < instructions.size(); ++op) {
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// todo, make sure this is in the register map
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if (instructions[op].opcode == mos6502::OpCode::sta && instructions[op].op.value.size() == 3) {
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for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) {
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if (instructions[next_op].opcode != mos6502::OpCode::sta
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&& instructions[next_op].op.value == instructions[op].op.value) {
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// we just found a use of ourselves back, abort the search, there's probably something else going on
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break;
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}
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if (instructions[next_op].opcode == mos6502::OpCode::lda
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&& instructions[next_op].op.value != instructions[op].op.value) {
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// someone just loaded lda with a different value, so we need to abort!
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break;
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}
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// abort at pla
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if (instructions[next_op].opcode == mos6502::OpCode::pla) { break; }
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// abort at jsr
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if (instructions[next_op].opcode == mos6502::OpCode::jsr) { break; }
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// abort at label
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if (instructions[next_op].type == ASMLine::Type::Label) { break; }
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if (instructions[next_op].opcode == mos6502::OpCode::sta
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&& instructions[next_op].op.value == instructions[op].op.value) {
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// looks like we found a redundant store, remove the first one
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instructions[op] =
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mos6502(ASMLine::Type::Directive, "; removed redundant sta: " + instructions[op].to_string());
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return true;
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}
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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// look for a transfer of A -> X immediately followed by LDX
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if (instructions[op].opcode == mos6502::OpCode::sta) {
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const auto next_op = next_instruction(op);
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if (instructions[next_op].opcode == mos6502::OpCode::ldx && instructions[op].op == instructions[next_op].op) {
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auto last_comment = instructions[next_op].comment;
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instructions[next_op] = mos6502(mos6502::OpCode::tax);
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instructions[next_op].comment = last_comment;
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return true;
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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// look for a transfer of A -> X immediately followed by LDX
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if (instructions[op].opcode == mos6502::OpCode::tax) {
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const auto next_op = next_instruction(op);
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if (instructions[next_op].opcode == mos6502::OpCode::ldx) {
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instructions[op] =
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mos6502(ASMLine::Type::Directive, "; removed redundant tax: " + instructions[op].to_string());
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return true;
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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// look for a transfer of Y -> A immediately followed by A -> Y
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if (instructions[op].opcode == mos6502::OpCode::tya) {
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const auto next_op = next_instruction(op);
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if (instructions[next_op].opcode == mos6502::OpCode::tay) {
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instructions[op] =
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mos6502(ASMLine::Type::Directive, "; removed redundant tay: " + instructions[op].to_string());
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return true;
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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// look for a store A -> loc immediately followed by loc -> A
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if (instructions[op].opcode == mos6502::OpCode::sta) {
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const auto next = next_instruction(op);
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if (instructions[next].opcode == mos6502::OpCode::lda && instructions[next].op == instructions[op].op) {
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instructions[next] =
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mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[next].to_string());
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return true;
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}
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}
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}
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// replace use of __zero_reg__ with literal 0
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for (auto &op : instructions) {
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if (op.type == ASMLine::Type::Instruction && op.op.type == Operand::Type::literal
|
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&& op.op.value == personality.get_register(1).value && op.opcode != mos6502::OpCode::sta) {
|
||||
// replace use of zero reg with literal 0
|
||||
const auto old_string = op.to_string();
|
||||
op.op.value = "#0";
|
||||
op.comment = "replaced use of register 1 with a literal 0, because of AVR GCC __zero_reg__ ; " + old_string;
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||
if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) {
|
||||
auto op2 = op + 1;
|
||||
bool block_optimized = false;
|
||||
for (auto &block : get_optimizable_blocks(instructions)) {
|
||||
block_optimized = block_optimized || optimize_redundant_lda_after_sta(block) || optimize_dead_sta(block, personality) || optimize_dead_tax(block)
|
||||
|| optimize_redundant_ldy(block) || optimize_redundant_lda(block, personality);
|
||||
|
||||
while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)
|
||||
&& (instructions[op2].opcode == mos6502::OpCode::jsr)) {
|
||||
// while inside this label
|
||||
if (instructions[op2].opcode == mos6502::OpCode::ldy) {
|
||||
|
||||
if (instructions[op2].op.value == instructions[op].op.value) {
|
||||
instructions[op2] =
|
||||
mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string());
|
||||
return true;
|
||||
} else {
|
||||
// if we ldy with any other value in this block then abort
|
||||
break;
|
||||
}
|
||||
}
|
||||
++op2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||
if (instructions[op].opcode == mos6502::OpCode::lda && instructions[op].op.type == Operand::Type::literal) {
|
||||
const auto operand = instructions[op].op;
|
||||
auto op2 = op + 1;
|
||||
// look for multiple stores of the same value
|
||||
while (
|
||||
op2 < instructions.size()
|
||||
&& (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) {
|
||||
++op2;
|
||||
}
|
||||
if (instructions[op2].opcode == mos6502::OpCode::lda && operand == instructions[op2].op) {
|
||||
instructions[op2] =
|
||||
mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op2].to_string());
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
return block_optimized;
|
||||
}
|
||||
|
||||
#endif// INC_6502_CPP_OPTIMIZER_HPP
|
||||
|
||||
Loading…
Reference in New Issue
Block a user