mirror of
https://github.com/lefticus/6502-cpp.git
synced 2024-12-25 21:29:23 +00:00
Some code organization and splitting up
This commit is contained in:
Jason Turner
parent
afcbe05bff
commit
e6040763eb
@ -1,6 +1,6 @@
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---
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Checks: '*,-fuchsia-*,-google-*,-zircon-*,-abseil-*,-modernize-use-trailing-return-type,-llvm*,-altera*,-misc-non-private-member-variables-in-classes,-readability-else-after-return'
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WarningsAsErrors: '*'
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WarningsAsErrors: ''
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HeaderFilterRegex: ''
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FormatStyle: none
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240
include/6502.hpp
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240
include/6502.hpp
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@ -0,0 +1,240 @@
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#ifndef INC_6502_CPP_6502_HPP
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#define INC_6502_CPP_6502_HPP
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#include "assembly.hpp"
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struct mos6502 : ASMLine
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{
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enum class OpCode {
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unknown,
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adc,
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AND,
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asl,
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bcc,
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bcs,
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beq,
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bit,
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bmi,
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bne,
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bpl,
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cpy,
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cmp,
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clc,
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dec,
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eor,
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inc,
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jmp,
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jsr,
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lda,
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ldy,
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lsr,
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ORA,
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pha,
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php,
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pla,
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plp,
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rol,
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ror,
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rts,
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sbc,
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sec,
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sta,
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sty,
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tax,
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tay,
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txa,
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tya,
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};
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static bool get_is_branch(const OpCode o)
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{
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switch (o) {
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case OpCode::beq:
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case OpCode::bne:
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case OpCode::bmi:
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case OpCode::bpl:
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case OpCode::bcc:
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case OpCode::bcs:
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return true;
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case OpCode::adc:
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case OpCode::AND:
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case OpCode::asl:
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case OpCode::bit:
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case OpCode::cpy:
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case OpCode::cmp:
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case OpCode::clc:
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case OpCode::dec:
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case OpCode::eor:
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case OpCode::inc:
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case OpCode::jmp:
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case OpCode::jsr:
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case OpCode::lda:
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case OpCode::ldy:
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case OpCode::lsr:
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case OpCode::ORA:
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case OpCode::pha:
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case OpCode::php:
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case OpCode::pla:
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case OpCode::plp:
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case OpCode::rol:
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case OpCode::ror:
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case OpCode::rts:
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case OpCode::sbc:
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case OpCode::sec:
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case OpCode::sta:
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case OpCode::sty:
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case OpCode::tax:
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case OpCode::tay:
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case OpCode::txa:
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case OpCode::tya:
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case OpCode::unknown:
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break;
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}
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return false;
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}
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static bool get_is_comparison(const OpCode o)
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{
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switch (o) {
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case OpCode::bit:
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case OpCode::cmp:
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case OpCode::cpy:
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return true;
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case OpCode::adc:
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case OpCode::AND:
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case OpCode::asl:
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case OpCode::beq:
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case OpCode::bne:
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case OpCode::bmi:
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case OpCode::bpl:
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case OpCode::bcc:
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case OpCode::bcs:
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case OpCode::clc:
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case OpCode::dec:
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case OpCode::eor:
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case OpCode::inc:
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case OpCode::jmp:
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case OpCode::jsr:
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case OpCode::lda:
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case OpCode::ldy:
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case OpCode::lsr:
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case OpCode::ORA:
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case OpCode::pha:
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case OpCode::php:
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case OpCode::pla:
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case OpCode::plp:
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case OpCode::rol:
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case OpCode::ror:
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case OpCode::rts:
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case OpCode::sbc:
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case OpCode::sec:
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case OpCode::sta:
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case OpCode::sty:
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case OpCode::tax:
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case OpCode::tay:
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case OpCode::txa:
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case OpCode::tya:
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case OpCode::unknown:
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break;
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}
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return false;
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}
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explicit mos6502(const OpCode o)
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: ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o))
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{
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}
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mos6502(const Type t, std::string s)
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: ASMLine(t, std::move(s))
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{
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}
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mos6502(const OpCode o, Operand t_o)
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: ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), op(std::move(t_o)), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o))
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{
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}
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constexpr static std::string_view to_string(const OpCode o)
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{
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switch (o) {
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case OpCode::lda: return "lda";
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case OpCode::asl: return "asl";
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case OpCode::rol: return "rol";
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case OpCode::ldy: return "ldy";
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case OpCode::tay: return "tay";
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case OpCode::tya: return "tya";
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case OpCode::tax: return "tax";
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case OpCode::txa: return "txa";
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case OpCode::cpy: return "cpy";
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case OpCode::eor: return "eor";
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case OpCode::sta: return "sta";
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case OpCode::sty: return "sty";
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case OpCode::pha: return "pha";
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case OpCode::pla: return "pla";
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case OpCode::php: return "php";
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case OpCode::plp: return "plp";
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case OpCode::lsr: return "lsr";
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case OpCode::ror: return "ror";
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case OpCode::AND: return "and";
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case OpCode::inc: return "inc";
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case OpCode::dec: return "dec";
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case OpCode::ORA: return "ora";
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case OpCode::cmp: return "cmp";
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case OpCode::bne: return "bne";
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case OpCode::bmi: return "bmi";
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case OpCode::beq: return "beq";
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case OpCode::jmp: return "jmp";
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case OpCode::adc: return "adc";
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case OpCode::sbc: return "sbc";
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case OpCode::rts: return "rts";
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case OpCode::clc: return "clc";
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case OpCode::sec: return "sec";
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case OpCode::bit: return "bit";
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case OpCode::jsr: return "jsr";
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case OpCode::bpl: return "bpl";
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case OpCode::bcc: return "bcc";
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case OpCode::bcs: return "bcs";
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case OpCode::unknown: return "";
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}
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return "";
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}
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[[nodiscard]] std::string to_string() const
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{
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switch (type) {
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case ASMLine::Type::Label:
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return text;// + ':';
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case ASMLine::Type::Directive:
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case ASMLine::Type::Instruction: {
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return fmt::format("\t{} {:15}; {}", text, op.value, comment);
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}
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}
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throw std::runtime_error("Unable to render: " + text);
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}
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OpCode opcode = OpCode::unknown;
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Operand op;
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std::string comment;
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bool is_branch = false;
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bool is_comparison = false;
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};
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#endif//INC_6502_CPP_6502_HPP
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51
include/assembly.hpp
Normal file
51
include/assembly.hpp
Normal file
@ -0,0 +1,51 @@
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#ifndef INC_6502_CPP_ASSEMBLY_HPP
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#define INC_6502_CPP_ASSEMBLY_HPP
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struct Operand
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{
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enum class Type {
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empty,
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literal,
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reg /*ister*/
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};
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Type type = Type::empty;
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int reg_num = 0;
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std::string value;
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Operand() = default;
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bool operator==(const Operand &other) const
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{
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return type == other.type && reg_num == other.reg_num && value == other.value;
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}
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Operand(const Type t, std::string v)
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: type(t), value(std::move(v))
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{
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assert(type == Type::literal);
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}
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Operand(const Type t, const int num)
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: type(t), reg_num(num)
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{
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assert(type == Type::reg);
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}
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};
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struct ASMLine
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{
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enum class Type {
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Label,
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Instruction,
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Directive
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};
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ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {}
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Type type;
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std::string text;
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};
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#endif//INC_6502_CPP_ASSEMBLY_HPP
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142
include/optimizer.hpp
Normal file
142
include/optimizer.hpp
Normal file
@ -0,0 +1,142 @@
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#ifndef INC_6502_CPP_OPTIMIZER_HPP
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#define INC_6502_CPP_OPTIMIZER_HPP
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#include "6502.hpp"
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#include <vector>
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bool optimize(std::vector<mos6502> &instructions)
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{
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if (instructions.size() < 2) {
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return false;
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}
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const auto next_instruction = [&instructions](auto i) {
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do {
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++i;
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} while (i < instructions.size() && instructions[i].type == ASMLine::Type::Directive);
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return i;
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};
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// remove unused flag-fix-up blocks
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// it might make sense in the future to only insert these if determined they are needed?
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for (size_t op = 10; op < instructions.size(); ++op) {
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if (instructions[op].opcode == mos6502::OpCode::lda) {
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if (instructions[op - 1].text == "; END remove if next is lda") {
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for (size_t inner_op = op - 1; inner_op > 1; --inner_op) {
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instructions[inner_op] = mos6502(ASMLine::Type::Directive,
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"; removed unused flag fix-up: " + instructions[inner_op].to_string());
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if (instructions[inner_op].text.find("; BEGIN") != std::string::npos) {
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return true;
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}
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}
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}
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}
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}
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// look for redundant load of lda after a tax
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for (size_t op = 0; op < instructions.size() - 3; ++op) {
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if (instructions[op].opcode == mos6502::OpCode::sta
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&& instructions[op + 1].opcode == mos6502::OpCode::tax
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&& instructions[op + 2].opcode == mos6502::OpCode::lda
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&& instructions[op].op.value == instructions[op + 2].op.value) {
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instructions[op + 2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string());
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return true;
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}
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}
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// look for redundant stores to 0-page registers with sta
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for (size_t op = 0; op < instructions.size(); ++op) {
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// todo, make sure this is in the register map
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if (instructions[op].opcode == mos6502::OpCode::sta
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&& instructions[op].op.value.size() == 3) {
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for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) {
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if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) {
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// we just found a use of ourselves back, abort the search, there's probably something else going on
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break;
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}
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if (instructions[next_op].opcode == mos6502::OpCode::lda && instructions[next_op].op.value != instructions[op].op.value) {
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// someone just loaded lda with a different value, so we need to abort!
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break;
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}
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// abort at label
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if (instructions[next_op].type == ASMLine::Type::Label) {
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break;
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}
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if (instructions[next_op].opcode == mos6502::OpCode::sta
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&& instructions[next_op].op.value == instructions[op].op.value) {
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// looks like we found a redundant store, remove the first one
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instructions[op] = mos6502(ASMLine::Type::Directive,
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"; removed redundant sta: " + instructions[op].to_string());
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return true;
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}
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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// look for a transfer of Y -> A immediately followed by A -> Y
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if (instructions[op].opcode == mos6502::OpCode::tya) {
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next_instruction(op);
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if (instructions[op].opcode == mos6502::OpCode::tay) {
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instructions[op] = mos6502(ASMLine::Type::Directive,
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"; removed redundant tay: " + instructions[op].to_string());
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return true;
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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// look for a store A -> loc immediately followed by loc -> A
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if (instructions[op].opcode == mos6502::OpCode::sta) {
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const auto next = next_instruction(op);
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if (instructions[next].opcode == mos6502::OpCode::lda
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&& instructions[next].op == instructions[op].op) {
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instructions[next] = mos6502(ASMLine::Type::Directive,
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"; removed redundant lda: " + instructions[next].to_string());
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return true;
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) {
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auto op2 = op + 1;
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while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)) {
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// while inside this label
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if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == instructions[op].op.value) {
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instructions[op2] = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string());
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return true;
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}
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++op2;
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}
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}
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}
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for (size_t op = 0; op < instructions.size() - 1; ++op) {
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if (instructions[op].opcode == mos6502::OpCode::lda
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&& instructions[op].op.type == Operand::Type::literal) {
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const auto operand = instructions[op].op;
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auto op2 = op + 1;
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// look for multiple stores of the same value
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while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) {
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++op2;
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}
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if (instructions[op2].opcode == mos6502::OpCode::lda
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&& operand == instructions[op2].op) {
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instructions[op2] = mos6502(ASMLine::Type::Directive,
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"; removed redundant lda: " + instructions[op2].to_string());
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return true;
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}
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}
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}
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return false;
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}
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#endif//INC_6502_CPP_OPTIMIZER_HPP
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93
include/personalities/c64.hpp
Normal file
93
include/personalities/c64.hpp
Normal file
@ -0,0 +1,93 @@
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#ifndef INC_6502_C_C64_HPP
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#define INC_6502_C_C64_HPP
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#include "../personality.hpp"
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struct C64 : Personality
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{
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void insert_autostart_sequence(std::vector<mos6502> &new_instructions) const override
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{
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constexpr static auto start_address = 0x0801;
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// first 2 bytes is the load address for a PRG file.
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new_instructions.emplace_back(ASMLine::Type::Directive, ".word " + std::to_string(start_address));
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new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address));
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new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC");
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new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00");
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}
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[[nodiscard]] Operand get_register(const int reg_num) const override
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{
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switch (reg_num) {
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// http://sta.c64.org/cbm64mem.html
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case 0:
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return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232
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case 1:
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return Operand(Operand::Type::literal, "$a8");// counter for rs232
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case 2:
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return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer
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case 3:
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return Operand(Operand::Type::literal, "$06");
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case 4:
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return Operand(Operand::Type::literal, "$fb");// unused
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case 5:
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return Operand(Operand::Type::literal, "$fc");// unused
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case 6:
|
||||
return Operand(Operand::Type::literal, "$fd");// unused
|
||||
case 7:
|
||||
return Operand(Operand::Type::literal, "$fe");// unused
|
||||
case 8:
|
||||
return Operand(Operand::Type::literal, "$22");// unused
|
||||
case 9:
|
||||
return Operand(Operand::Type::literal, "$23");// unused
|
||||
case 10:
|
||||
return Operand(Operand::Type::literal, "$39");// Current BASIC line number
|
||||
case 11:
|
||||
return Operand(Operand::Type::literal, "$3a");// Current BASIC line number
|
||||
case 12:
|
||||
return Operand(Operand::Type::literal, "$61");// arithmetic register #1
|
||||
case 13:
|
||||
return Operand(Operand::Type::literal, "$62");
|
||||
case 14:
|
||||
return Operand(Operand::Type::literal, "$63");
|
||||
case 15:
|
||||
return Operand(Operand::Type::literal, "$64");
|
||||
case 16:
|
||||
return Operand(Operand::Type::literal, "$65");
|
||||
case 17:
|
||||
return Operand(Operand::Type::literal, "$69");// arithmetic register #2
|
||||
case 18:
|
||||
return Operand(Operand::Type::literal, "$6a");
|
||||
case 19:
|
||||
return Operand(Operand::Type::literal, "$6b");
|
||||
case 20:
|
||||
return Operand(Operand::Type::literal, "$6c");
|
||||
case 21:
|
||||
return Operand(Operand::Type::literal, "$6d");
|
||||
case 22:
|
||||
return Operand(Operand::Type::literal, "$57");// arithmetic register #3
|
||||
case 23:
|
||||
return Operand(Operand::Type::literal, "$58");
|
||||
case 24:
|
||||
return Operand(Operand::Type::literal, "$59");
|
||||
case 25:
|
||||
return Operand(Operand::Type::literal, "$5a");
|
||||
case 26:
|
||||
return Operand(Operand::Type::literal, "$5b");
|
||||
case 27:
|
||||
return Operand(Operand::Type::literal, "$5c");// arithmetic register #4
|
||||
case 28:
|
||||
return Operand(Operand::Type::literal, "$5d");
|
||||
case 29:
|
||||
return Operand(Operand::Type::literal, "$5e");
|
||||
case 30:
|
||||
return Operand(Operand::Type::literal, "$5f");
|
||||
case 31:
|
||||
return Operand(Operand::Type::literal, "$60");
|
||||
}
|
||||
throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num));
|
||||
}
|
||||
};
|
||||
|
||||
#endif//INC_6502_C_C64_HPP
|
||||
23
include/personality.hpp
Normal file
23
include/personality.hpp
Normal file
@ -0,0 +1,23 @@
|
||||
#ifndef INC_6502_CPP_PERSONALITY_HPP
|
||||
#define INC_6502_CPP_PERSONALITY_HPP
|
||||
|
||||
#include <vector>
|
||||
#include "6502.hpp"
|
||||
|
||||
class Personality
|
||||
{
|
||||
public:
|
||||
virtual void insert_autostart_sequence(std::vector<mos6502> &new_instructions) const = 0;
|
||||
[[nodiscard]] virtual Operand get_register(const int reg_num) const = 0;
|
||||
|
||||
virtual ~Personality() = default;
|
||||
Personality(const Personality &) = delete;
|
||||
Personality(Personality &&) = delete;
|
||||
Personality &operator=(const Personality &) = delete;
|
||||
Personality &operator=(Personality &&) = delete;
|
||||
|
||||
protected:
|
||||
Personality() = default;
|
||||
};
|
||||
|
||||
#endif//INC_6502_CPP_PERSONALITY_HPP
|
||||
527
src/6502-c++.cpp
527
src/6502-c++.cpp
@ -10,151 +10,10 @@
|
||||
#include <string>
|
||||
#include <vector>
|
||||
|
||||
struct Operand
|
||||
{
|
||||
enum class Type {
|
||||
empty,
|
||||
literal,
|
||||
reg /*ister*/
|
||||
};
|
||||
|
||||
Type type = Type::empty;
|
||||
int reg_num = 0;
|
||||
std::string value;
|
||||
|
||||
Operand() = default;
|
||||
|
||||
bool operator==(const Operand &other) const
|
||||
{
|
||||
return type == other.type && reg_num == other.reg_num && value == other.value;
|
||||
}
|
||||
|
||||
Operand(const Type t, std::string v)
|
||||
: type(t), value(std::move(v))
|
||||
{
|
||||
assert(type == Type::literal);
|
||||
}
|
||||
|
||||
Operand(const Type t, const int num)
|
||||
: type(t), reg_num(num)
|
||||
{
|
||||
assert(type == Type::reg);
|
||||
}
|
||||
};
|
||||
|
||||
struct mos6502;
|
||||
|
||||
class Personality
|
||||
{
|
||||
public:
|
||||
virtual void insert_autostart_sequence(std::vector<mos6502> &new_instructions) const = 0;
|
||||
[[nodiscard]] virtual Operand get_register(const int reg_num) const = 0;
|
||||
|
||||
virtual ~Personality() = default;
|
||||
Personality(const Personality &) = delete;
|
||||
Personality(Personality &&) = delete;
|
||||
Personality &operator=(const Personality &) = delete;
|
||||
Personality &operator=(Personality &&) = delete;
|
||||
|
||||
protected:
|
||||
Personality() = default;
|
||||
};
|
||||
|
||||
struct ASMLine
|
||||
{
|
||||
enum class Type {
|
||||
Label,
|
||||
Instruction,
|
||||
Directive
|
||||
};
|
||||
|
||||
ASMLine(Type t, std::string te) : type(t), text(std::move(te)) {}
|
||||
|
||||
Type type;
|
||||
std::string text;
|
||||
};
|
||||
|
||||
struct C64 : Personality
|
||||
{
|
||||
|
||||
void insert_autostart_sequence(std::vector<mos6502> &new_instructions) const override {
|
||||
new_instructions.emplace_back(ASMLine::Type::Directive, "; jmp to start of program with BASIC");
|
||||
new_instructions.emplace_back(ASMLine::Type::Directive, ".byt $0B,$08,$0A,$00,$9E,$32,$30,$36,$31,$00,$00,$00");
|
||||
}
|
||||
|
||||
[[nodiscard]] Operand get_register(const int reg_num) const override
|
||||
{
|
||||
switch (reg_num) {
|
||||
// http://sta.c64.org/cbm64mem.html
|
||||
case 0:
|
||||
return Operand(Operand::Type::literal, "$a7");// bit buffer for rs232
|
||||
case 1:
|
||||
return Operand(Operand::Type::literal, "$a8");// counter for rs232
|
||||
case 2:
|
||||
return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer
|
||||
case 3:
|
||||
return Operand(Operand::Type::literal, "$06");
|
||||
case 4:
|
||||
return Operand(Operand::Type::literal, "$fb");// unused
|
||||
case 5:
|
||||
return Operand(Operand::Type::literal, "$fc");// unused
|
||||
case 6:
|
||||
return Operand(Operand::Type::literal, "$fd");// unused
|
||||
case 7:
|
||||
return Operand(Operand::Type::literal, "$fe");// unused
|
||||
case 8:
|
||||
return Operand(Operand::Type::literal, "$22");// unused
|
||||
case 9:
|
||||
return Operand(Operand::Type::literal, "$23");// unused
|
||||
case 10:
|
||||
return Operand(Operand::Type::literal, "$39");// Current BASIC line number
|
||||
case 11:
|
||||
return Operand(Operand::Type::literal, "$3a");// Current BASIC line number
|
||||
case 12:
|
||||
return Operand(Operand::Type::literal, "$61");// arithmetic register #1
|
||||
case 13:
|
||||
return Operand(Operand::Type::literal, "$62");
|
||||
case 14:
|
||||
return Operand(Operand::Type::literal, "$63");
|
||||
case 15:
|
||||
return Operand(Operand::Type::literal, "$64");
|
||||
case 16:
|
||||
return Operand(Operand::Type::literal, "$65");
|
||||
case 17:
|
||||
return Operand(Operand::Type::literal, "$69");// arithmetic register #2
|
||||
case 18:
|
||||
return Operand(Operand::Type::literal, "$6a");
|
||||
case 19:
|
||||
return Operand(Operand::Type::literal, "$6b");
|
||||
case 20:
|
||||
return Operand(Operand::Type::literal, "$6c");
|
||||
case 21:
|
||||
return Operand(Operand::Type::literal, "$6d");
|
||||
case 22:
|
||||
return Operand(Operand::Type::literal, "$57");// arithmetic register #3
|
||||
case 23:
|
||||
return Operand(Operand::Type::literal, "$58");
|
||||
case 24:
|
||||
return Operand(Operand::Type::literal, "$59");
|
||||
case 25:
|
||||
return Operand(Operand::Type::literal, "$5a");
|
||||
case 26:
|
||||
return Operand(Operand::Type::literal, "$5b");
|
||||
case 27:
|
||||
return Operand(Operand::Type::literal, "$5c");// arithmetic register #4
|
||||
case 28:
|
||||
return Operand(Operand::Type::literal, "$5d");
|
||||
case 29:
|
||||
return Operand(Operand::Type::literal, "$5e");
|
||||
case 30:
|
||||
return Operand(Operand::Type::literal, "$5f");
|
||||
case 31:
|
||||
return Operand(Operand::Type::literal, "$60");
|
||||
}
|
||||
throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num));
|
||||
}
|
||||
};
|
||||
|
||||
#include "../include/assembly.hpp"
|
||||
#include "../include/6502.hpp"
|
||||
#include "../include/optimizer.hpp"
|
||||
#include "../include/personalities/c64.hpp"
|
||||
|
||||
int parse_8bit_literal(const std::string &s)
|
||||
{
|
||||
@ -200,240 +59,6 @@ std::string fixup_8bit_literal(const std::string &s)
|
||||
}
|
||||
|
||||
|
||||
struct mos6502 : ASMLine
|
||||
{
|
||||
enum class OpCode {
|
||||
unknown,
|
||||
|
||||
adc,
|
||||
AND,
|
||||
asl,
|
||||
|
||||
bcc,
|
||||
bcs,
|
||||
beq,
|
||||
bit,
|
||||
bmi,
|
||||
bne,
|
||||
bpl,
|
||||
|
||||
cpy,
|
||||
cmp,
|
||||
clc,
|
||||
|
||||
dec,
|
||||
|
||||
eor,
|
||||
|
||||
inc,
|
||||
|
||||
jmp,
|
||||
jsr,
|
||||
|
||||
lda,
|
||||
ldy,
|
||||
lsr,
|
||||
|
||||
ORA,
|
||||
|
||||
pha,
|
||||
php,
|
||||
pla,
|
||||
plp,
|
||||
|
||||
rol,
|
||||
ror,
|
||||
rts,
|
||||
|
||||
sbc,
|
||||
sec,
|
||||
sta,
|
||||
sty,
|
||||
|
||||
tax,
|
||||
tay,
|
||||
txa,
|
||||
tya,
|
||||
};
|
||||
|
||||
static bool get_is_branch(const OpCode o)
|
||||
{
|
||||
switch (o) {
|
||||
case OpCode::beq:
|
||||
case OpCode::bne:
|
||||
case OpCode::bmi:
|
||||
case OpCode::bpl:
|
||||
case OpCode::bcc:
|
||||
case OpCode::bcs:
|
||||
return true;
|
||||
case OpCode::adc:
|
||||
case OpCode::AND:
|
||||
case OpCode::asl:
|
||||
case OpCode::bit:
|
||||
case OpCode::cpy:
|
||||
case OpCode::cmp:
|
||||
case OpCode::clc:
|
||||
case OpCode::dec:
|
||||
case OpCode::eor:
|
||||
case OpCode::inc:
|
||||
case OpCode::jmp:
|
||||
case OpCode::jsr:
|
||||
case OpCode::lda:
|
||||
case OpCode::ldy:
|
||||
case OpCode::lsr:
|
||||
case OpCode::ORA:
|
||||
case OpCode::pha:
|
||||
case OpCode::php:
|
||||
case OpCode::pla:
|
||||
case OpCode::plp:
|
||||
case OpCode::rol:
|
||||
case OpCode::ror:
|
||||
case OpCode::rts:
|
||||
case OpCode::sbc:
|
||||
case OpCode::sec:
|
||||
case OpCode::sta:
|
||||
case OpCode::sty:
|
||||
case OpCode::tax:
|
||||
case OpCode::tay:
|
||||
case OpCode::txa:
|
||||
case OpCode::tya:
|
||||
|
||||
case OpCode::unknown:
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
static bool get_is_comparison(const OpCode o)
|
||||
{
|
||||
switch (o) {
|
||||
case OpCode::bit:
|
||||
case OpCode::cmp:
|
||||
case OpCode::cpy:
|
||||
return true;
|
||||
case OpCode::adc:
|
||||
case OpCode::AND:
|
||||
case OpCode::asl:
|
||||
case OpCode::beq:
|
||||
case OpCode::bne:
|
||||
case OpCode::bmi:
|
||||
case OpCode::bpl:
|
||||
case OpCode::bcc:
|
||||
case OpCode::bcs:
|
||||
case OpCode::clc:
|
||||
case OpCode::dec:
|
||||
case OpCode::eor:
|
||||
case OpCode::inc:
|
||||
case OpCode::jmp:
|
||||
case OpCode::jsr:
|
||||
case OpCode::lda:
|
||||
case OpCode::ldy:
|
||||
case OpCode::lsr:
|
||||
case OpCode::ORA:
|
||||
case OpCode::pha:
|
||||
case OpCode::php:
|
||||
case OpCode::pla:
|
||||
case OpCode::plp:
|
||||
case OpCode::rol:
|
||||
case OpCode::ror:
|
||||
case OpCode::rts:
|
||||
case OpCode::sbc:
|
||||
case OpCode::sec:
|
||||
case OpCode::sta:
|
||||
case OpCode::sty:
|
||||
case OpCode::tax:
|
||||
case OpCode::tay:
|
||||
case OpCode::txa:
|
||||
case OpCode::tya:
|
||||
case OpCode::unknown:
|
||||
break;
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
|
||||
explicit mos6502(const OpCode o)
|
||||
: ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o))
|
||||
{
|
||||
}
|
||||
|
||||
mos6502(const Type t, std::string s)
|
||||
: ASMLine(t, std::move(s))
|
||||
{
|
||||
}
|
||||
|
||||
mos6502(const OpCode o, Operand t_o)
|
||||
: ASMLine(Type::Instruction, std::string{ to_string(o) }), opcode(o), op(std::move(t_o)), is_branch(get_is_branch(o)), is_comparison(get_is_comparison(o))
|
||||
{
|
||||
}
|
||||
|
||||
constexpr static std::string_view to_string(const OpCode o)
|
||||
{
|
||||
switch (o) {
|
||||
case OpCode::lda: return "lda";
|
||||
case OpCode::asl: return "asl";
|
||||
case OpCode::rol: return "rol";
|
||||
case OpCode::ldy: return "ldy";
|
||||
case OpCode::tay: return "tay";
|
||||
case OpCode::tya: return "tya";
|
||||
case OpCode::tax: return "tax";
|
||||
case OpCode::txa: return "txa";
|
||||
case OpCode::cpy: return "cpy";
|
||||
case OpCode::eor: return "eor";
|
||||
case OpCode::sta: return "sta";
|
||||
case OpCode::sty: return "sty";
|
||||
case OpCode::pha: return "pha";
|
||||
case OpCode::pla: return "pla";
|
||||
case OpCode::php: return "php";
|
||||
case OpCode::plp: return "plp";
|
||||
case OpCode::lsr: return "lsr";
|
||||
case OpCode::ror: return "ror";
|
||||
case OpCode::AND: return "and";
|
||||
case OpCode::inc: return "inc";
|
||||
case OpCode::dec: return "dec";
|
||||
case OpCode::ORA: return "ora";
|
||||
case OpCode::cmp: return "cmp";
|
||||
case OpCode::bne: return "bne";
|
||||
case OpCode::bmi: return "bmi";
|
||||
case OpCode::beq: return "beq";
|
||||
case OpCode::jmp: return "jmp";
|
||||
case OpCode::adc: return "adc";
|
||||
case OpCode::sbc: return "sbc";
|
||||
case OpCode::rts: return "rts";
|
||||
case OpCode::clc: return "clc";
|
||||
case OpCode::sec: return "sec";
|
||||
case OpCode::bit: return "bit";
|
||||
case OpCode::jsr: return "jsr";
|
||||
case OpCode::bpl: return "bpl";
|
||||
case OpCode::bcc: return "bcc";
|
||||
case OpCode::bcs: return "bcs";
|
||||
case OpCode::unknown: return "";
|
||||
}
|
||||
|
||||
return "";
|
||||
}
|
||||
|
||||
[[nodiscard]] std::string to_string() const
|
||||
{
|
||||
switch (type) {
|
||||
case ASMLine::Type::Label:
|
||||
return text;// + ':';
|
||||
case ASMLine::Type::Directive:
|
||||
case ASMLine::Type::Instruction: {
|
||||
return fmt::format("\t{} {:15}; {}", text, op.value, comment);
|
||||
}
|
||||
}
|
||||
throw std::runtime_error("Unable to render: " + text);
|
||||
}
|
||||
|
||||
|
||||
OpCode opcode = OpCode::unknown;
|
||||
Operand op;
|
||||
std::string comment;
|
||||
bool is_branch = false;
|
||||
bool is_comparison = false;
|
||||
};
|
||||
|
||||
|
||||
struct AVR : ASMLine
|
||||
{
|
||||
@ -872,6 +497,7 @@ void translate_instruction(const Personality &personality, std::vector<mos6502>
|
||||
instructions.emplace_back(mos6502::OpCode::sta, personality.get_register(o1_reg_num));
|
||||
return;
|
||||
}
|
||||
|
||||
case AVR::OpCode::cpc: {
|
||||
// this instruction seems to need to be used in the case after a sbc operation, where the
|
||||
// carry flag is set to the appropriate borrow state, so I'm going to not invert
|
||||
@ -882,6 +508,7 @@ void translate_instruction(const Personality &personality, std::vector<mos6502>
|
||||
instructions.emplace_back(mos6502::OpCode::sbc, personality.get_register(o2_reg_num));
|
||||
return;
|
||||
}
|
||||
|
||||
case AVR::OpCode::brsh: {
|
||||
if (o1.value == ".+2") {
|
||||
// assumes 6502 'borrow' for Carry flag instead of carry, so bcs instead of bcc
|
||||
@ -996,140 +623,6 @@ void to_mos6502(const Personality &personality, const AVR &from_instruction, std
|
||||
}
|
||||
}
|
||||
|
||||
bool optimize(std::vector<mos6502> &instructions)
|
||||
{
|
||||
if (instructions.size() < 2) {
|
||||
return false;
|
||||
}
|
||||
|
||||
const auto next_instruction = [&instructions](auto i) {
|
||||
do {
|
||||
++i;
|
||||
} while (i < instructions.size() && instructions[i].type == ASMLine::Type::Directive);
|
||||
return i;
|
||||
};
|
||||
|
||||
|
||||
// remove unused flag-fix-up blocks
|
||||
// it might make sense in the future to only insert these if determined they are needed?
|
||||
for (size_t op = 10; op < instructions.size(); ++op) {
|
||||
if (instructions[op].opcode == mos6502::OpCode::lda) {
|
||||
if (instructions[op - 1].text == "; END remove if next is lda") {
|
||||
for (size_t inner_op = op - 1; inner_op > 1; --inner_op) {
|
||||
instructions[inner_op] = mos6502(ASMLine::Type::Directive,
|
||||
"; removed unused flag fix-up: " + instructions[inner_op].to_string());
|
||||
|
||||
if (instructions[inner_op].text.find("; BEGIN") != std::string::npos) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
// look for redundant load of lda after a tax
|
||||
for (size_t op = 0; op < instructions.size() - 3; ++op) {
|
||||
if (instructions[op].opcode == mos6502::OpCode::sta
|
||||
&& instructions[op + 1].opcode == mos6502::OpCode::tax
|
||||
&& instructions[op + 2].opcode == mos6502::OpCode::lda
|
||||
&& instructions[op].op.value == instructions[op + 2].op.value) {
|
||||
instructions[op + 2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string());
|
||||
return true;
|
||||
}
|
||||
}
|
||||
|
||||
// look for redundant stores to 0-page registers with sta
|
||||
for (size_t op = 0; op < instructions.size(); ++op) {
|
||||
// todo, make sure this is in the register map
|
||||
if (instructions[op].opcode == mos6502::OpCode::sta
|
||||
&& instructions[op].op.value.size() == 3) {
|
||||
for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) {
|
||||
if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) {
|
||||
// we just found a use of ourselves back, abort the search, there's probably something else going on
|
||||
break;
|
||||
}
|
||||
if (instructions[next_op].opcode == mos6502::OpCode::lda && instructions[next_op].op.value != instructions[op].op.value) {
|
||||
// someone just loaded lda with a different value, so we need to abort!
|
||||
break;
|
||||
}
|
||||
|
||||
// abort at label
|
||||
if (instructions[next_op].type == ASMLine::Type::Label) {
|
||||
break;
|
||||
}
|
||||
|
||||
if (instructions[next_op].opcode == mos6502::OpCode::sta
|
||||
&& instructions[next_op].op.value == instructions[op].op.value) {
|
||||
// looks like we found a redundant store, remove the first one
|
||||
instructions[op] = mos6502(ASMLine::Type::Directive,
|
||||
"; removed redundant sta: " + instructions[op].to_string());
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||
// look for a transfer of Y -> A immediately followed by A -> Y
|
||||
if (instructions[op].opcode == mos6502::OpCode::tya) {
|
||||
next_instruction(op);
|
||||
if (instructions[op].opcode == mos6502::OpCode::tay) {
|
||||
instructions[op] = mos6502(ASMLine::Type::Directive,
|
||||
"; removed redundant tay: " + instructions[op].to_string());
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||
// look for a store A -> loc immediately followed by loc -> A
|
||||
if (instructions[op].opcode == mos6502::OpCode::sta) {
|
||||
const auto next = next_instruction(op);
|
||||
if (instructions[next].opcode == mos6502::OpCode::lda
|
||||
&& instructions[next].op == instructions[op].op) {
|
||||
instructions[next] = mos6502(ASMLine::Type::Directive,
|
||||
"; removed redundant lda: " + instructions[next].to_string());
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||
if (instructions[op].opcode == mos6502::OpCode::ldy && instructions[op].op.type == Operand::Type::literal) {
|
||||
auto op2 = op + 1;
|
||||
|
||||
while (op2 < instructions.size() && (instructions[op2].type != ASMLine::Type::Label)) {
|
||||
// while inside this label
|
||||
if (instructions[op2].opcode == mos6502::OpCode::ldy && instructions[op2].op.value == instructions[op].op.value) {
|
||||
instructions[op2] = mos6502(ASMLine::Type::Directive, "; removed redundant ldy: " + instructions[op2].to_string());
|
||||
return true;
|
||||
}
|
||||
++op2;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||
if (instructions[op].opcode == mos6502::OpCode::lda
|
||||
&& instructions[op].op.type == Operand::Type::literal) {
|
||||
const auto operand = instructions[op].op;
|
||||
auto op2 = op + 1;
|
||||
// look for multiple stores of the same value
|
||||
while (op2 < instructions.size() && (instructions[op2].opcode == mos6502::OpCode::sta || instructions[op2].type == ASMLine::Type::Directive)) {
|
||||
++op2;
|
||||
}
|
||||
if (instructions[op2].opcode == mos6502::OpCode::lda
|
||||
&& operand == instructions[op2].op) {
|
||||
instructions[op2] = mos6502(ASMLine::Type::Directive,
|
||||
"; removed redundant lda: " + instructions[op2].to_string());
|
||||
return true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
bool fix_long_branches(std::vector<mos6502> &instructions, int &branch_patch_count)
|
||||
{
|
||||
@ -1290,13 +783,9 @@ void run(const Personality &personality, std::istream &input)
|
||||
}();
|
||||
|
||||
|
||||
for (const auto &l : new_labels) {
|
||||
std::clog << "Label: '" << l.first << "': '" << l.second << "'\n";
|
||||
}
|
||||
|
||||
for (auto &i : instructions) {
|
||||
if (i.type == ASMLine::Type::Label) {
|
||||
std::clog << "Looking up Label: '" << i.text << "'\n";
|
||||
if (i.text == "0") {
|
||||
i.text = "-memcpy_0";
|
||||
} else {
|
||||
@ -1323,11 +812,9 @@ void run(const Personality &personality, std::istream &input)
|
||||
}
|
||||
}
|
||||
|
||||
constexpr static auto start_address = 0x0801;
|
||||
|
||||
std::vector<mos6502> new_instructions;
|
||||
new_instructions.emplace_back(ASMLine::Type::Directive, ".word " + std::to_string(start_address));
|
||||
new_instructions.emplace_back(ASMLine::Type::Directive, "* = " + std::to_string(start_address));
|
||||
|
||||
personality.insert_autostart_sequence(new_instructions);
|
||||
// set __zero_reg__ (reg 1 on AVR) to 0
|
||||
new_instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00"));
|
||||
|
||||
@ -7,7 +7,7 @@ if(CPP_STARTER_USE_SDL)
|
||||
endif()
|
||||
|
||||
# Generic test that uses conan libs
|
||||
add_executable(6502-c++ 6502-c++.cpp)
|
||||
add_executable(6502-c++ 6502-c++.cpp ../include/optimizer.hpp ../include/assembly.hpp ../include/6502.hpp ../include/personality.hpp ../include/personalities/c64.hpp)
|
||||
target_link_libraries(
|
||||
6502-c++
|
||||
PRIVATE project_options
|
||||
|
||||
Loading…
Reference in New Issue
Block a user