mirror of
https://github.com/lefticus/6502-cpp.git
synced 2024-12-22 01:30:03 +00:00
Remove i386 which was lagging very far behind now
This commit is contained in:
Jason Turner
parent
4ffae19177
commit
f0caf81299
527
src/6502-c++.cpp
527
src/6502-c++.cpp
@ -356,201 +356,6 @@ struct mos6502 : ASMLine
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bool is_comparison = false;
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bool is_comparison = false;
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};
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};
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struct i386 : ASMLine
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{
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enum class OpCode {
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unknown,
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movzbl,
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movzwl,
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shrb,
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shrl,
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xorl,
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andl,
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andb,
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addb,
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ret,
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movb,
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cmpb,
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movl,
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jmp,
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jne,
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je,
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js,
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testb,
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incl,
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incb,
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decl,
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decb,
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sarl,
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addl,
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subl,
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subb,
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sall,
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orl,
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orb,
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rep,
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pushl,
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sbbb,
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negb,
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notb,
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retl,
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call
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};
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static Operand get_register(const int reg_num, const int offset = 0)
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{
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switch (reg_num) {
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// http://sta.c64.org/cbm64mem.html
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case 0x00:
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return Operand(Operand::Type::literal, "$03");// unused, fp->int routine pointer
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case 0x01:
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return Operand(Operand::Type::literal, "$04");
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case 0x02:
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return Operand(Operand::Type::literal, "$05");// unused, int->fp routine pointer
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case 0x03:
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return Operand(Operand::Type::literal, "$06");
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case 0x04:
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return Operand(Operand::Type::literal, "$fb");// unused
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case 0x05:
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return Operand(Operand::Type::literal, "$fc");// unused
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case 0x06:
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return Operand(Operand::Type::literal, "$fd");// unused
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case 0x07:
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return Operand(Operand::Type::literal, "$fe");// unused
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case 0x08:
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return Operand(Operand::Type::literal, "$22");// unused
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case 0x09:
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return Operand(Operand::Type::literal, "$23");// unused
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case 0x0A:
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return Operand(Operand::Type::literal, "$39");// Current BASIC line number
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case 0x0B:
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return Operand(Operand::Type::literal, "$3a");// Current BASIC line number
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case 0x10:
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return get_register(0x00 + offset);
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case 0x11:
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return get_register(0x02 + offset);
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case 0x12:
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return get_register(0x04 + offset);
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case 0x13:
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return get_register(0x06 + offset);
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case 0x14:
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return get_register(0x08 + offset);
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case 0x15:
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return get_register(0x0A + offset);
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};
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throw std::runtime_error("Unhandled register number: " + std::to_string(reg_num));
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}
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static OpCode parse_opcode(Type t, const std::string &o)
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{
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switch (t) {
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case Type::Label:
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return OpCode::unknown;
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case Type::Directive:
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return OpCode::unknown;
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case Type::Instruction: {
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if (o == "movzwl") return OpCode::movzwl;
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if (o == "movzbl") return OpCode::movzbl;
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if (o == "shrb") return OpCode::shrb;
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if (o == "shrl") return OpCode::shrl;
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if (o == "xorl") return OpCode::xorl;
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if (o == "andl") return OpCode::andl;
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if (o == "ret") return OpCode::ret;
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if (o == "movb") return OpCode::movb;
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if (o == "cmpb") return OpCode::cmpb;
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if (o == "movl") return OpCode::movl;
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if (o == "jmp") return OpCode::jmp;
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if (o == "testb") return OpCode::testb;
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if (o == "incl") return OpCode::incl;
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if (o == "sarl") return OpCode::sarl;
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if (o == "decl") return OpCode::decl;
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if (o == "jne") return OpCode::jne;
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if (o == "je") return OpCode::je;
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if (o == "js") return OpCode::js;
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if (o == "subl") return OpCode::subl;
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if (o == "subb") return OpCode::subb;
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if (o == "addl") return OpCode::addl;
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if (o == "addb") return OpCode::addb;
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if (o == "sall") return OpCode::sall;
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if (o == "orl") return OpCode::orl;
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if (o == "andb") return OpCode::andb;
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if (o == "orb") return OpCode::orb;
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if (o == "decb") return OpCode::decb;
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if (o == "incb") return OpCode::incb;
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if (o == "rep") return OpCode::rep;
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if (o == "notb") return OpCode::notb;
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if (o == "negb") return OpCode::negb;
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if (o == "sbbb") return OpCode::sbbb;
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if (o == "pushl") return OpCode::pushl;
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if (o == "retl") return OpCode::retl;
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if (o == "call") return OpCode::call;
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if (o == "calll") return OpCode::call;
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}
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}
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throw std::runtime_error("Unknown opcode: " + o);
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}
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static Operand parse_operand(std::string o)
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{
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if (o.empty()) {
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return Operand();
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}
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if (o[0] == '%') {
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if (o == "%al") {
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return Operand(Operand::Type::reg, 0x00);
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} else if (o == "%ah") {
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return Operand(Operand::Type::reg, 0x01);
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} else if (o == "%bl") {
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return Operand(Operand::Type::reg, 0x02);
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} else if (o == "%bh") {
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return Operand(Operand::Type::reg, 0x03);
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} else if (o == "%cl") {
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return Operand(Operand::Type::reg, 0x04);
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} else if (o == "%ch") {
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return Operand(Operand::Type::reg, 0x05);
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} else if (o == "%dl") {
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return Operand(Operand::Type::reg, 0x06);
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} else if (o == "%dh") {
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return Operand(Operand::Type::reg, 0x07);
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} else if (o == "%sil") {
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return Operand(Operand::Type::reg, 0x08);
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} else if (o == "%dil") {
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return Operand(Operand::Type::reg, 0x0A);
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} else if (o == "%ax" || o == "%eax") {
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return Operand(Operand::Type::reg, 0x10);
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} else if (o == "%bx" || o == "%ebx") {
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return Operand(Operand::Type::reg, 0x11);
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} else if (o == "%cx" || o == "%ecx") {
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return Operand(Operand::Type::reg, 0x12);
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} else if (o == "%dx" || o == "%edx") {
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return Operand(Operand::Type::reg, 0x13);
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} else if (o == "%si" || o == "%esi") {
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return Operand(Operand::Type::reg, 0x14);
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} else if (o == "%di" || o == "%edi") {
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return Operand(Operand::Type::reg, 0x15);
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} else {
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throw std::runtime_error("Unknown register operand: '" + o + "'");
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}
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} else {
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return Operand(Operand::Type::literal, std::move(o));
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}
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}
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i386(const int t_line_num, std::string t_line_text, Type t, std::string t_opcode, std::string o1 = "", std::string o2 = "")
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: ASMLine(t, t_opcode), line_num(t_line_num), line_text(std::move(t_line_text)),
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opcode(parse_opcode(t, t_opcode)), operand1(parse_operand(o1)), operand2(parse_operand(o2))
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{
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}
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int line_num;
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std::string line_text;
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OpCode opcode;
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Operand operand1;
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Operand operand2;
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};
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struct AVR : ASMLine
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struct AVR : ASMLine
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{
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{
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@ -1079,7 +884,6 @@ void translate_instruction(std::vector<mos6502> &instructions, const AVR::OpCode
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instructions.emplace_back(mos6502::OpCode::bcs, o1);
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instructions.emplace_back(mos6502::OpCode::bcs, o1);
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return;
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return;
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}
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}
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}
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}
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case AVR::OpCode::breq: {
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case AVR::OpCode::breq: {
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@ -1089,291 +893,11 @@ void translate_instruction(std::vector<mos6502> &instructions, const AVR::OpCode
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case AVR::OpCode::unknown: {
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case AVR::OpCode::unknown: {
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throw std::runtime_error("Could not translate 'unknown' instruction");
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throw std::runtime_error("Could not translate 'unknown' instruction");
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}
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}
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}
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}
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throw std::runtime_error("Could not translate unhandled instruction");
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throw std::runtime_error("Could not translate unhandled instruction");
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}
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}
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void translate_instruction(std::vector<mos6502> &instructions, const i386::OpCode op, const Operand &o1, const Operand &o2)
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{
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switch (op) {
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case i386::OpCode::ret:
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instructions.emplace_back(mos6502::OpCode::rts);
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break;
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case i386::OpCode::retl:
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/// \todo I don't know if this is completely correct for retl translation
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instructions.emplace_back(mos6502::OpCode::rts);
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break;
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case i386::OpCode::movl:
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if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1));
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#<" + o1.value));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, "#>" + o1.value));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1));
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} else {
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throw std::runtime_error("Cannot translate movl instruction");
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}
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break;
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case i386::OpCode::xorl:
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if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg
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&& o1.reg_num == o2.reg_num) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00"));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num, 1));
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} else {
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throw std::runtime_error("Cannot translate xorl instruction");
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}
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break;
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case i386::OpCode::movb:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::sta, o2);
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
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instructions.emplace_back(mos6502::OpCode::sta, o2);
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} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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} else {
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throw std::runtime_error("Cannot translate movb instruction");
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}
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break;
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case i386::OpCode::orb:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::ORA, o2);
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instructions.emplace_back(mos6502::OpCode::sta, o2);
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} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
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instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
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instructions.emplace_back(mos6502::OpCode::ORA, i386::get_register(o2.reg_num));
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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} else {
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throw std::runtime_error("Cannot translate orb instruction");
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}
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break;
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case i386::OpCode::movzbl:
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if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
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instructions.emplace_back(mos6502::OpCode::lda, o1);
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instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
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} else {
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throw std::runtime_error("Cannot translate movzbl instruction");
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}
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break;
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case i386::OpCode::shrb:
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if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) {
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const auto do_shift = [&instructions](const int reg_num) {
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instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num));
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};
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if (o1.type == Operand::Type::literal) {
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const auto count = parse_8bit_literal(o1.value);
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for (int i = 0; i < count; ++i) {
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do_shift(o2.reg_num);
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}
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} else {
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do_shift(o1.reg_num);
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}
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} else {
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throw std::runtime_error("Cannot translate shrb instruction");
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}
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break;
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case i386::OpCode::shrl:
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if (o1.type == Operand::Type::reg || o2.type == Operand::Type::reg) {
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const auto do_shift = [&instructions](const int reg_num) {
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instructions.emplace_back(mos6502::OpCode::lsr, i386::get_register(reg_num, 1));
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instructions.emplace_back(mos6502::OpCode::ror, i386::get_register(reg_num));
|
|
||||||
};
|
|
||||||
|
|
||||||
if (o1.type == Operand::Type::literal) {
|
|
||||||
const auto count = parse_8bit_literal(o1.value);
|
|
||||||
for (int i = 0; i < count; ++i) {
|
|
||||||
do_shift(o2.reg_num);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
do_shift(o1.reg_num);
|
|
||||||
}
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate shrl instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::testb:
|
|
||||||
if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg && o1.reg_num == o2.reg_num) {
|
|
||||||
// this just tests the register for 0
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
|
|
||||||
// instructions.emplace_back(mos6502::OpCode::bit, Operand(Operand::Type::literal, "#$00"));
|
|
||||||
} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg) {
|
|
||||||
// ands the values
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num));
|
|
||||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
|
|
||||||
// ands the values
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::bit, i386::get_register(o2.reg_num));
|
|
||||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
|
|
||||||
// ands the values
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::bit, o2);
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate testb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::decb:
|
|
||||||
if (o1.type == Operand::Type::reg) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::dec, i386::get_register(o1.reg_num));
|
|
||||||
} else {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::dec, o1);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::incb:
|
|
||||||
if (o1.type == Operand::Type::reg) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num));
|
|
||||||
} else {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::inc, o1);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::jne:
|
|
||||||
instructions.emplace_back(mos6502::OpCode::bne, o1);
|
|
||||||
break;
|
|
||||||
case i386::OpCode::je:
|
|
||||||
instructions.emplace_back(mos6502::OpCode::beq, o1);
|
|
||||||
break;
|
|
||||||
case i386::OpCode::js:
|
|
||||||
instructions.emplace_back(mos6502::OpCode::bmi, o1);
|
|
||||||
break;
|
|
||||||
case i386::OpCode::jmp:
|
|
||||||
instructions.emplace_back(mos6502::OpCode::jmp, o1);
|
|
||||||
break;
|
|
||||||
case i386::OpCode::addb:
|
|
||||||
if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::clc);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::adc, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));
|
|
||||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::clc);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::adc, o2);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, o2);
|
|
||||||
} else if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::clc);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::adc, o2);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, o2);
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate addb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::cmpb:
|
|
||||||
if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, o2);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o2.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::cmp, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate cmpb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::andb:
|
|
||||||
if (o1.type == Operand::Type::literal && o2.type == Operand::Type::reg) {
|
|
||||||
const auto reg = i386::get_register(o2.reg_num);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, reg);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, reg);
|
|
||||||
} else if (o1.type == Operand::Type::literal && o2.type == Operand::Type::literal) {
|
|
||||||
const auto reg = i386::get_register(o2.reg_num);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, o2);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::AND, Operand(o1.type, fixup_8bit_literal(o1.value)));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, o2);
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate andb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::negb:
|
|
||||||
if (o1.type == Operand::Type::reg) {
|
|
||||||
// perform a two's complement of the register location
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff"));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::inc, i386::get_register(o1.reg_num));
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate negb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::notb:
|
|
||||||
if (o1.type == Operand::Type::reg) {
|
|
||||||
// exclusive or against 0xff to perform a logical not
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff"));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o1.reg_num));
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate notb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::subb:
|
|
||||||
// DEST <- DEST - SRC
|
|
||||||
// o2 = o2 - o1
|
|
||||||
// Ensure that we set the carry flag before performing the subtraction
|
|
||||||
if (o1.type == Operand::Type::reg && o2.type == Operand::Type::literal) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, o2);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sec);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sbc, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, o2);
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate subb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
case i386::OpCode::pushl:
|
|
||||||
if (o1.type == Operand::Type::reg) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::pha);
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, i386::get_register(o1.reg_num, 1));
|
|
||||||
instructions.emplace_back(mos6502::OpCode::pha);
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate pushl instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case i386::OpCode::sbbb:
|
|
||||||
// DEST <- (DEST – (SRC + CF))
|
|
||||||
// o2 <- (o2 - (o1 + cf))
|
|
||||||
// if o1 and o2 are the same we get
|
|
||||||
// o2 <- (o2 - (o2 + cf))
|
|
||||||
// o2 <- -cf
|
|
||||||
if (o1.type == Operand::Type::reg && o2.type == Operand::Type::reg
|
|
||||||
&& o1.reg_num == o2.reg_num) {
|
|
||||||
instructions.emplace_back(mos6502::OpCode::lda, Operand(Operand::Type::literal, "#$00"));// reset a
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sbc, Operand(Operand::Type::literal, "#$00"));// subtract out the carry flag
|
|
||||||
instructions.emplace_back(mos6502::OpCode::eor, Operand(Operand::Type::literal, "#$ff"));// invert the bits
|
|
||||||
instructions.emplace_back(mos6502::OpCode::sta, i386::get_register(o2.reg_num));// place the value
|
|
||||||
} else {
|
|
||||||
throw std::runtime_error("Cannot translate sbbb instruction");
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
|
|
||||||
case i386::OpCode::call:
|
|
||||||
instructions.emplace_back(mos6502::OpCode::jsr, o1);
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
throw std::runtime_error("Cannot translate unhandled instruction");
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
enum class LogLevel {
|
enum class LogLevel {
|
||||||
Warning,
|
Warning,
|
||||||
Error
|
Error
|
||||||
@ -1391,8 +915,7 @@ std::string to_string(const LogLevel ll)
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
template<typename FromArch>
|
void log(LogLevel ll, const AVR &i, const std::string &message)
|
||||||
void log(LogLevel ll, const FromArch &i, const std::string &message)
|
|
||||||
{
|
{
|
||||||
std::cerr << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n";
|
std::cerr << to_string(ll) << ": " << i.line_num << ": " << message << ": `" << i.line_text << "`\n";
|
||||||
}
|
}
|
||||||
@ -1402,8 +925,7 @@ void log(LogLevel ll, const int line_no, const std::string &line, const std::str
|
|||||||
std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n";
|
std::cerr << to_string(ll) << ": " << line_no << ": " << message << ": `" << line << "`\n";
|
||||||
}
|
}
|
||||||
|
|
||||||
template<typename FromArch>
|
void to_mos6502(const AVR &from_instruction, std::vector<mos6502> &instructions)
|
||||||
void to_mos6502(const FromArch &from_instruction, std::vector<mos6502> &instructions)
|
|
||||||
{
|
{
|
||||||
try {
|
try {
|
||||||
switch (from_instruction.type) {
|
switch (from_instruction.type) {
|
||||||
@ -1483,9 +1005,8 @@ bool optimize(std::vector<mos6502> &instructions)
|
|||||||
// it might make sense in the future to only insert these if determined they are needed?
|
// it might make sense in the future to only insert these if determined they are needed?
|
||||||
for (size_t op = 10; op < instructions.size(); ++op) {
|
for (size_t op = 10; op < instructions.size(); ++op) {
|
||||||
if (instructions[op].opcode == mos6502::OpCode::lda) {
|
if (instructions[op].opcode == mos6502::OpCode::lda) {
|
||||||
if (instructions[op-1].text == "; END remove if next is lda")
|
if (instructions[op - 1].text == "; END remove if next is lda") {
|
||||||
{
|
for (size_t inner_op = op - 1; inner_op > 1; --inner_op) {
|
||||||
for (size_t inner_op = op-1; inner_op > 1; --inner_op) {
|
|
||||||
instructions[inner_op] = mos6502(ASMLine::Type::Directive,
|
instructions[inner_op] = mos6502(ASMLine::Type::Directive,
|
||||||
"; removed unused flag fix-up: " + instructions[inner_op].to_string());
|
"; removed unused flag fix-up: " + instructions[inner_op].to_string());
|
||||||
|
|
||||||
@ -1501,11 +1022,10 @@ bool optimize(std::vector<mos6502> &instructions)
|
|||||||
// look for redundant load of lda after a tax
|
// look for redundant load of lda after a tax
|
||||||
for (size_t op = 0; op < instructions.size() - 3; ++op) {
|
for (size_t op = 0; op < instructions.size() - 3; ++op) {
|
||||||
if (instructions[op].opcode == mos6502::OpCode::sta
|
if (instructions[op].opcode == mos6502::OpCode::sta
|
||||||
&& instructions[op+1].opcode == mos6502::OpCode::tax
|
&& instructions[op + 1].opcode == mos6502::OpCode::tax
|
||||||
&& instructions[op+2].opcode == mos6502::OpCode::lda
|
&& instructions[op + 2].opcode == mos6502::OpCode::lda
|
||||||
&& instructions[op].op.value == instructions[op+2].op.value)
|
&& instructions[op].op.value == instructions[op + 2].op.value) {
|
||||||
{
|
instructions[op + 2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op + 2].to_string());
|
||||||
instructions[op+2] = mos6502(ASMLine::Type::Directive, "; removed redundant lda: " + instructions[op+2].to_string());
|
|
||||||
return true;
|
return true;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -1514,8 +1034,7 @@ bool optimize(std::vector<mos6502> &instructions)
|
|||||||
for (size_t op = 0; op < instructions.size(); ++op) {
|
for (size_t op = 0; op < instructions.size(); ++op) {
|
||||||
// todo, make sure this is in the register map
|
// todo, make sure this is in the register map
|
||||||
if (instructions[op].opcode == mos6502::OpCode::sta
|
if (instructions[op].opcode == mos6502::OpCode::sta
|
||||||
&& instructions[op].op.value.size() == 3)
|
&& instructions[op].op.value.size() == 3) {
|
||||||
{
|
|
||||||
for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) {
|
for (size_t next_op = op + 1; next_op < instructions.size(); ++next_op) {
|
||||||
if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) {
|
if (instructions[next_op].opcode != mos6502::OpCode::sta && instructions[next_op].op.value == instructions[op].op.value) {
|
||||||
// we just found a use of ourselves back, abort the search, there's probably something else going on
|
// we just found a use of ourselves back, abort the search, there's probably something else going on
|
||||||
@ -1532,7 +1051,7 @@ bool optimize(std::vector<mos6502> &instructions)
|
|||||||
}
|
}
|
||||||
|
|
||||||
if (instructions[next_op].opcode == mos6502::OpCode::sta
|
if (instructions[next_op].opcode == mos6502::OpCode::sta
|
||||||
&& instructions[next_op].op.value == instructions[op].op.value) {
|
&& instructions[next_op].op.value == instructions[op].op.value) {
|
||||||
// looks like we found a redundant store, remove the first one
|
// looks like we found a redundant store, remove the first one
|
||||||
instructions[op] = mos6502(ASMLine::Type::Directive,
|
instructions[op] = mos6502(ASMLine::Type::Directive,
|
||||||
"; removed redundant sta: " + instructions[op].to_string());
|
"; removed redundant sta: " + instructions[op].to_string());
|
||||||
@ -1540,7 +1059,6 @@ bool optimize(std::vector<mos6502> &instructions)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
for (size_t op = 0; op < instructions.size() - 1; ++op) {
|
||||||
@ -1689,12 +1207,6 @@ void setup_target_cpu_state([[maybe_unused]] const std::vector<AVR> &instruction
|
|||||||
new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1));
|
new_instructions.emplace_back(mos6502::OpCode::sta, AVR::get_register(1));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void setup_target_cpu_state([[maybe_unused]] const std::vector<i386> &instructions, [[maybe_unused]] std::vector<mos6502> &new_instructions)
|
|
||||||
{
|
|
||||||
}
|
|
||||||
|
|
||||||
template<typename Arch>
|
|
||||||
void run(std::istream &input)
|
void run(std::istream &input)
|
||||||
{
|
{
|
||||||
std::regex Comment(R"(\s*\#.*)");
|
std::regex Comment(R"(\s*\#.*)");
|
||||||
@ -1707,7 +1219,7 @@ void run(std::istream &input)
|
|||||||
int lineno = 0;
|
int lineno = 0;
|
||||||
|
|
||||||
|
|
||||||
std::vector<Arch> instructions;
|
std::vector<AVR> instructions;
|
||||||
|
|
||||||
while (input.good()) {
|
while (input.good()) {
|
||||||
std::string line;
|
std::string line;
|
||||||
@ -1875,19 +1387,6 @@ int main([[maybe_unused]] const int argc, const char *argv[])
|
|||||||
}
|
}
|
||||||
}();
|
}();
|
||||||
|
|
||||||
const bool is_386 = [&]() {
|
std::cout << "; AVR Mode\n";
|
||||||
for (std::size_t index = 0; index < static_cast<std::size_t>(argc); ++index) {
|
run(input);
|
||||||
if (strstr(argv[index], "x86") != nullptr) {
|
|
||||||
return true;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
return false;
|
|
||||||
}();
|
|
||||||
|
|
||||||
if (!is_386) {
|
|
||||||
std::cout << "; AVR Mode\n";
|
|
||||||
run<AVR>(input);
|
|
||||||
} else {
|
|
||||||
run<i386>(input);
|
|
||||||
}
|
|
||||||
}
|
}
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user