Merge pull request #1 from robmcmullen/legal_instructions
Decimal mode & passes torture tests
This commit is contained in:
David Buchanan
GitHub
commit
7e3ef5bd78
138
6502-emu.c
138
6502-emu.c
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@ -1,5 +1,6 @@
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#include <stdio.h>
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#include <stdlib.h>
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#include <unistd.h>
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#include <termios.h>
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#include <time.h>
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@ -18,18 +19,28 @@ void step_delay()
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nanosleep(&req, &rem);
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}
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void run_cpu()
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void run_cpu(long cycle_stop, int verbose, int mem_dump, int break_pc, int fast)
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{
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int cycles = 0;
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long cycles = 0;
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int cycles_per_step = (CPU_FREQ / (ONE_SECOND / STEP_DURATION));
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for (;;) {
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for (cycles %= cycles_per_step; cycles < cycles_per_step;) {
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cycles += step_cpu();
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if (mem_dump) save_memory(NULL);
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cycles += step_cpu(verbose);
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if ((cycle_stop > 0) && (total_cycles >= cycle_stop)) goto end;
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step_uart();
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if (break_pc >= 0 && PC == (uint16_t)break_pc) {
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fprintf(stderr, "break at %04x\n", break_pc);
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save_memory(NULL);
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goto end;
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}
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}
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step_delay(); // remove this for more speed
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if (!fast) step_delay();
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}
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end:
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return;
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}
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void restore_stdin()
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@ -48,26 +59,123 @@ void raw_stdin()
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atexit(restore_stdin);
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}
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int hextoint(char *str) {
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int val;
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if (*str == '$') str++;
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val = strtol(str, NULL, 16);
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return val;
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}
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void usage(char *argv[]) {
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fprintf(stderr, "Usage: %s [OPTIONS] FILE\n"
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"Simulate a NMOS 6502 processor\n"
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"\nOPTIONS:\n"
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"\n CPU Initialization (specify all values in hex; $nn, 0xNN, etc.)\n"
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" -a HEX set A register (default 0)\n"
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" -x HEX set X register (default 0)\n"
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" -y HEX set Y register (default 0)\n"
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" -s HEX set stack pointer (default $ff)\n"
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" -p HEX set processor status register (default 0)\n"
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" -r ADDR set initial run address (default: use value at RST_VEC)\n"
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"\n Emulator Control\n"
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" -v print CPU info at every step\n"
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" -i connect stdin/stdout to the emulator\n"
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" -b ADDR stop when PC reaches this address, write memory dump, and exit\n"
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" -c NUM exit after number of cycles (default: never)\n"
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" -f run as fast as possible; no delay loop\n"
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"\n Memory Initialization\n"
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" -l ADDR load address for ROM file (default $c000)\n"
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" FILE binary file to load\n"
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, argv[0]);
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}
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int main(int argc, char *argv[])
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{
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if (argc != 2) {
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printf("Usage: %s file.rom\n", argv[0]);
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printf("The first 16k of \"file.rom\" is loaded into the last 16k of memory.\n");
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int a, x, y, sp, sr, pc, load_addr;
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int verbose, interactive, mem_dump, break_pc, fast;
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long cycles;
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int opt;
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verbose = 0;
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interactive = 0;
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mem_dump = 0;
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cycles = 0;
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load_addr = 0xC000;
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break_pc = -1;
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fast = 0;
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a = 0;
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x = 0;
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y = 0;
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sp = 0xFF;
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sr = 0;
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pc = -RST_VEC; // negative implies indirect
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while ((opt = getopt(argc, argv, "hvimfa:b:x:y:r:p:s:g:c:l:")) != -1) {
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switch (opt) {
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case 'v':
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verbose = 1;
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break;
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case 'i':
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interactive = 1;
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break;
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case 'm':
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mem_dump = 1;
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break;
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case 'f':
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fast = 1;
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break;
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case 'b':
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break_pc = hextoint(optarg);
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break;
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case 'a':
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a = hextoint(optarg);
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break;
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case 'x':
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x = hextoint(optarg);
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break;
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case 'y':
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y = hextoint(optarg);
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break;
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case 's':
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sp = hextoint(optarg);
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break;
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case 'p':
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sr = hextoint(optarg);
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break;
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case 'r':
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case 'g':
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pc = hextoint(optarg);
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break;
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case 'c':
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cycles = atol(optarg);
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break;
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case 'l':
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load_addr = hextoint(optarg);
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break;
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case 'h':
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default: /* '?' */
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usage(argv);
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exit(EXIT_FAILURE);
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}
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}
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if (optind >= argc) {
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fprintf(stderr, "Error: expected binary file to load\n\n");
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usage(argv);
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exit(EXIT_FAILURE);
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}
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if (load_rom(argv[optind], load_addr) != 0) {
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printf("Error loading \"%s\".\n", argv[optind]);
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return EXIT_FAILURE;
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}
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if (load_rom(argv[1]) != 0) {
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printf("Error loading \"%s\".\n", argv[1]);
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return EXIT_FAILURE;
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}
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raw_stdin(); // allow individual keystrokes to be detected
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if (interactive) raw_stdin(); // allow individual keystrokes to be detected
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init_tables();
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init_uart();
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reset_cpu();
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run_cpu();
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reset_cpu(a, x, y, sp, sr, pc);
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run_cpu(cycles, verbose, mem_dump, break_pc, fast);
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return EXIT_SUCCESS;
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}
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723
6502.c
723
6502.c
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@ -4,8 +4,6 @@
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#include "6502.h"
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//#define DEBUG
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int lengths[NUM_MODES]; // instruction length table, indexed by addressing mode
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uint8_t * (*get_ptr[NUM_MODES])(); // addressing mode decoder table
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Instruction instructions[0x100]; // instruction data table
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@ -48,12 +46,29 @@ static inline uint8_t * write_ptr()
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return write_addr = get_ptr[inst.mode]();
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}
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/* Branch logic common to all branch instructions */
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static inline void take_branch()
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{
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uint16_t oldPC;
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oldPC = PC + 2; // PC has already moved to point to the next instruction
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PC = read_ptr() - memory;
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if ((PC ^ oldPC) & 0xff00) extra_cycles += 1; // addr crosses page boundary
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extra_cycles += 1;
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}
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/* Instruction Implementations */
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static void inst_ADC()
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{
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uint8_t operand = * read_ptr();
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int tmp = A + operand + (SR.bits.carry & 1);
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unsigned int tmp = A + operand + (SR.bits.carry & 1);
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if (SR.bits.decimal) {
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tmp = (A & 0x0f) + (operand & 0x0f) + (SR.bits.carry & 1);
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if (tmp >= 10) tmp = (tmp - 10) | 0x10;
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tmp += (A & 0xf0) + (operand & 0xf0);
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if (tmp > 0x9f) tmp += 0x60;
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}
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SR.bits.carry = tmp > 0xFF;
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SR.bits.overflow = ((A^tmp)&(operand^tmp)&0x80) != 0;
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A = tmp & 0xFF;
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@ -81,21 +96,21 @@ static void inst_ASL()
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static void inst_BCC()
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{
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if (!SR.bits.carry) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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static void inst_BCS()
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{
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if (SR.bits.carry) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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static void inst_BEQ()
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{
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if (SR.bits.zero) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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@ -110,21 +125,21 @@ static void inst_BIT()
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static void inst_BMI()
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{
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if (SR.bits.sign) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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static void inst_BNE()
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{
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if (!SR.bits.zero) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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static void inst_BPL()
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{
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if (!SR.bits.sign) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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@ -145,14 +160,14 @@ static void inst_BRK()
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static void inst_BVC()
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{
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if (!SR.bits.overflow) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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static void inst_BVS()
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{
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if (SR.bits.overflow) {
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PC = read_ptr() - memory;
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take_branch();
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}
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}
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@ -305,7 +320,9 @@ static void inst_LSR()
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static void inst_NOP()
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{
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// nothing
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// thrown away, just used to compute any extra cycles for the multi-byte
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// NOP statements
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read_ptr();
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}
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static void inst_ORA()
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@ -322,8 +339,16 @@ static void inst_PHA()
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static void inst_PHP()
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{
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SR.bits.brk = 1; // this is slightly unexpected, but it's what the real hardware does.
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stack_push(SR.byte);
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union StatusReg pushed_sr;
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// PHP sets the BRK flag in the byte that is pushed onto the stack,
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// but doesn't affect the status register itself. this is slightly
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// unexpected, but it's what the real hardware does.
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//
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// See http://visual6502.org/wiki/index.php?title=6502_BRK_and_B_bit
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pushed_sr.byte = SR.byte;
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pushed_sr.bits.brk = 1;
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stack_push(pushed_sr.byte);
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}
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static void inst_PLA()
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@ -337,6 +362,7 @@ static void inst_PLP()
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{
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SR.byte = stack_pull();
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SR.bits.unused = 1;
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SR.bits.brk = 0;
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}
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static void inst_ROL()
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@ -381,11 +407,21 @@ static void inst_RTS()
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static void inst_SBC()
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{
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uint8_t operand = ~(* read_ptr()); // identical to ACD with the operand inverted
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int tmp = A + operand + (SR.bits.carry & 1);
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SR.bits.carry = tmp > 0xFF;
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SR.bits.overflow = ((A^tmp)&(operand^tmp)&0x80) != 0;
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A = tmp & 0xFF;
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uint8_t operand = * read_ptr();
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unsigned int tmp, lo, hi;
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tmp = A - operand - 1 + (SR.bits.carry & 1);
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SR.bits.overflow = ((A^tmp)&(A^operand)&0x80) != 0;
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if (SR.bits.decimal) {
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lo = (A & 0x0f) - (operand & 0x0f) - 1 + SR.bits.carry;
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hi = (A >> 4) - (operand >> 4);
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if (lo & 0x10) lo -= 6, hi--;
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if (hi & 0x10) hi -= 6;
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A = (hi << 4) | (lo & 0x0f);
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}
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else {
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A = tmp & 0xFF;
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}
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SR.bits.carry = tmp < 0x100;
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N_flag(A);
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Z_flag(A);
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}
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@ -398,7 +434,6 @@ static void inst_SEC()
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static void inst_SED()
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{
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SR.bits.decimal = 1;
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printf("DECIMAL! :(\r\n"); // TODO
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}
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static void inst_SEI()
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@ -409,6 +444,7 @@ static void inst_SEI()
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static void inst_STA()
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{
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* write_ptr() = A;
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extra_cycles = 0; // STA has no addressing modes that use the extra cycle
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}
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static void inst_STX()
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@ -463,6 +499,13 @@ static void inst_TYA()
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/* Addressing Implementations */
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uint8_t * get_IMPL()
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{
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// dummy implementation; for completeness necessary for cycle counting NOP
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// instructions
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return &memory[0];
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}
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uint8_t * get_IMM()
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{
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return &memory[(uint16_t) (PC+1)];
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@ -502,12 +545,18 @@ uint8_t * get_ABS()
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uint8_t * get_ABSX()
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{
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return &memory[(uint16_t) (get_uint16() + X)];
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uint16_t ptr;
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ptr = (uint16_t)(get_uint16() + X);
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if ((uint8_t)ptr < X) extra_cycles ++;
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return &memory[ptr];
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}
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uint8_t * get_ABSY()
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{
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return &memory[(uint16_t) (get_uint16() + Y)];
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uint16_t ptr;
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ptr = (uint16_t)(get_uint16() + Y);
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if ((uint8_t)ptr < Y) extra_cycles ++;
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return &memory[ptr];
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}
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uint8_t * get_IND()
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@ -520,15 +569,28 @@ uint8_t * get_IND()
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uint8_t * get_XIND()
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{
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uint16_t ptr;
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memcpy(&ptr, get_ZPX(), sizeof(ptr));
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ptr = ((* get_IMM()) + X) & 0xFF;
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if (ptr == 0xff) { // check for wraparound in zero page
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ptr = memory[ptr] + (memory[ptr & 0xff00] << 8);
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}
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else {
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memcpy(&ptr, &memory[ptr], sizeof(ptr));
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}
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return &memory[ptr];
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}
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uint8_t * get_INDY()
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{
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uint16_t ptr;
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memcpy(&ptr, get_ZP(), sizeof(ptr));
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ptr = * get_IMM();
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if (ptr == 0xff) { // check for wraparound in zero page
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ptr = memory[ptr] + (memory[ptr & 0xff00] << 8);
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}
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else {
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memcpy(&ptr, &memory[ptr], sizeof(ptr));
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}
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ptr += Y;
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if ((uint8_t)ptr < Y) extra_cycles ++;
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return &memory[ptr];
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}
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|
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@ -537,6 +599,28 @@ uint8_t * get_REL()
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return &memory[(uint16_t) (PC + (int8_t) * get_IMM())];
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}
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uint8_t * get_JMP_IND_BUG()
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{
|
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uint8_t * addr;
|
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uint16_t ptr;
|
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|
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ptr = get_uint16();
|
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if ((ptr & 0xff) == 0xff) {
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// Bug when crosses a page boundary. When using relative index ($xxff),
|
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// instead of using the last byte of the page and the first byte of the
|
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// next page, it uses the first byte of the same page. E.g. jmp ($baff)
|
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// would use the value at $baff as the LSB, but $ba00 as the high byte
|
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// instead of $bb00. This was fixed in the 65C02
|
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ptr = memory[ptr] + (memory[ptr & 0xff00] << 8);
|
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|
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}
|
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else {
|
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addr = &memory[ptr];
|
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memcpy(&ptr, addr, sizeof(ptr));
|
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}
|
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return &memory[ptr];
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}
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/* Construction of Tables */
|
||||
|
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|
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@ -557,7 +641,8 @@ void init_tables() // this is only done at runtime to improve code readability.
|
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lengths[ZP] = 2;
|
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lengths[ZPX] = 2;
|
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lengths[ZPY] = 2;
|
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|
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lengths[JMP_IND_BUG] = 3;
|
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|
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/* Addressing Modes */
|
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|
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get_ptr[ACC] = get_ACC;
|
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|
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@ -565,6 +650,7 @@ void init_tables() // this is only done at runtime to improve code readability.
|
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get_ptr[ABSX] = get_ABSX;
|
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get_ptr[ABSY] = get_ABSY;
|
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get_ptr[IMM] = get_IMM;
|
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get_ptr[IMPL] = get_IMPL;
|
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get_ptr[IND] = get_IND;
|
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get_ptr[XIND] = get_XIND;
|
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get_ptr[INDY] = get_INDY;
|
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|
|
@ -572,283 +658,291 @@ void init_tables() // this is only done at runtime to improve code readability.
|
|||
get_ptr[ZP] = get_ZP;
|
||||
get_ptr[ZPX] = get_ZPX;
|
||||
get_ptr[ZPY] = get_ZPY;
|
||||
|
||||
get_ptr[JMP_IND_BUG] = get_JMP_IND_BUG;
|
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|
||||
/* Instructions */
|
||||
|
||||
instructions[0x00] = (Instruction) {"BRK impl", inst_BRK, IMPL, 7,};
|
||||
instructions[0x00] = (Instruction) {"BRK impl", inst_BRK, IMPL, 7};
|
||||
instructions[0x01] = (Instruction) {"ORA X,ind", inst_ORA, XIND, 6};
|
||||
instructions[0x02] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x03] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x04] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x05] = (Instruction) {"ORA zpg", inst_ORA, ZP, 5};
|
||||
instructions[0x06] = (Instruction) {"ASL zpg", inst_ASL, ZP, 1};
|
||||
instructions[0x07] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x08] = (Instruction) {"PHP impl", inst_PHP, IMPL, 1};
|
||||
instructions[0x09] = (Instruction) {"ORA #", inst_ORA, IMM, 1};
|
||||
instructions[0x0A] = (Instruction) {"ASL A", inst_ASL, ACC, 1};
|
||||
instructions[0x0B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x0C] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x0D] = (Instruction) {"ORA abs", inst_ORA, ABS, 1};
|
||||
instructions[0x0E] = (Instruction) {"ASL abs", inst_ASL, ABS, 1};
|
||||
instructions[0x0F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x10] = (Instruction) {"BPL rel", inst_BPL, REL, 1};
|
||||
instructions[0x11] = (Instruction) {"ORA ind,Y", inst_ORA, INDY, 1};
|
||||
instructions[0x12] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x13] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x14] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x15] = (Instruction) {"ORA zpg,X", inst_ORA, ZPX, 1};
|
||||
instructions[0x16] = (Instruction) {"ASL zpg,X", inst_ASL, ZPX, 1};
|
||||
instructions[0x17] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x18] = (Instruction) {"CLC impl", inst_CLC, IMPL, 1};
|
||||
instructions[0x19] = (Instruction) {"ORA abs,Y", inst_ORA, ABSY, 1};
|
||||
instructions[0x1A] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x1B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x1C] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x1D] = (Instruction) {"ORA abs,X", inst_ORA, ABSX, 1};
|
||||
instructions[0x1E] = (Instruction) {"ASL abs,X", inst_ASL, ABSX, 1};
|
||||
instructions[0x1F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x20] = (Instruction) {"JSR abs", inst_JSR, ABS, 1};
|
||||
instructions[0x21] = (Instruction) {"AND X,ind", inst_AND, XIND, 1};
|
||||
instructions[0x22] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x23] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x24] = (Instruction) {"BIT zpg", inst_BIT, ZP, 1};
|
||||
instructions[0x25] = (Instruction) {"AND zpg", inst_AND, ZP, 1};
|
||||
instructions[0x26] = (Instruction) {"ROL zpg", inst_ROL, ZP, 1};
|
||||
instructions[0x27] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x28] = (Instruction) {"PLP impl", inst_PLP, IMPL, 1};
|
||||
instructions[0x29] = (Instruction) {"AND #", inst_AND, IMM, 1};
|
||||
instructions[0x2A] = (Instruction) {"ROL A", inst_ROL, ACC, 1};
|
||||
instructions[0x2B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x2C] = (Instruction) {"BIT abs", inst_BIT, ABS, 1};
|
||||
instructions[0x2D] = (Instruction) {"AND abs", inst_AND, ABS, 1};
|
||||
instructions[0x2E] = (Instruction) {"ROL abs", inst_ROL, ABS, 1};
|
||||
instructions[0x2F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x30] = (Instruction) {"BMI rel", inst_BMI, REL, 1};
|
||||
instructions[0x31] = (Instruction) {"AND ind,Y", inst_AND, INDY, 1};
|
||||
instructions[0x32] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x33] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x34] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x35] = (Instruction) {"AND zpg,X", inst_AND, ZPX, 1};
|
||||
instructions[0x36] = (Instruction) {"ROL zpg,X", inst_ROL, ZPX, 1};
|
||||
instructions[0x37] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x38] = (Instruction) {"SEC impl", inst_SEC, IMPL, 1};
|
||||
instructions[0x39] = (Instruction) {"AND abs,Y", inst_AND, ABSY, 1};
|
||||
instructions[0x3A] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x3B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x3C] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x3D] = (Instruction) {"AND abs,X", inst_AND, ABSX, 1};
|
||||
instructions[0x3E] = (Instruction) {"ROL abs,X", inst_ROL, ABSX, 1};
|
||||
instructions[0x3F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x40] = (Instruction) {"RTI impl", inst_RTI, IMPL, 1};
|
||||
instructions[0x41] = (Instruction) {"EOR X,ind", inst_EOR, XIND, 1};
|
||||
instructions[0x42] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x43] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x44] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x45] = (Instruction) {"EOR zpg", inst_EOR, ZP, 1};
|
||||
instructions[0x46] = (Instruction) {"LSR zpg", inst_LSR, ZP, 1};
|
||||
instructions[0x47] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x48] = (Instruction) {"PHA impl", inst_PHA, IMPL, 1};
|
||||
instructions[0x49] = (Instruction) {"EOR #", inst_EOR, IMM, 1};
|
||||
instructions[0x4A] = (Instruction) {"LSR A", inst_LSR, ACC, 1};
|
||||
instructions[0x4B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x4C] = (Instruction) {"JMP abs", inst_JMP, ABS, 1};
|
||||
instructions[0x4D] = (Instruction) {"EOR abs", inst_EOR, ABS, 1};
|
||||
instructions[0x4E] = (Instruction) {"LSR abs", inst_LSR, ABS, 1};
|
||||
instructions[0x4F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x50] = (Instruction) {"BVC rel", inst_BVC, REL, 1};
|
||||
instructions[0x51] = (Instruction) {"EOR ind,Y", inst_EOR, INDY, 1};
|
||||
instructions[0x52] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x53] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x54] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x55] = (Instruction) {"EOR zpg,X", inst_EOR, ZPX, 1};
|
||||
instructions[0x56] = (Instruction) {"LSR zpg,X", inst_LSR, ZPX, 1};
|
||||
instructions[0x57] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x58] = (Instruction) {"CLI impl", inst_CLI, IMPL, 1};
|
||||
instructions[0x59] = (Instruction) {"EOR abs,Y", inst_EOR, ABSY, 1};
|
||||
instructions[0x5A] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x5B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x5C] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x5D] = (Instruction) {"EOR abs,X", inst_EOR, ABSX, 1};
|
||||
instructions[0x5E] = (Instruction) {"LSR abs,X", inst_LSR, ABSX, 1};
|
||||
instructions[0x5F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x60] = (Instruction) {"RTS impl", inst_RTS, IMPL, 1};
|
||||
instructions[0x61] = (Instruction) {"ADC X,ind", inst_ADC, XIND, 1};
|
||||
instructions[0x62] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x63] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x64] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x65] = (Instruction) {"ADC zpg", inst_ADC, ZP, 1};
|
||||
instructions[0x66] = (Instruction) {"ROR zpg", inst_ROR, ZP, 1};
|
||||
instructions[0x67] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x68] = (Instruction) {"PLA impl", inst_PLA, IMPL, 1};
|
||||
instructions[0x69] = (Instruction) {"ADC #", inst_ADC, IMM, 1};
|
||||
instructions[0x6A] = (Instruction) {"ROR A", inst_ROR, ACC, 1};
|
||||
instructions[0x6B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x6C] = (Instruction) {"JMP ind", inst_JMP, IND, 1};
|
||||
instructions[0x6D] = (Instruction) {"ADC abs", inst_ADC, ABS, 1};
|
||||
instructions[0x6E] = (Instruction) {"ROR abs", inst_ROR, ABS, 1};
|
||||
instructions[0x6F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x70] = (Instruction) {"BVS rel", inst_BVS, REL, 1};
|
||||
instructions[0x71] = (Instruction) {"ADC ind,Y", inst_ADC, INDY, 1};
|
||||
instructions[0x72] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x73] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x74] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x75] = (Instruction) {"ADC zpg,X", inst_ADC, ZPX, 1};
|
||||
instructions[0x76] = (Instruction) {"ROR zpg,X", inst_ROR, ZPX, 1};
|
||||
instructions[0x77] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x78] = (Instruction) {"SEI impl", inst_SEI, IMPL, 1};
|
||||
instructions[0x79] = (Instruction) {"ADC abs,Y", inst_ADC, ABSY, 1};
|
||||
instructions[0x7A] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x7B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x7C] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x7D] = (Instruction) {"ADC abs,X", inst_ADC, ABSX, 1};
|
||||
instructions[0x7E] = (Instruction) {"ROR abs,X", inst_ROR, ABSX, 1};
|
||||
instructions[0x7F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x80] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x81] = (Instruction) {"STA X,ind", inst_STA, XIND, 1};
|
||||
instructions[0x82] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x83] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x84] = (Instruction) {"STY zpg", inst_STY, ZP, 1};
|
||||
instructions[0x85] = (Instruction) {"STA zpg", inst_STA, ZP, 1};
|
||||
instructions[0x86] = (Instruction) {"STX zpg", inst_STX, ZP, 1};
|
||||
instructions[0x87] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x88] = (Instruction) {"DEY impl", inst_DEY, IMPL, 1};
|
||||
instructions[0x89] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x8A] = (Instruction) {"TXA impl", inst_TXA, IMPL, 1};
|
||||
instructions[0x8B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x8C] = (Instruction) {"STY abs", inst_STY, ABS, 1};
|
||||
instructions[0x8D] = (Instruction) {"STA abs", inst_STA, ABS, 1};
|
||||
instructions[0x8E] = (Instruction) {"STX abs", inst_STX, ABS, 1};
|
||||
instructions[0x8F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x90] = (Instruction) {"BCC rel", inst_BCC, REL, 1};
|
||||
instructions[0x91] = (Instruction) {"STA ind,Y", inst_STA, INDY, 1};
|
||||
instructions[0x92] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x93] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x94] = (Instruction) {"STY zpg,X", inst_STY, ZPX, 1};
|
||||
instructions[0x95] = (Instruction) {"STA zpg,X", inst_STA, ZPX, 1};
|
||||
instructions[0x96] = (Instruction) {"STX zpg,Y", inst_STX, ZPY, 1};
|
||||
instructions[0x97] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x98] = (Instruction) {"TYA impl", inst_TYA, IMPL, 1};
|
||||
instructions[0x99] = (Instruction) {"STA abs,Y", inst_STA, ABSY, 1};
|
||||
instructions[0x9A] = (Instruction) {"TXS impl", inst_TXS, IMPL, 1};
|
||||
instructions[0x9B] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x9C] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x9D] = (Instruction) {"STA abs,X", inst_STA, ABSX, 1};
|
||||
instructions[0x9E] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x9F] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xA0] = (Instruction) {"LDY #", inst_LDY, IMM, 1};
|
||||
instructions[0xA1] = (Instruction) {"LDA X,ind", inst_LDA, XIND, 1};
|
||||
instructions[0xA2] = (Instruction) {"LDX #", inst_LDX, IMM, 1};
|
||||
instructions[0xA3] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xA4] = (Instruction) {"LDY zpg", inst_LDY, ZP, 1};
|
||||
instructions[0xA5] = (Instruction) {"LDA zpg", inst_LDA, ZP, 1};
|
||||
instructions[0xA6] = (Instruction) {"LDX zpg", inst_LDX, ZP, 1};
|
||||
instructions[0xA7] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xA8] = (Instruction) {"TAY impl", inst_TAY, IMPL, 1};
|
||||
instructions[0xA9] = (Instruction) {"LDA #", inst_LDA, IMM, 1};
|
||||
instructions[0xAA] = (Instruction) {"TAX impl", inst_TAX, IMPL, 1};
|
||||
instructions[0xAB] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xAC] = (Instruction) {"LDY abs", inst_LDY, ABS, 1};
|
||||
instructions[0xAD] = (Instruction) {"LDA abs", inst_LDA, ABS, 1};
|
||||
instructions[0xAE] = (Instruction) {"LDX abs", inst_LDX, ABS, 1};
|
||||
instructions[0xAF] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xB0] = (Instruction) {"BCS rel", inst_BCS, REL, 1};
|
||||
instructions[0xB1] = (Instruction) {"LDA ind,Y", inst_LDA, INDY, 1};
|
||||
instructions[0xB2] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xB3] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xB4] = (Instruction) {"LDY zpg,X", inst_LDY, ZPX, 1};
|
||||
instructions[0xB5] = (Instruction) {"LDA zpg,X", inst_LDA, ZPX, 1};
|
||||
instructions[0xB6] = (Instruction) {"LDX zpg,Y", inst_LDX, ZPY, 1};
|
||||
instructions[0xB7] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xB8] = (Instruction) {"CLV impl", inst_CLV, IMPL, 1};
|
||||
instructions[0xB9] = (Instruction) {"LDA abs,Y", inst_LDA, ABSY, 1};
|
||||
instructions[0xBA] = (Instruction) {"TSX impl", inst_TSX, IMPL, 1};
|
||||
instructions[0xBB] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xBC] = (Instruction) {"LDY abs,X", inst_LDY, ABSX, 1};
|
||||
instructions[0xBD] = (Instruction) {"LDA abs,X", inst_LDA, ABSX, 1};
|
||||
instructions[0xBE] = (Instruction) {"LDX abs,Y", inst_LDX, ABSY, 1};
|
||||
instructions[0xBF] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xC0] = (Instruction) {"CPY #", inst_CPY, IMM, 1};
|
||||
instructions[0xC1] = (Instruction) {"CMP X,ind", inst_CMP, XIND, 1};
|
||||
instructions[0xC2] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xC3] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xC4] = (Instruction) {"CPY zpg", inst_CPY, ZP, 1};
|
||||
instructions[0xC5] = (Instruction) {"CMP zpg", inst_CMP, ZP, 1};
|
||||
instructions[0xC6] = (Instruction) {"DEC zpg", inst_DEC, ZP, 1};
|
||||
instructions[0xC7] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xC8] = (Instruction) {"INY impl", inst_INY, IMPL, 1};
|
||||
instructions[0xC9] = (Instruction) {"CMP #", inst_CMP, IMM, 1};
|
||||
instructions[0xCA] = (Instruction) {"DEX impl", inst_DEX, IMPL, 1};
|
||||
instructions[0xCB] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xCC] = (Instruction) {"CPY abs", inst_CPY, ABS, 1};
|
||||
instructions[0xCD] = (Instruction) {"CMP abs", inst_CMP, ABS, 1};
|
||||
instructions[0xCE] = (Instruction) {"DEC abs", inst_DEC, ABS, 1};
|
||||
instructions[0xCF] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xD0] = (Instruction) {"BNE rel", inst_BNE, REL, 1};
|
||||
instructions[0xD1] = (Instruction) {"CMP ind,Y", inst_CMP, INDY, 1};
|
||||
instructions[0xD2] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xD3] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xD4] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xD5] = (Instruction) {"CMP zpg,X", inst_CMP, ZPX, 1};
|
||||
instructions[0xD6] = (Instruction) {"DEC zpg,X", inst_DEC, ZPX, 1};
|
||||
instructions[0xD7] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xD8] = (Instruction) {"CLD impl", inst_CLD, IMPL, 1};
|
||||
instructions[0xD9] = (Instruction) {"CMP abs,Y", inst_CMP, ABSY, 1};
|
||||
instructions[0xDA] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xDB] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xDC] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xDD] = (Instruction) {"CMP abs,X", inst_CMP, ABSX, 1};
|
||||
instructions[0xDE] = (Instruction) {"DEC abs,X", inst_DEC, ABSX, 1};
|
||||
instructions[0xDF] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xE0] = (Instruction) {"CPX #", inst_CPX, IMM, 1};
|
||||
instructions[0xE1] = (Instruction) {"SBC X,ind", inst_SBC, XIND, 1};
|
||||
instructions[0xE2] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xE3] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xE4] = (Instruction) {"CPX zpg", inst_CPX, ZP, 1};
|
||||
instructions[0xE5] = (Instruction) {"SBC zpg", inst_SBC, ZP, 1};
|
||||
instructions[0xE6] = (Instruction) {"INC zpg", inst_INC, ZP, 1};
|
||||
instructions[0xE7] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xE8] = (Instruction) {"INX impl", inst_INX, IMPL, 1};
|
||||
instructions[0xE9] = (Instruction) {"SBC #", inst_SBC, IMM, 1};
|
||||
instructions[0xEA] = (Instruction) {"NOP impl", inst_NOP, IMPL, 1};
|
||||
instructions[0xEB] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xEC] = (Instruction) {"CPX abs", inst_CPX, ABS, 1};
|
||||
instructions[0xED] = (Instruction) {"SBC abs", inst_SBC, ABS, 1};
|
||||
instructions[0xEE] = (Instruction) {"INC abs", inst_INC, ABS, 1};
|
||||
instructions[0xEF] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xF0] = (Instruction) {"BEQ rel", inst_BEQ, REL, 1};
|
||||
instructions[0xF1] = (Instruction) {"SBC ind,Y", inst_SBC, INDY, 1};
|
||||
instructions[0xF2] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xF3] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xF4] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xF5] = (Instruction) {"SBC zpg,X", inst_SBC, ZPX, 1};
|
||||
instructions[0xF6] = (Instruction) {"INC zpg,X", inst_INC, ZPX, 1};
|
||||
instructions[0xF7] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xF8] = (Instruction) {"SED impl", inst_SED, IMPL, 1};
|
||||
instructions[0xF9] = (Instruction) {"SBC abs,Y", inst_SBC, ABSY, 1};
|
||||
instructions[0xFA] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xFB] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xFC] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0xFD] = (Instruction) {"SBC abs,X", inst_SBC, ABSX, 1};
|
||||
instructions[0xFE] = (Instruction) {"INC abs,X", inst_INC, ABSX, 1};
|
||||
instructions[0xFF] = (Instruction) {"???", inst_NOP, IMPL, 1};
|
||||
instructions[0x02] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x03] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x04] = (Instruction) {"???", inst_NOP, ZP, 3};
|
||||
instructions[0x05] = (Instruction) {"ORA zpg", inst_ORA, ZP, 3};
|
||||
instructions[0x06] = (Instruction) {"ASL zpg", inst_ASL, ZP, 5};
|
||||
instructions[0x07] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x08] = (Instruction) {"PHP impl", inst_PHP, IMPL, 3};
|
||||
instructions[0x09] = (Instruction) {"ORA #", inst_ORA, IMM, 2};
|
||||
instructions[0x0A] = (Instruction) {"ASL A", inst_ASL, ACC, 2};
|
||||
instructions[0x0B] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x0C] = (Instruction) {"???", inst_NOP, ABS, 4};
|
||||
instructions[0x0D] = (Instruction) {"ORA abs", inst_ORA, ABS, 4};
|
||||
instructions[0x0E] = (Instruction) {"ASL abs", inst_ASL, ABS, 6};
|
||||
instructions[0x0F] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x10] = (Instruction) {"BPL rel", inst_BPL, REL, 2};
|
||||
instructions[0x11] = (Instruction) {"ORA ind,Y", inst_ORA, INDY, 5};
|
||||
instructions[0x12] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x13] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x14] = (Instruction) {"???", inst_NOP, ZP, 4};
|
||||
instructions[0x15] = (Instruction) {"ORA zpg,X", inst_ORA, ZPX, 4};
|
||||
instructions[0x16] = (Instruction) {"ASL zpg,X", inst_ASL, ZPX, 6};
|
||||
instructions[0x17] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x18] = (Instruction) {"CLC impl", inst_CLC, IMPL, 2};
|
||||
instructions[0x19] = (Instruction) {"ORA abs,Y", inst_ORA, ABSY, 4};
|
||||
instructions[0x1A] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x1B] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x1C] = (Instruction) {"???", inst_NOP, ABSX, 4};
|
||||
instructions[0x1D] = (Instruction) {"ORA abs,X", inst_ORA, ABSX, 4};
|
||||
instructions[0x1E] = (Instruction) {"ASL abs,X", inst_ASL, ABSX, 7};
|
||||
instructions[0x1F] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x20] = (Instruction) {"JSR abs", inst_JSR, ABS, 6};
|
||||
instructions[0x21] = (Instruction) {"AND X,ind", inst_AND, XIND, 6};
|
||||
instructions[0x22] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x23] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x24] = (Instruction) {"BIT zpg", inst_BIT, ZP, 3};
|
||||
instructions[0x25] = (Instruction) {"AND zpg", inst_AND, ZP, 3};
|
||||
instructions[0x26] = (Instruction) {"ROL zpg", inst_ROL, ZP, 5};
|
||||
instructions[0x27] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x28] = (Instruction) {"PLP impl", inst_PLP, IMPL, 4};
|
||||
instructions[0x29] = (Instruction) {"AND #", inst_AND, IMM, 2};
|
||||
instructions[0x2A] = (Instruction) {"ROL A", inst_ROL, ACC, 2};
|
||||
instructions[0x2B] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x2C] = (Instruction) {"BIT abs", inst_BIT, ABS, 4};
|
||||
instructions[0x2D] = (Instruction) {"AND abs", inst_AND, ABS, 4};
|
||||
instructions[0x2E] = (Instruction) {"ROL abs", inst_ROL, ABS, 6};
|
||||
instructions[0x2F] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x30] = (Instruction) {"BMI rel", inst_BMI, REL, 2};
|
||||
instructions[0x31] = (Instruction) {"AND ind,Y", inst_AND, INDY, 5};
|
||||
instructions[0x32] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x33] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x34] = (Instruction) {"???", inst_NOP, ZP, 4};
|
||||
instructions[0x35] = (Instruction) {"AND zpg,X", inst_AND, ZPX, 4};
|
||||
instructions[0x36] = (Instruction) {"ROL zpg,X", inst_ROL, ZPX, 6};
|
||||
instructions[0x37] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x38] = (Instruction) {"SEC impl", inst_SEC, IMPL, 2};
|
||||
instructions[0x39] = (Instruction) {"AND abs,Y", inst_AND, ABSY, 4};
|
||||
instructions[0x3A] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x3B] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x3C] = (Instruction) {"???", inst_NOP, ABSX, 4};
|
||||
instructions[0x3D] = (Instruction) {"AND abs,X", inst_AND, ABSX, 4};
|
||||
instructions[0x3E] = (Instruction) {"ROL abs,X", inst_ROL, ABSX, 7};
|
||||
instructions[0x3F] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x40] = (Instruction) {"RTI impl", inst_RTI, IMPL, 6};
|
||||
instructions[0x41] = (Instruction) {"EOR X,ind", inst_EOR, XIND, 6};
|
||||
instructions[0x42] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x43] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x44] = (Instruction) {"???", inst_NOP, ZP, 3};
|
||||
instructions[0x45] = (Instruction) {"EOR zpg", inst_EOR, ZP, 3};
|
||||
instructions[0x46] = (Instruction) {"LSR zpg", inst_LSR, ZP, 5};
|
||||
instructions[0x47] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x48] = (Instruction) {"PHA impl", inst_PHA, IMPL, 3};
|
||||
instructions[0x49] = (Instruction) {"EOR #", inst_EOR, IMM, 2};
|
||||
instructions[0x4A] = (Instruction) {"LSR A", inst_LSR, ACC, 2};
|
||||
instructions[0x4B] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x4C] = (Instruction) {"JMP abs", inst_JMP, ABS, 3};
|
||||
instructions[0x4D] = (Instruction) {"EOR abs", inst_EOR, ABS, 4};
|
||||
instructions[0x4E] = (Instruction) {"LSR abs", inst_LSR, ABS, 6};
|
||||
instructions[0x4F] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x50] = (Instruction) {"BVC rel", inst_BVC, REL, 2};
|
||||
instructions[0x51] = (Instruction) {"EOR ind,Y", inst_EOR, INDY, 5};
|
||||
instructions[0x52] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x53] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x54] = (Instruction) {"???", inst_NOP, ZP, 4};
|
||||
instructions[0x55] = (Instruction) {"EOR zpg,X", inst_EOR, ZPX, 4};
|
||||
instructions[0x56] = (Instruction) {"LSR zpg,X", inst_LSR, ZPX, 6};
|
||||
instructions[0x57] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x58] = (Instruction) {"CLI impl", inst_CLI, IMPL, 2};
|
||||
instructions[0x59] = (Instruction) {"EOR abs,Y", inst_EOR, ABSY, 4};
|
||||
instructions[0x5A] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x5B] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x5C] = (Instruction) {"???", inst_NOP, ABSX, 4};
|
||||
instructions[0x5D] = (Instruction) {"EOR abs,X", inst_EOR, ABSX, 4};
|
||||
instructions[0x5E] = (Instruction) {"LSR abs,X", inst_LSR, ABSX, 7};
|
||||
instructions[0x5F] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x60] = (Instruction) {"RTS impl", inst_RTS, IMPL, 6};
|
||||
instructions[0x61] = (Instruction) {"ADC X,ind", inst_ADC, XIND, 6};
|
||||
instructions[0x62] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x63] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x64] = (Instruction) {"???", inst_NOP, ZP, 3};
|
||||
instructions[0x65] = (Instruction) {"ADC zpg", inst_ADC, ZP, 3};
|
||||
instructions[0x66] = (Instruction) {"ROR zpg", inst_ROR, ZP, 5};
|
||||
instructions[0x67] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x68] = (Instruction) {"PLA impl", inst_PLA, IMPL, 4};
|
||||
instructions[0x69] = (Instruction) {"ADC #", inst_ADC, IMM, 2};
|
||||
instructions[0x6A] = (Instruction) {"ROR A", inst_ROR, ACC, 2};
|
||||
instructions[0x6B] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x6C] = (Instruction) {"JMP ind", inst_JMP, JMP_IND_BUG, 5};
|
||||
instructions[0x6D] = (Instruction) {"ADC abs", inst_ADC, ABS, 4};
|
||||
instructions[0x6E] = (Instruction) {"ROR abs", inst_ROR, ABS, 6};
|
||||
instructions[0x6F] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x70] = (Instruction) {"BVS rel", inst_BVS, REL, 2};
|
||||
instructions[0x71] = (Instruction) {"ADC ind,Y", inst_ADC, INDY, 5};
|
||||
instructions[0x72] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x73] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0x74] = (Instruction) {"???", inst_NOP, ZP, 4};
|
||||
instructions[0x75] = (Instruction) {"ADC zpg,X", inst_ADC, ZPX, 4};
|
||||
instructions[0x76] = (Instruction) {"ROR zpg,X", inst_ROR, ZPX, 6};
|
||||
instructions[0x77] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x78] = (Instruction) {"SEI impl", inst_SEI, IMPL, 2};
|
||||
instructions[0x79] = (Instruction) {"ADC abs,Y", inst_ADC, ABSY, 4};
|
||||
instructions[0x7A] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x7B] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x7C] = (Instruction) {"???", inst_NOP, ABSX, 4};
|
||||
instructions[0x7D] = (Instruction) {"ADC abs,X", inst_ADC, ABSX, 4};
|
||||
instructions[0x7E] = (Instruction) {"ROR abs,X", inst_ROR, ABSX, 7};
|
||||
instructions[0x7F] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0x80] = (Instruction) {"???", inst_NOP, IMM, 2};
|
||||
instructions[0x81] = (Instruction) {"STA X,ind", inst_STA, XIND, 6};
|
||||
instructions[0x82] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x83] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x84] = (Instruction) {"STY zpg", inst_STY, ZP, 3};
|
||||
instructions[0x85] = (Instruction) {"STA zpg", inst_STA, ZP, 3};
|
||||
instructions[0x86] = (Instruction) {"STX zpg", inst_STX, ZP, 3};
|
||||
instructions[0x87] = (Instruction) {"???", inst_NOP, IMPL, 3};
|
||||
instructions[0x88] = (Instruction) {"DEY impl", inst_DEY, IMPL, 2};
|
||||
instructions[0x89] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x8A] = (Instruction) {"TXA impl", inst_TXA, IMPL, 2};
|
||||
instructions[0x8B] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x8C] = (Instruction) {"STY abs", inst_STY, ABS, 4};
|
||||
instructions[0x8D] = (Instruction) {"STA abs", inst_STA, ABS, 4};
|
||||
instructions[0x8E] = (Instruction) {"STX abs", inst_STX, ABS, 4};
|
||||
instructions[0x8F] = (Instruction) {"???", inst_NOP, IMPL, 4};
|
||||
instructions[0x90] = (Instruction) {"BCC rel", inst_BCC, REL, 2};
|
||||
instructions[0x91] = (Instruction) {"STA ind,Y", inst_STA, INDY, 6};
|
||||
instructions[0x92] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0x93] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0x94] = (Instruction) {"STY zpg,X", inst_STY, ZPX, 4};
|
||||
instructions[0x95] = (Instruction) {"STA zpg,X", inst_STA, ZPX, 4};
|
||||
instructions[0x96] = (Instruction) {"STX zpg,Y", inst_STX, ZPY, 4};
|
||||
instructions[0x97] = (Instruction) {"???", inst_NOP, IMPL, 4};
|
||||
instructions[0x98] = (Instruction) {"TYA impl", inst_TYA, IMPL, 2};
|
||||
instructions[0x99] = (Instruction) {"STA abs,Y", inst_STA, ABSY, 5};
|
||||
instructions[0x9A] = (Instruction) {"TXS impl", inst_TXS, IMPL, 2};
|
||||
instructions[0x9B] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x9C] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x9D] = (Instruction) {"STA abs,X", inst_STA, ABSX, 5};
|
||||
instructions[0x9E] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0x9F] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0xA0] = (Instruction) {"LDY #", inst_LDY, IMM, 2};
|
||||
instructions[0xA1] = (Instruction) {"LDA X,ind", inst_LDA, XIND, 6};
|
||||
instructions[0xA2] = (Instruction) {"LDX #", inst_LDX, IMM, 2};
|
||||
instructions[0xA3] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0xA4] = (Instruction) {"LDY zpg", inst_LDY, ZP, 3};
|
||||
instructions[0xA5] = (Instruction) {"LDA zpg", inst_LDA, ZP, 3};
|
||||
instructions[0xA6] = (Instruction) {"LDX zpg", inst_LDX, ZP, 3};
|
||||
instructions[0xA7] = (Instruction) {"???", inst_NOP, IMPL, 3};
|
||||
instructions[0xA8] = (Instruction) {"TAY impl", inst_TAY, IMPL, 2};
|
||||
instructions[0xA9] = (Instruction) {"LDA #", inst_LDA, IMM, 2};
|
||||
instructions[0xAA] = (Instruction) {"TAX impl", inst_TAX, IMPL, 2};
|
||||
instructions[0xAB] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xAC] = (Instruction) {"LDY abs", inst_LDY, ABS, 4};
|
||||
instructions[0xAD] = (Instruction) {"LDA abs", inst_LDA, ABS, 4};
|
||||
instructions[0xAE] = (Instruction) {"LDX abs", inst_LDX, ABS, 4};
|
||||
instructions[0xAF] = (Instruction) {"???", inst_NOP, IMPL, 4};
|
||||
instructions[0xB0] = (Instruction) {"BCS rel", inst_BCS, REL, 2};
|
||||
instructions[0xB1] = (Instruction) {"LDA ind,Y", inst_LDA, INDY, 5};
|
||||
instructions[0xB2] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xB3] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0xB4] = (Instruction) {"LDY zpg,X", inst_LDY, ZPX, 4};
|
||||
instructions[0xB5] = (Instruction) {"LDA zpg,X", inst_LDA, ZPX, 4};
|
||||
instructions[0xB6] = (Instruction) {"LDX zpg,Y", inst_LDX, ZPY, 4};
|
||||
instructions[0xB7] = (Instruction) {"???", inst_NOP, IMPL, 4};
|
||||
instructions[0xB8] = (Instruction) {"CLV impl", inst_CLV, IMPL, 2};
|
||||
instructions[0xB9] = (Instruction) {"LDA abs,Y", inst_LDA, ABSY, 4};
|
||||
instructions[0xBA] = (Instruction) {"TSX impl", inst_TSX, IMPL, 2};
|
||||
instructions[0xBB] = (Instruction) {"???", inst_NOP, IMPL, 4};
|
||||
instructions[0xBC] = (Instruction) {"LDY abs,X", inst_LDY, ABSX, 4};
|
||||
instructions[0xBD] = (Instruction) {"LDA abs,X", inst_LDA, ABSX, 4};
|
||||
instructions[0xBE] = (Instruction) {"LDX abs,Y", inst_LDX, ABSY, 4};
|
||||
instructions[0xBF] = (Instruction) {"???", inst_NOP, IMPL, 4};
|
||||
instructions[0xC0] = (Instruction) {"CPY #", inst_CPY, IMM, 2};
|
||||
instructions[0xC1] = (Instruction) {"CMP X,ind", inst_CMP, XIND, 6};
|
||||
instructions[0xC2] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xC3] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0xC4] = (Instruction) {"CPY zpg", inst_CPY, ZP, 3};
|
||||
instructions[0xC5] = (Instruction) {"CMP zpg", inst_CMP, ZP, 3};
|
||||
instructions[0xC6] = (Instruction) {"DEC zpg", inst_DEC, ZP, 5};
|
||||
instructions[0xC7] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0xC8] = (Instruction) {"INY impl", inst_INY, IMPL, 2};
|
||||
instructions[0xC9] = (Instruction) {"CMP #", inst_CMP, IMM, 2};
|
||||
instructions[0xCA] = (Instruction) {"DEX impl", inst_DEX, IMPL, 2};
|
||||
instructions[0xCB] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xCC] = (Instruction) {"CPY abs", inst_CPY, ABS, 4};
|
||||
instructions[0xCD] = (Instruction) {"CMP abs", inst_CMP, ABS, 4};
|
||||
instructions[0xCE] = (Instruction) {"DEC abs", inst_DEC, ABS, 6};
|
||||
instructions[0xCF] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0xD0] = (Instruction) {"BNE rel", inst_BNE, REL, 2};
|
||||
instructions[0xD1] = (Instruction) {"CMP ind,Y", inst_CMP, INDY, 5};
|
||||
instructions[0xD2] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xD3] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0xD4] = (Instruction) {"???", inst_NOP, ZP, 4};
|
||||
instructions[0xD5] = (Instruction) {"CMP zpg,X", inst_CMP, ZPX, 4};
|
||||
instructions[0xD6] = (Instruction) {"DEC zpg,X", inst_DEC, ZPX, 6};
|
||||
instructions[0xD7] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0xD8] = (Instruction) {"CLD impl", inst_CLD, IMPL, 2};
|
||||
instructions[0xD9] = (Instruction) {"CMP abs,Y", inst_CMP, ABSY, 4};
|
||||
instructions[0xDA] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xDB] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0xDC] = (Instruction) {"???", inst_NOP, ABSX, 4};
|
||||
instructions[0xDD] = (Instruction) {"CMP abs,X", inst_CMP, ABSX, 4};
|
||||
instructions[0xDE] = (Instruction) {"DEC abs,X", inst_DEC, ABSX, 7};
|
||||
instructions[0xDF] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0xE0] = (Instruction) {"CPX #", inst_CPX, IMM, 2};
|
||||
instructions[0xE1] = (Instruction) {"SBC X,ind", inst_SBC, XIND, 6};
|
||||
instructions[0xE2] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xE3] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0xE4] = (Instruction) {"CPX zpg", inst_CPX, ZP, 3};
|
||||
instructions[0xE5] = (Instruction) {"SBC zpg", inst_SBC, ZP, 3};
|
||||
instructions[0xE6] = (Instruction) {"INC zpg", inst_INC, ZP, 5};
|
||||
instructions[0xE7] = (Instruction) {"???", inst_NOP, IMPL, 5};
|
||||
instructions[0xE8] = (Instruction) {"INX impl", inst_INX, IMPL, 2};
|
||||
instructions[0xE9] = (Instruction) {"SBC #", inst_SBC, IMM, 2};
|
||||
instructions[0xEA] = (Instruction) {"NOP impl", inst_NOP, IMPL, 2};
|
||||
instructions[0xEB] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xEC] = (Instruction) {"CPX abs", inst_CPX, ABS, 4};
|
||||
instructions[0xED] = (Instruction) {"SBC abs", inst_SBC, ABS, 4};
|
||||
instructions[0xEE] = (Instruction) {"INC abs", inst_INC, ABS, 6};
|
||||
instructions[0xEF] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0xF0] = (Instruction) {"BEQ rel", inst_BEQ, REL, 2};
|
||||
instructions[0xF1] = (Instruction) {"SBC ind,Y", inst_SBC, INDY, 5};
|
||||
instructions[0xF2] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xF3] = (Instruction) {"???", inst_NOP, IMPL, 8};
|
||||
instructions[0xF4] = (Instruction) {"???", inst_NOP, ZP, 4};
|
||||
instructions[0xF5] = (Instruction) {"SBC zpg,X", inst_SBC, ZPX, 4};
|
||||
instructions[0xF6] = (Instruction) {"INC zpg,X", inst_INC, ZPX, 6};
|
||||
instructions[0xF7] = (Instruction) {"???", inst_NOP, IMPL, 6};
|
||||
instructions[0xF8] = (Instruction) {"SED impl", inst_SED, IMPL, 2};
|
||||
instructions[0xF9] = (Instruction) {"SBC abs,Y", inst_SBC, ABSY, 4};
|
||||
instructions[0xFA] = (Instruction) {"???", inst_NOP, IMPL, 2};
|
||||
instructions[0xFB] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
instructions[0xFC] = (Instruction) {"???", inst_NOP, ABSX, 4};
|
||||
instructions[0xFD] = (Instruction) {"SBC abs,X", inst_SBC, ABSX, 4};
|
||||
instructions[0xFE] = (Instruction) {"INC abs,X", inst_INC, ABSX, 7};
|
||||
instructions[0xFF] = (Instruction) {"???", inst_NOP, IMPL, 7};
|
||||
}
|
||||
|
||||
void reset_cpu()
|
||||
void reset_cpu(int _a, int _x, int _y, int _sp, int _sr, int _pc)
|
||||
{
|
||||
A = 0;
|
||||
X = 0;
|
||||
Y = 0;
|
||||
SP = 0xFF;
|
||||
A = _a;
|
||||
X = _x;
|
||||
Y = _y;
|
||||
SP = _sp;
|
||||
|
||||
SR.byte = 0;
|
||||
SR.byte = _sr;
|
||||
SR.bits.interrupt = 1;
|
||||
SR.bits.unused = 1;
|
||||
|
||||
memcpy(&PC, &memory[RST_VEC], sizeof(PC));
|
||||
if (_pc < 0)
|
||||
memcpy(&PC, &memory[-_pc], sizeof(PC));
|
||||
else
|
||||
PC = _pc;
|
||||
|
||||
total_cycles = 0;
|
||||
}
|
||||
|
||||
int load_rom(char * filename)
|
||||
{ // TODO allow more flexible loading
|
||||
int load_rom(char * filename, int load_addr)
|
||||
{
|
||||
int loaded_size, max_size;
|
||||
|
||||
memset(memory, 0, sizeof(memory)); // clear ram first
|
||||
|
||||
FILE * fp = fopen(filename, "r");
|
||||
|
|
@ -857,33 +951,46 @@ int load_rom(char * filename)
|
|||
return -1;
|
||||
}
|
||||
|
||||
if (!fread(&memory[0xC000], 0x4000, 1, fp)) {
|
||||
printf("Error: ROM file too short.\n");
|
||||
return -1;
|
||||
}
|
||||
max_size = 0x10000 - load_addr;
|
||||
loaded_size = (int)fread(&memory[load_addr], 1, (size_t)max_size, fp);
|
||||
fprintf(stderr, "Loaded $%04x bytes: $%04x - $%04x\n", loaded_size, load_addr, load_addr + loaded_size - 1);
|
||||
|
||||
fclose(fp);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int step_cpu() // returns cycle count
|
||||
int step_cpu(int verbose) // returns cycle count
|
||||
{
|
||||
inst = instructions[memory[PC]];
|
||||
|
||||
#ifdef DEBUG
|
||||
printf("PC=%04X OPCODE=%02X: %s\r\n", PC, memory[PC], inst.mnemonic);
|
||||
printf("A=%02X X=%02X Y=%02X SR=%02X SP=%02X\r\n", A, X, Y, SR.byte, SP);
|
||||
|
||||
/* dump memory for analysis (slows down emulation significantly) */
|
||||
|
||||
FILE * fp = fopen("memdump", "w");
|
||||
fwrite(&memory, sizeof(memory), 1, fp);
|
||||
fclose(fp);
|
||||
#endif
|
||||
|
||||
if (verbose) {
|
||||
// almost match for NES dump for easier comparison
|
||||
printf("%04X ", PC);
|
||||
if (lengths[inst.mode] == 3)
|
||||
printf("%02X %02X %02X", memory[PC], memory[PC+1], memory[PC+2]);
|
||||
else if (lengths[inst.mode] == 2)
|
||||
printf("%02X %02X ", memory[PC], memory[PC+1]);
|
||||
else
|
||||
printf("%02X ", memory[PC]);
|
||||
printf(" %-10s A:%02X X:%02X Y:%02X P:%02X SP:%02X CYC:%3d\n", inst.mnemonic, A, X, Y, SR.byte, SP, (int)((total_cycles * 3) % 341));
|
||||
}
|
||||
|
||||
jumping = 0;
|
||||
extra_cycles = 0;
|
||||
inst.function();
|
||||
if (jumping == 0) PC += lengths[inst.mode];
|
||||
|
||||
return inst.cycles;
|
||||
|
||||
// 7 cycle instructions (e.g. ROL $nnnn,X) don't have a penalty cycle for
|
||||
// crossing a page boundary.
|
||||
if (inst.cycles == 7) extra_cycles = 0;
|
||||
|
||||
total_cycles += inst.cycles + extra_cycles;
|
||||
return inst.cycles + extra_cycles;
|
||||
}
|
||||
|
||||
void save_memory(char * filename) { // dump memory for analysis (slows down emulation significantly)
|
||||
if (filename == NULL) filename = "memdump";
|
||||
FILE * fp = fopen(filename, "w");
|
||||
fwrite(&memory, sizeof(memory), 1, fp);
|
||||
fclose(fp);
|
||||
}
|
||||
|
|
|
|||
15
6502.h
15
6502.h
|
|
@ -4,7 +4,7 @@
|
|||
#define CPU_FREQ 4e6 // 4Mhz
|
||||
#define STEP_DURATION 10e6 // 10ms
|
||||
#define ONE_SECOND 1e9
|
||||
#define NUM_MODES 13
|
||||
#define NUM_MODES 14
|
||||
|
||||
#define NMI_VEC 0xFFFA
|
||||
#define RST_VEC 0xFFFC
|
||||
|
|
@ -16,6 +16,8 @@ uint8_t X;
|
|||
uint8_t Y;
|
||||
uint16_t PC;
|
||||
uint8_t SP; // points to first empty stack location
|
||||
uint8_t extra_cycles;
|
||||
uint64_t total_cycles;
|
||||
|
||||
void * read_addr;
|
||||
void * write_addr;
|
||||
|
|
@ -51,7 +53,8 @@ typedef enum {
|
|||
REL,
|
||||
ZP,
|
||||
ZPX,
|
||||
ZPY
|
||||
ZPY,
|
||||
JMP_IND_BUG,
|
||||
} Mode;
|
||||
|
||||
typedef struct {
|
||||
|
|
@ -65,8 +68,10 @@ Instruction instructions[0x100];
|
|||
|
||||
void init_tables();
|
||||
|
||||
void reset_cpu();
|
||||
void reset_cpu(int _a, int _x, int _y, int _sp, int _sr, int _pc);
|
||||
|
||||
int load_rom(char * filename);
|
||||
int load_rom(char * filename, int load_addr);
|
||||
|
||||
int step_cpu();
|
||||
int step_cpu(int verbose);
|
||||
|
||||
void save_memory(char * filename);
|
||||
|
|
|
|||
|
|
@ -0,0 +1,40 @@
|
|||
#!/usr/bin/env python
|
||||
|
||||
# NES test rom: https://wiki.nesdev.com/w/index.php/Emulator_tests
|
||||
|
||||
# other tests:
|
||||
# https://github.com/Klaus2m5/6502_65C02_functional_tests
|
||||
# https://github.com/christopherpow/nes-test-roms
|
||||
|
||||
# other simulators:
|
||||
# http://piumarta.com/software/lib6502/
|
||||
# https://github.com/dennis-chen/6502-Emu/blob/master/src/cpu.c
|
||||
|
||||
# references
|
||||
# https://wiki.nesdev.com/w/index.php/Status_flags
|
||||
# http://www.emulator101.com/6502-addressing-modes.html
|
||||
# http://nesdev.com/6502.txt
|
||||
|
||||
# now passes the NES torture test, docs at http://www.qmtpro.com/~nes/misc/nestest.txt
|
||||
# NES ROM available at http://nickmass.com/images/nestest.nes
|
||||
# log for passing test available at http://www.qmtpro.com/~nes/misc/nestest.log
|
||||
|
||||
|
||||
# Format of test log from the NES test
|
||||
# C761 4C 68 C7 JMP $C768 A:40 X:00 Y:00 P:24 SP:FB CYC:195
|
||||
|
||||
|
||||
with open('test.log') as f1, open('test/nestest-real-6502.log') as f2:
|
||||
for i, (line1, line2) in enumerate(zip(f1, f2)):
|
||||
fail = False
|
||||
if line1[0:19] != line2[0:19]:
|
||||
fail = True
|
||||
if line1[48:81] != line2[48:81]:
|
||||
fail = True
|
||||
|
||||
if fail and "NOP" not in line2:
|
||||
print("first diff: line #%d: %s\ngen: %s\nnes: %s\n" % (i, line2[0:19], line1, line2))
|
||||
print(" gen: group 1: %s group 2: %s" % (line1[0:19], line1[48:81]))
|
||||
print(" nes: group 1: %s group 2: %s" % (line2[0:19], line2[48:81]))
|
||||
break
|
||||
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
echo "Running NES test"
|
||||
echo "***** Note: successful NES test will fail at the first illegal instruction, LAX at line 5259"
|
||||
./6502-emu -v -s 0xfd -r 0xc000 -c 300000 test/nestest-real-6502.rom > test.log; python compare.py
|
||||
echo
|
||||
echo "Running decimal mode test"
|
||||
./6502-emu -s 0xfd -c 3000000 -l 0x000a -r 0x1000 test/6502_functional_test+decimal.bin
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
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Reference in New Issue