articulate show

This commit is contained in:
Mark Canlas 2020-08-14 23:22:13 -04:00
parent 7ebd295e10
commit 8794f2ddea
4 changed files with 17 additions and 5 deletions

View File

@ -100,7 +100,7 @@ class CPU {
registers.A
def A_=[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit =
ctx.push(LDA, x, "set A to value " + ev.toAddressLiteral(x))
ctx.push(LDA, x, "set A to " + ev.toShow(x))
def A_=(reg: registers.DestinationA)(implicit ctx: AssemblyContext): Unit =
reg match {

View File

@ -8,6 +8,9 @@ object GlobalAddress {
val operandType: OperandType =
MemoryLocation
def toShow(x: GlobalAddress): String =
String.format("global address 0x%04x", x.n)
def toAddressLiteral(x: GlobalAddress): String =
String.format("$%04x", x.n)
}
@ -15,7 +18,7 @@ object GlobalAddress {
case class GlobalAddress(n: Int) {
def write[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit = {
ctx.push(LDA, x, s"write value ${ev.toAddressLiteral(x)} to address $n")
ctx.push(LDA, x, s"write ${ev.toShow(x)} to address $n")
ctx.push(STA, this, "")
}
}

View File

@ -5,6 +5,8 @@ import cats.Contravariant
trait Operand[A] {
def toAddressLiteral(x: A): String
def toShow(x: A): String
def operandType: OperandType
}
@ -14,6 +16,9 @@ object Operand {
val operandType: OperandType =
ValueLiteral
def toShow(x: Int): String =
x.toString
def toAddressLiteral(x: Int): String =
String.format("#$%02x", x)
}
@ -25,10 +30,11 @@ object Operand {
val operandType: OperandType =
fa.operandType
def toShow(x: B): String =
fa.toShow(f(x))
def toAddressLiteral(x: B): String =
fa.toAddressLiteral {
f(x)
}
fa.toAddressLiteral(f(x))
}
}
}

View File

@ -6,6 +6,9 @@ object ZeroAddress {
val operandType: OperandType =
MemoryLocation
def toShow(x: ZeroAddress): String =
String.format("global address 0x%02x", x.n)
def toAddressLiteral(x: ZeroAddress): String =
String.format("$%02x", x.n)
}