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@ -100,7 +100,7 @@ class CPU {
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registers.A
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def A_=[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit =
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ctx.push(LDA, x, "set A to value " + ev.toAddressLiteral(x))
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ctx.push(LDA, x, "set A to " + ev.toShow(x))
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def A_=(reg: registers.DestinationA)(implicit ctx: AssemblyContext): Unit =
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reg match {
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@ -8,6 +8,9 @@ object GlobalAddress {
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val operandType: OperandType =
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MemoryLocation
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def toShow(x: GlobalAddress): String =
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String.format("global address 0x%04x", x.n)
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def toAddressLiteral(x: GlobalAddress): String =
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String.format("$%04x", x.n)
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}
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@ -15,7 +18,7 @@ object GlobalAddress {
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case class GlobalAddress(n: Int) {
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def write[A](x: A)(implicit ctx: AssemblyContext, ev: Operand[A]): Unit = {
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ctx.push(LDA, x, s"write value ${ev.toAddressLiteral(x)} to address $n")
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ctx.push(LDA, x, s"write ${ev.toShow(x)} to address $n")
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ctx.push(STA, this, "")
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}
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}
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@ -5,6 +5,8 @@ import cats.Contravariant
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trait Operand[A] {
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def toAddressLiteral(x: A): String
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def toShow(x: A): String
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def operandType: OperandType
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}
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@ -14,6 +16,9 @@ object Operand {
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val operandType: OperandType =
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ValueLiteral
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def toShow(x: Int): String =
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x.toString
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def toAddressLiteral(x: Int): String =
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String.format("#$%02x", x)
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}
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@ -25,10 +30,11 @@ object Operand {
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val operandType: OperandType =
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fa.operandType
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def toShow(x: B): String =
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fa.toShow(f(x))
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def toAddressLiteral(x: B): String =
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fa.toAddressLiteral {
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f(x)
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}
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fa.toAddressLiteral(f(x))
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}
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}
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}
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@ -6,6 +6,9 @@ object ZeroAddress {
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val operandType: OperandType =
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MemoryLocation
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def toShow(x: ZeroAddress): String =
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String.format("global address 0x%02x", x.n)
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def toAddressLiteral(x: ZeroAddress): String =
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String.format("$%02x", x.n)
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}
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