From 9e81295fe1abe014b68ab0b69831be9fc91d6f59 Mon Sep 17 00:00:00 2001 From: Mark Canlas Date: Tue, 4 Oct 2022 14:55:25 -0400 Subject: [PATCH] start asm2 conversion --- .../com/htmlism/scratchpad/syntax/package.scala | 12 +++++++++++- .../scala/com/htmlism/scratchpad/FeatureSpec.scala | 10 +++++----- 2 files changed, 16 insertions(+), 6 deletions(-) diff --git a/scratchpad/src/main/scala/com/htmlism/scratchpad/syntax/package.scala b/scratchpad/src/main/scala/com/htmlism/scratchpad/syntax/package.scala index 2aff8c9..f828d4f 100644 --- a/scratchpad/src/main/scala/com/htmlism/scratchpad/syntax/package.scala +++ b/scratchpad/src/main/scala/com/htmlism/scratchpad/syntax/package.scala @@ -2,9 +2,19 @@ package com.htmlism.scratchpad package object syntax: implicit class WriteRegisterOps[Addr](reg: WriteAddress[Addr]): - def write[A: Loadable](x: A): syntax.PartiallyAppliedWrite[A, Addr] = + def writeConst[A: Loadable](x: A): syntax.PartiallyAppliedWrite[A, Addr] = new syntax.PartiallyAppliedWrite(reg, x) + def writeFrom[R: Store]: Asm2[R, Addr] = + val storeInstruction = + Store[R].to + + val storeStr = + s"$storeInstruction ${reg.n.toString}" + + // TODO encoding now already makes the structures lose semantic meaning + Asm2(List(s"$storeInstruction ${reg.n.toString}")) + class PartiallyAppliedWrite[Addr: Loadable, A](reg: WriteAddress[A], x: Addr): def apply[R: Load: Store: Register]: String = val literal = diff --git a/scratchpad/src/test/scala/com/htmlism/scratchpad/FeatureSpec.scala b/scratchpad/src/test/scala/com/htmlism/scratchpad/FeatureSpec.scala index b492862..da597e0 100644 --- a/scratchpad/src/test/scala/com/htmlism/scratchpad/FeatureSpec.scala +++ b/scratchpad/src/test/scala/com/htmlism/scratchpad/FeatureSpec.scala @@ -12,23 +12,23 @@ class ExampleRegister class FeatureSpec extends AnyFunSuite with Matchers: test("zero page address as write only supports writing") { ExampleRegister - .write(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A" + .writeConst(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A" } test("zero page address as read/write supports writing") { ExampleRegister - .write(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A" + .writeConst(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A" } test("writing to an address can use A, X, and Y registers for bouncing") { ExampleRegister - .write(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A" + .writeConst(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A" ExampleRegister - .write(2)[X] shouldBe "LDX 2 STX 1 ; example = 2, via X" + .writeConst(2)[X] shouldBe "LDX 2 STX 1 ; example = 2, via X" ExampleRegister - .write(2)[Y] shouldBe "LDY 2 STY 1 ; example = 2, via Y" + .writeConst(2)[Y] shouldBe "LDY 2 STY 1 ; example = 2, via Y" } ignore("the write payload is a typesafe enum") {}