From a3d85136123e91df016ce54e52ec21be39bb3705 Mon Sep 17 00:00:00 2001 From: Mark Canlas Date: Tue, 16 Jan 2024 20:10:31 -0500 Subject: [PATCH] outline specs --- .../firepower/core/RegisterAllocatorSuite.scala | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/firepower-core/src/test/scala/com/htmlism/firepower/core/RegisterAllocatorSuite.scala b/firepower-core/src/test/scala/com/htmlism/firepower/core/RegisterAllocatorSuite.scala index 8ddbeec..22b6694 100644 --- a/firepower-core/src/test/scala/com/htmlism/firepower/core/RegisterAllocatorSuite.scala +++ b/firepower-core/src/test/scala/com/htmlism/firepower/core/RegisterAllocatorSuite.scala @@ -3,6 +3,14 @@ package com.htmlism.firepower.core import weaver.FunSuite object RegisterAllocatorSuite extends FunSuite: - // TODO test("cam allocate registers"): - expect.eql(1, 1) + expect.eql("TODO", "TODO") + + test("A register can be allocated to a single byte width"): + expect.eql("TODO", "TODO") + + test("Allocates CPU registers first, then zero page, then global"): + expect.eql("TODO", "TODO") + + test("A register can be allocated to a two-byte width, always a memory register"): + expect.eql("TODO", "TODO")