add comment/intuition

This commit is contained in:
Mark Canlas 2022-08-03 15:24:08 -04:00
parent 4aa50a3741
commit c8a5325ed2
3 changed files with 24 additions and 22 deletions

View File

@ -1,15 +1,8 @@
package com.htmlism.scratchpad
object Address:
def zero(n: Int): ZeroPageAddress =
ZeroPageAddress(n % 256)
case class ZeroPageAddress(n: Int, alias: String)
def absolute(n: Int): GlobalAddress =
GlobalAddress(n % (256 * 256))
case class ZeroPageAddress(n: Int)
case class GlobalAddress(n: Int)
case class GlobalAddress(n: Int, alias: String)
sealed trait ReadAddress:
def addr: ZeroPageAddress

View File

@ -7,10 +7,19 @@ package object syntax:
class PartiallyAppliedWrite[A: Loadable](reg: WriteAddress, x: A):
def apply[B: Register]: String =
val literal =
summon[Loadable[A]].show(x)
val register =
summon[Register[B]].self
val first =
"LD" + summon[Register[B]].self + " " + summon[Loadable[A]].show(x)
s"LD$register $literal"
val second =
"ST" + summon[Register[B]].self + " " + reg.addr.n.toString
s"ST$register ${reg.addr.n.toString}"
first + " " + second
val desc =
s"${reg.addr.alias} = $literal, via $register"
s"$first $second ; $desc"

View File

@ -7,24 +7,24 @@ import com.htmlism.scratchpad.syntax._
class FeatureSpec extends AnyFunSuite with Matchers:
test("zero page address as write only supports writing") {
WriteOnlyAddress(Address.zero(0x01))
.write(2)[A] shouldBe "LDA 2 STA 1"
WriteOnlyAddress(ZeroPageAddress(0x01, "example"))
.write(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A"
}
test("zero page address as read/write supports writing") {
ReadWriteAddress(Address.zero(0x01))
.write(2)[A] shouldBe "LDA 2 STA 1"
ReadWriteAddress(ZeroPageAddress(0x01, "example"))
.write(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A"
}
test("writing to an address can use A, X, and Y registers for bouncing") {
ReadWriteAddress(Address.zero(0x01))
.write(2)[A] shouldBe "LDA 2 STA 1"
ReadWriteAddress(ZeroPageAddress(0x01, "example"))
.write(2)[A] shouldBe "LDA 2 STA 1 ; example = 2, via A"
ReadWriteAddress(Address.zero(0x01))
.write(2)[X] shouldBe "LDX 2 STX 1"
ReadWriteAddress(ZeroPageAddress(0x01, "example"))
.write(2)[X] shouldBe "LDX 2 STX 1 ; example = 2, via X"
ReadWriteAddress(Address.zero(0x01))
.write(2)[Y] shouldBe "LDY 2 STY 1"
ReadWriteAddress(ZeroPageAddress(0x01, "example"))
.write(2)[Y] shouldBe "LDY 2 STY 1 ; example = 2, via Y"
}
ignore("the write payload is a typesafe enum") {}