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https://github.com/mcanlas/6502-opcodes.git
synced 2025-01-20 10:33:46 +00:00
trim types; use cats
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parent
e432132328
commit
e5a2830be6
@ -6,3 +6,4 @@ lazy val root =
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libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.1" % "test",
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libraryDependencies += "org.scalatest" %% "scalatest" % "3.2.1" % "test",
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scalafmtOnCompile := true
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scalafmtOnCompile := true
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)
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)
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.withCats
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@ -7,4 +7,12 @@ object ProjectPlugin extends AutoPlugin {
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override lazy val projectSettings = Seq(
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override lazy val projectSettings = Seq(
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scalaVersion := "2.13.3"
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scalaVersion := "2.13.3"
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)
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)
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object autoImport {
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implicit class ProjectOps(p: Project) {
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def withCats: Project =
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p
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.settings(libraryDependencies += "org.typelevel" %% "cats-core" % "2.2.0-RC2")
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}
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}
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}
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}
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@ -1,5 +1,7 @@
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package com.htmlism
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package com.htmlism
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import cats.implicits._
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import java.io.PrintWriter
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import java.io.PrintWriter
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object MatchOpcodes {
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object MatchOpcodes {
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@ -222,41 +224,41 @@ object MatchOpcodes {
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n match {
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n match {
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case BitPattern(aaabbb, cc) =>
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case BitPattern(aaabbb, cc) =>
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cc match {
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cc match {
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case 0 => (c00 _).tupled(aaabbb)
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case 0 => (c00 _).tupled(aaabbb).some
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case 1 => (c01 _).tupled(aaabbb)
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case 1 => (c01 _).tupled(aaabbb).some
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case 2 => (c10 _).tupled(aaabbb)
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case 2 => (c10 _).tupled(aaabbb).some
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case 3 => None
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case 3 => None
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}
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}
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}
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}
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}
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}
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def c01(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
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def c01(aaa: Int, bbb: Int): (Instruction, AddressingMode) = {
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val instruction =
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val instruction =
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Seq(ORA, AND, EOR, ADC, STA, LDA, CMP, SBC)(aaa)
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Seq(ORA, AND, EOR, ADC, STA, LDA, CMP, SBC)(aaa)
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val addressingMode =
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val addressingMode =
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Seq(IndirectX, ZeroPage, Immediate, Absolute, IndirectY, ZeroPageX, AbsoluteY, AbsoluteX)(bbb)
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Seq(IndirectX, ZeroPage, Immediate, Absolute, IndirectY, ZeroPageX, AbsoluteY, AbsoluteX)(bbb)
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Some(instruction -> addressingMode)
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instruction -> addressingMode
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}
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}
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def c10(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
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def c10(aaa: Int, bbb: Int): (Instruction, AddressingMode) = {
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val instruction =
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val instruction =
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Seq(ASL, ROL, LSR, ROR, STX, LDX, DEC, INC)(aaa)
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Seq(ASL, ROL, LSR, ROR, STX, LDX, DEC, INC)(aaa)
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val addressingMode =
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val addressingMode =
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Seq(Immediate, ZeroPage, Accumulator, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
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Seq(Immediate, ZeroPage, Accumulator, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
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Some(instruction -> addressingMode)
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instruction -> addressingMode
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}
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}
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def c00(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
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def c00(aaa: Int, bbb: Int): (Instruction, AddressingMode) = {
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val instruction =
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val instruction =
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Seq(NoInstruction, BIT, JMP, JMP, STY, LDY, CPY, CPX)(aaa)
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Seq(NoInstruction, BIT, JMP, JMP, STY, LDY, CPY, CPX)(aaa)
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val addressingMode =
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val addressingMode =
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Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
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Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
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Some(instruction -> addressingMode)
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instruction -> addressingMode
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}
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}
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}
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}
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