diff --git a/src/main/scala/com/htmlism/AddressingMode.scala b/src/main/scala/com/htmlism/AddressingMode.scala
index e0c79c3..ab0e927 100644
--- a/src/main/scala/com/htmlism/AddressingMode.scala
+++ b/src/main/scala/com/htmlism/AddressingMode.scala
@@ -8,9 +8,10 @@ case object ZeroPageX   extends AddressingMode
 case object Absolute    extends AddressingMode
 case object AbsoluteX   extends AddressingMode
 case object AbsoluteY   extends AddressingMode
+case object Indirect    extends AddressingMode // used by jump
 case object IndirectX   extends AddressingMode
 case object IndirectY   extends AddressingMode
-case object Relative    extends AddressingMode
+case object Relative    extends AddressingMode // used by branches
 case object Accumulator extends AddressingMode
 case object Implied     extends AddressingMode
 case object NoMode      extends AddressingMode
diff --git a/src/main/scala/com/htmlism/MatchOpcodes.scala b/src/main/scala/com/htmlism/MatchOpcodes.scala
index bf60370..a15ccf9 100644
--- a/src/main/scala/com/htmlism/MatchOpcodes.scala
+++ b/src/main/scala/com/htmlism/MatchOpcodes.scala
@@ -18,6 +18,12 @@ object MatchOpcodes {
       .toMap
 
   // format: off
+  def injectedOpcodesJump: Map[Int, (Instruction, AddressingMode)] =
+    Map(
+      0x4C -> (JMP -> Absolute),
+      0x6C -> (JMP -> Indirect),
+    )
+
   def injectedOpcodesRelative: Map[Int, (Instruction, AddressingMode)] =
     Map(
       0x10 -> BPL,
@@ -68,7 +74,8 @@ object MatchOpcodes {
     val lookup =
       generatedOpcodes ++
         injectedOpcodesImplied ++
-        injectedOpcodesRelative
+        injectedOpcodesRelative ++
+        injectedOpcodesJump
 
     out.print("<table>")
 
@@ -263,12 +270,24 @@ object MatchOpcodes {
 
   def c00(aaa: Int, bbb: Int): Option[(Instruction, AddressingMode)] = {
     val instruction =
-      Seq(NoInstruction, BIT, JMP, JMP, STY, LDY, CPY, CPX)(aaa)
+      Seq(NoInstruction, BIT, NoInstruction, NoInstruction, STY, LDY, CPY, CPX)(aaa)
 
     val addressingMode =
-      Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
+      instruction match {
+        case BIT =>
+          Seq(NoMode, ZeroPage, NoMode, Absolute, NoMode, NoMode, NoMode, NoMode)(bbb)
 
-    if (addressingMode == NoMode)
+        case STY =>
+          Seq(NoMode, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, NoMode)(bbb)
+
+        case LDY =>
+          Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, ZeroPageX, NoMode, AbsoluteX)(bbb)
+
+        case _ =>
+          Seq(Immediate, ZeroPage, NoMode, Absolute, NoMode, NoMode, NoMode, NoMode)(bbb)
+      }
+
+    if (instruction == NoInstruction || addressingMode == NoMode)
       None
     else
       (instruction -> addressingMode).some