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4 Commits

Author SHA1 Message Date
Mark Canlas 29efb32781 index register 2024-01-17 10:08:52 -05:00
Mark Canlas a3d8513612 outline specs 2024-01-16 20:10:31 -05:00
Mark Canlas ae459a3334 register allocator stub 2024-01-16 19:47:51 -05:00
Mark Canlas bf67f5fc29 register allocation 2024-01-16 19:26:46 -05:00
2 changed files with 24 additions and 2 deletions

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@ -1,5 +1,8 @@
- it would be cool for the generated code writer to go to files
- and make the +1 methods optional (for when it is at max)
- normalize A, X, Y, ZP, and GP to "registers", allocated by an allocator
- X and Y are also index registers, so slightly special
- unit test: what if a for loop is three deep? the outermost loop must be a memory register
- it would be cool for the 22-tuple Scala code generator code writer to go to files
- and make the +1 methods optional (for when it is at max == 22)
- the payload/`xs` of a program should be an ADT of either chunks or one instruction
- where a chunk is just many instructions
- and an instruction already has the value X with its encoder, but chooses an eternal mode

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@ -0,0 +1,19 @@
package com.htmlism.firepower.core
import weaver.FunSuite
object RegisterAllocatorSuite extends FunSuite:
test("cam allocate registers"):
expect.eql("TODO", "TODO")
test("A register can be allocated to a single byte width"):
expect.eql("TODO", "TODO")
test("Allocates CPU registers first, then zero page, then global"):
expect.eql("TODO", "TODO")
test("A single-byte register can specifically be an index register"):
expect.eql("TODO", "TODO")
test("A register can be allocated to a two-byte width, always a memory register"):
expect.eql("TODO", "TODO")