From 12434a8e4782ee8fd6d578f8ba3bfe8cbcbea84b Mon Sep 17 00:00:00 2001 From: Klaus2m5 Date: Wed, 7 Aug 2013 18:56:09 +0200 Subject: [PATCH] first commit --- .gitattributes | 22 + .gitignore | 215 ++ 6502_65C02_functional_tests.zip | Bin 0 -> 48874 bytes 6502_functional_test.a65 | 5597 ++++++++++++++++++++++++++++++ 6502_interrupt_test.a65 | 969 ++++++ 65C02_extended_opcodes_test.a65c | 2664 ++++++++++++++ license.txt | 674 ++++ readme.txt | 27 + 8 files changed, 10168 insertions(+) create mode 100644 .gitattributes create mode 100644 .gitignore create mode 100644 6502_65C02_functional_tests.zip create mode 100644 6502_functional_test.a65 create mode 100644 6502_interrupt_test.a65 create mode 100644 65C02_extended_opcodes_test.a65c create mode 100644 license.txt create mode 100644 readme.txt diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..412eeda --- /dev/null +++ b/.gitattributes @@ -0,0 +1,22 @@ +# Auto detect text files and perform LF normalization +* text=auto + +# Custom for Visual Studio +*.cs diff=csharp +*.sln merge=union +*.csproj merge=union +*.vbproj merge=union +*.fsproj merge=union +*.dbproj merge=union + +# Standard to msysgit +*.doc diff=astextplain +*.DOC diff=astextplain +*.docx diff=astextplain +*.DOCX diff=astextplain +*.dot diff=astextplain +*.DOT diff=astextplain +*.pdf diff=astextplain +*.PDF diff=astextplain +*.rtf diff=astextplain +*.RTF diff=astextplain diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b9d6bd9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,215 @@ +################# +## Eclipse +################# + +*.pydevproject +.project +.metadata +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.classpath +.settings/ +.loadpath + +# External tool builders +.externalToolBuilders/ + +# Locally stored "Eclipse launch configurations" +*.launch + +# CDT-specific +.cproject + +# PDT-specific +.buildpath + + +################# +## Visual Studio +################# + +## Ignore Visual Studio temporary files, build results, and +## files generated by popular Visual Studio add-ons. + +# User-specific files +*.suo +*.user +*.sln.docstates + +# Build results + +[Dd]ebug/ +[Rr]elease/ +x64/ +build/ +[Bb]in/ +[Oo]bj/ + +# MSTest test Results +[Tt]est[Rr]esult*/ +[Bb]uild[Ll]og.* + +*_i.c +*_p.c +*.ilk +*.meta +*.obj +*.pch +*.pdb +*.pgc +*.pgd +*.rsp +*.sbr +*.tlb +*.tli +*.tlh +*.tmp +*.tmp_proj +*.log +*.vspscc +*.vssscc +.builds +*.pidb +*.log +*.scc + +# Visual C++ cache files +ipch/ +*.aps +*.ncb +*.opensdf +*.sdf +*.cachefile + +# Visual Studio profiler +*.psess +*.vsp +*.vspx + +# Guidance Automation Toolkit +*.gpState + +# ReSharper is a .NET coding add-in +_ReSharper*/ +*.[Rr]e[Ss]harper + +# TeamCity is a build add-in +_TeamCity* + +# DotCover is a Code Coverage Tool +*.dotCover + +# NCrunch +*.ncrunch* +.*crunch*.local.xml + +# Installshield output folder +[Ee]xpress/ + +# DocProject is a documentation generator add-in +DocProject/buildhelp/ +DocProject/Help/*.HxT +DocProject/Help/*.HxC +DocProject/Help/*.hhc +DocProject/Help/*.hhk +DocProject/Help/*.hhp +DocProject/Help/Html2 +DocProject/Help/html + +# Click-Once directory +publish/ + +# Publish Web Output +*.Publish.xml +*.pubxml + +# NuGet Packages Directory +## TODO: If you have NuGet Package Restore enabled, uncomment the next line +#packages/ + +# Windows Azure Build Output +csx +*.build.csdef + +# Windows Store app package directory +AppPackages/ + +# Others +sql/ +*.Cache +ClientBin/ +[Ss]tyle[Cc]op.* +~$* +*~ +*.dbmdl +*.[Pp]ublish.xml +*.pfx +*.publishsettings + +# RIA/Silverlight projects +Generated_Code/ + +# Backup & report files from converting an old project file to a newer +# Visual Studio version. Backup files are not needed, because we have git ;-) +_UpgradeReport_Files/ +Backup*/ +UpgradeLog*.XML +UpgradeLog*.htm + +# SQL Server files +App_Data/*.mdf +App_Data/*.ldf + +############# +## Windows detritus +############# + +# Windows image file caches +Thumbs.db +ehthumbs.db + +# Folder config file +Desktop.ini + +# Recycle Bin used on file shares +$RECYCLE.BIN/ + +# Mac crap +.DS_Store + + +############# +## Python +############# + +*.py[co] + +# Packages +*.egg +*.egg-info +dist/ +build/ +eggs/ +parts/ +var/ +sdist/ +develop-eggs/ +.installed.cfg + +# Installer logs +pip-log.txt + +# Unit test / coverage reports +.coverage +.tox + +#Translations +*.mo + +#Mr Developer +.mr.developer.cfg diff --git a/6502_65C02_functional_tests.zip b/6502_65C02_functional_tests.zip new file mode 100644 index 0000000000000000000000000000000000000000..ef06f3a58fd0a2d96456993bf79585590c9a3c0f GIT binary patch literal 48874 zcmXtfV{|4wv~{hiZQHhO+vc>L_Ni^#wr$(CZQGjm&U?S_{y0hYIXhX&Uip!%lPJo7 zf}sKd0YL%TguV(dg?L&9hynp=lYjtW{`0c4F)|yNJKLE!S=rke{Wfqi131wev9n$2 z{b+28xBT#(9{Hx(Jt9-O++j#IOisQaCA9ojG4y{S-10olYKp`@w_Zpw06ySTSPnf^k)el-ekn)7RsZ})&Ho+6x$a&f(7?^ zA(=&SSR*jtiGSsY4?@}J_7CgIA&4dU@nU`n5bAs;teeHy#s8x0c?Mx{ggCHtBZ@Iv8FAtU(0C zV?mQ6~JPJ0;7)n*%tVFb2q9|?|G;6b$fGvf75?Hil>Ti5Yl$3 z=Z>5tfD7j(2w@P95`_|{fav4q+VzT;an-Z#+w1#*BpYV`qJXfIofT#eADe$zxP7?z zx0_)17C*9(AT}0WVTTXnVCWHw5@-s=A-5Tf>7}dw5W#r*O@fjg!Z|Rf&8dc$a_#wx zX6^(E<3**K7vunTU@u@@)Qm(Dv2_&%sCk)kM{soUS!- z0oYJtk~RfGmLB*)eH6}valbL2n~+(GTy`~pViT1WCj30#a38{4BJh0o(?M_ei6Coe z0hX)iqc$spj;iy@sq3?VZ=hmS)~_ef*>hk>=U-2n0|p2~&AX3Izv@?RT!KB%MKkR< zHESXM;JqLH38?1)0#=!Sg>=G-6@s<8-a^QtEcZKy{)N)f7^^zDEUyihuyx0xz3?k~j@!DWYRnIZ$&Syz*7LZbpu>J(HFVt5>u(HqIEpf^f4MZ} z+~5tZ1uzV2TyC9N?s3&i>QhAVLaUp=f-L{-|1$Ad8-LB!-ce@bRed6W{JiP`Kug zrTKgMi}0yZ$3kECr^ofBW5%6=c07;}4KTn0fQmvX7UY8a3Eu-?Es%r$_S}BJzf)b$ z=0tAm&r-N#XT|>NvO#HF2?_RxN1^QC^9OhP1xC^6DEF`_t?RwVr9V0Bp zOovqw%GgL|x$``j-qBHgBpxFs_pi&2%pIC75corXpvr$YZbS<1|Kq>!<>(;v(Hn#} z>bvND5z2^f;}MSM=5#Y>fWHUsu1xl)49gU)c>(x6)9otN|Apa)BFuNeS< zV1izr^X9}3J`0U7l5!F8+N*hDa&}2bbc5YAqHkKaOk8Orrc@IYNsj9)_w{`GuAsSe)}aE? zLnxVlWgtfyRC_n0wQ1duvv7>Bo<5;HgpUXHM5rD27Hcb@gu15ojojsHC_q)71;ClW zAh%1O%PO70c~lWBL=;A-UCIN_M6(jlRwQm+izCK_C==t7H)%z*w2;FtMneTGPbqj% zAW0rDQgdLnEyl*O8*>QqQ{3pxCz2h?;cuxQfhFNNlPI2(S4#zjLXIQ~6xguz**h2R zVqAUq{M>;J5+vQ2y|)hU=QuDiyd#;A8_fB{6VM@3W=Lfg5aKy7Y^qm<))22(!!cBt z4_+Iq7W+bvicR1TqYK6@X}gJbS&%@l@z!{>Bqwe&4{za;niz5v7W{*x4Oq13ng5Q) zHZ1j^+xpSNWLpx1Xy9AmEud9^`MvFL38~|fURH2T(a@2&@*d0}Qw4;`7mPa^;E(i+HeAY&@LNL9`hq)^K&S#i3W0G_+1>QTNUxjLJiaN# zGYsE+W2M_*YliDIxh!(R-Zl8~22r1PL71iTKRB(o3W~h4WwHWIBsjwskWfOF85af5 z;iAas%c%S!9w0heBVllTuruIA^SphPisW_!$xtnV*NYN4Q1$Oii@=r&V;e_WyA&ok z0qJX!xgVMvRHXAqz&^a?ENYRot+@|vsDs_J??1+3hMB;HrZh%$5~}LCO!xx zHM1XWuSAQa{^LDKMK0P&3hIgcPH}=&W!sCc`5Tk7Zq9aiI5Y_Ps2OikKVpWdbag-+ z6OsF#ZwP-dI~@U6n66EWK_&hsV)ZIR3qM;}-0C$(?wXwYO!E1H;ciqZ_Q72cVJ^vg zN0_BN<>L64<|sXug%Z8{2;u2(+?YN)6g#r!UvV(#%eUG3l!FD2&<$Ndr-2W~G1Ryn z>Aq;Cxfe$9xcf(i9ZUWU0Qjbt68Pv$%F+Cdph#fzsl8Rq>I4=DpAjiPjPlKi?~sb; z^w-Sgk1X-G+^=~C0}B{7>S?{*d#MygAy}}Lvc`lWGZq}Q?^dV<&=MuigpkueBb98E zGgP@)gHMzJPzLa*5-42L%zua{EY4G~XC+DW3$duVhOQk?qgL~Ene{;?af`bEc>&pR zCC=7Fer_`*gnw1v#<+SK#Kand@7f!3kmQ7*%i$HD)QY=g1i^E_ zVZ_Mt#yHtHFN_<7I_klZ#morxrUc1Z|Ej@{Ht)9q_S)toRAH>nbmA0MA)p%(P|2x0 zdPxT+xNzZU-6*L8Ik1cNNWG7NYJbP;B}dW@r4_~2@T*vBv@9vIBB-|SC54tZsW;f= z4*|Z`l@7wODsnt`9F+otX z4pK*&QK99U$bL$J?km&B@V<@HsL2*LXu^o16{@1iWGW6O4J>m^m-OyNe@$s#!j zlG*hvgi!Y~vymB7cTy#tPxzNl9Vy0VGHlF|f^od#P(|Ua(sNYTz*Ms;wVei?^QD}H zpb}o@KA*tuRZya7Ji zX@kiG8~RGmgUY-96}$wp92fo;xSqFeT}sz%!yU;f>C+nLc$2kmGk!0q#K9}GpS35jzK;>-z(KN;P0IM_}M6TPBkhvxeb~r`+9ENN+KpQ z))8J%kbA=(x^P^l#sqMAt4~4iw~p5PuF{B>eO>f9CGJ?%IrFzkrgEv;!|G3OLg(5p z+!VQ`vu7=9u@b2@e2(+NjG z6Z(%}V{Dn=Yw7BBB&*6dp}AJj0x&;Lz$pokL(0sV#iqb1Syp%{T{+DBjZ1C>yxeDi z==1BTIVpVZ!0~I$u5z;^!#ndQt+m9DLTy!@&ud*ZYxswe$Uk~Utw5`3{6Id*cc+ir znnTcBrw)AHlalX1ri9S-T#yuzWw^_w04#}M$l^yXuT_n9sUS+Ns$}T>(F|#V(fg<* zsJaySaPd?UlG3&I1;-ZaWEm92db9q_<==an(6;X1#pL01TnF|>ie`6f?xpXNR`JkN z2`M{y2awd-lJ{zo7UE=)GB9Tl*#l~k$5HFrDb|toD!)#Ijgty8S5UT9UE+9>cPu~b z8M=#do)Xj~8Qxn{^{wzL@$R!-4H$>)e9e$$BzAk9WEfqU(^MXQ4qH=N{tU{-L7=k9A}-t62KwC-m4m=YpJ z*hHtO-`MszAL^o#y3HBLXZ&q9-;9;UeIu$Pw49Ft85wsEa7Q_eOyllogD=e4yWX_! zJfb{mu7cR!J}Y|F+i7FNIyrfIHZSXaG^ea_3~5*rg;B7vZ?H`8kR3BJYVFc9RL3SW zsO{3XUW!QMddMTl$RD>J0D7MwGLlkCpQAyx6T%NN=hxkFIi^dd@jk|TGZr4!EZ4sb zN$s}&9@}&?%%fScEN)Ii5UJjLJvjGlA#4SNWJ}uFv0=BAr^K-a5mP_0NNGTOrux`v zoN?=r9#+^UsF1hmF_Z8?VR1qu`kj|S)xXnMn+%3p}l$--TltWxsIdYp|t{RvtWdRK#S8mrc4nz92+uMAyTRZ z)=(}KOg;jmhU>PDPPlvkM4IR-V97yVmo*ITp=rifS^N(Gn+~R$RFs5jirhw+V=53` z+&iHX6DN=pO(ne}|7PMKkzFBBR(XnXGvaZ+xhqX7tB|OIB0YJ{^s4cdp_VOhIyXm4 z6>|3Vy9UtOE-Zx^qt_cvg3TkA$qPeldbN)3aYxK~P+Z-1hV65sPt*8yud;mhi!i!8 z6%^I1Wzqc6X!DmnlI9E5)&X}XKEF*?8Js0f?5W>XTNNitH%``U29AxBVj1BY#?kKj zr!9XkS{A_IeXRE%AMxc`zeHD-R48n%7-$8DPn$JUAuH#npWel*7e`}FbHsnB=W~DE z4_&k8bX~CK{BFjno%I;VUag!LDm!u`BrX2y`E#jc*7gd$ z6VkqXyi;U5sIs+;+gB!|i-eZPD#ijIEPs(NF1ph;#Es7KEJHYxU%iic475<(T_E`?bJP6fB_2)r1_sLVCEXrI6OF>RBm47 z1B=xE$Ww|jDPow$4Qbiipr9bVr;Q>mjbSq`2w_B>bt>v>W*$3u8Ny#V3J6%o#7|v3 zq#joT@>2N)kWdT4Up09aOpfre;kf@xr4uhD{!YWK-j&jM&XO;7FTrn2+Irjai=4Ib zn{3wu^}Ifs-r-hBbz)v(W69ieeG7+%`jAXpS7&qUrj}pIbC-_(U9%C7z!b`WX5s03YOdW`;OS2S#OW!o|;4p6(3n& zg}Z>|-j8~ruS!M|Ban5-irXKt+?N7z(a>+zV-eL?D!`noLtT8mQtKh+Hl*FN@S!0wmGqc8Z)`q`ZU9dm95O3iUNa_)Gdmc z{wV=`?1oq+Ula)F{PWRmqeGk`*XO&Ji0j||IpW0)%oB5djke)YS`vS!TW??dxECA1 zqY?n-<0Zg9u!q%EIJN%HU0#7oO9 zTFbxLGBwu3l`TiDYH~G88BV|F31z9+gb#GQy(@hSv*ZZ73&IW31D8B1w!v8Fnfjw< z$1azHzN7;><{oKeeSVR+us{pZU5zJy(ZZLJyGmSQpQy%ScVa6Z?eAt~tu2CH!@|$D zmaqVA#EBq2HH}@pr!rt#I?UiPX1;~`%^ytWxw^0@Cnyd_Tjl7bGnvZ78y?MeGbe%2 z69?DN$I|k5n0q}Hf)#ctL6+vIDkG2aR}GzbXU08xi^mX9|MZ+7vA#^W{5ls@y)Oe?93V`IEzMGiWuQY%(=&93Gzd<8js9^d~K^Q;RK(` z3ImEW+l!}k6U;Iv_!lXb)yO@_CjEx_q5WLznnFv4r5rr9ZrNo#UL13}lPnkx*Ja!Q zDYsX}Jf7=zI|BE^iwDWp~RKG_avb4;Fi(zrXe%$}A{gMU$DD&>XOx0T= zx{4*(-bU6nH?tZq=1^?X({yPxt#_8u`du!@E`xsO(yFQ5nBJPY^!v9<>LmQ<(;!Z_ z@{iF9fSJIh$h>f@FJEHa)MCL6@#|z;;1{>Y!t0ashS!bW#a(Ebv@S{S8eDm(C{Q8VPB<1G@ zl|^2A4~ZSLOI(+fmS5CQo*zVHQx=ks24!$oCK4jff{9?vIf*&tr@eVNjiLK*K`+C$Pwf_Jlu=sw83sIJ(3IFmfa|rM zB*7z<;&l1$Xy3C}56(fo?{RE-q1S1b(`3s8u?LZ$JH!+Hnim)bT48NAoSM4=NtI9F zg(VL+*1ymD@lO~3?BSms?8i6#y_4MVa3gglz?VXp_pMDRDiC+l4p1`PZ%iDg+n2_y^hTqq6Z#)?_{rMHdU0Z6<7w1X8 zi`&DlPBoB$0Un`VvHY(}z|Xn1=jBDHzrXuB8ySpb$3b8qx99DeGCSNqcKru_?YQ{` z21i43mThS6@1f*tB76#1nKB&5Ws(;^hi&@E(`k&9bx~xNo(E?=v6s5(khNLXgRTyb zL$V|$RVRx`ax5+7yRS=)Z>=3lJj_ov!ID?+k-X+j^Us z54Z8@kM13tKOKQ!_#Bym%}l|0w(xgyb*KpzyP{xj$o~2SO7eKJ$u~U1h->PX~rqHq;=b+qYVQLma-;I9y-*PDc7BJggF zyhZA!0NE}43V9rO@^Rrv(!xn*WO0%`3~1(G-f{kRgSJWzt{`EqP+j$H>+rq(KF2S+?;P6mUdZW>a{ObCF&6$ zB-qVxsEn(B6Rkj`M$?L!wmUXS=Q7J#UVq|=fp6cYY~7aZ&&HYFBto4GY4Y8XJ4nHp zWy)8xYt)=XfT>o7XWBNXRZ7K8z|%bqe0lwPW=5x81uvf_&W>mWEgA`?=MF#H4m34$ z3gw=y?vSG^P$scYFST4SU+mhCkJyaVcAuJdG^da3XitiWY^jP%f&;mzKUZUds(Z*z zEYq*(ZE_Y!hFwGB?%0%exq{K#j=b;enq0bM5fRw5*kI$4%d$~z+&scrzU17ow<57F z^pFppE^R59>e^k640~8x*|03opN&YBsyVF6@&bAHy6qL2eTq1a7YVW1Y};zFG!s!5 zYd_K~T^t)N!GLQ9BNi~LOP++z0q=-9%NL+IcrXlj?9e~E z&x~HOQA)}v+~T>Ip(y**U!g1U+}unDxG0DT$134mid37w_r~>)Q}ndpY{1>bVNFZk zjW}qxLIG{MpRzH(%Aqs|JG!u_j1sqkWVYKwRSgweuZgx$OEuM-9dlu#cC^3=W}2dX z2th9&U-JfVwVLq^SIDlYTaj&V)oIt8nP%1)FXoK$8g$>3Exl3rd+@hje>d2gxt668 zJhF&CJ%My_B|n7cGti-TtbOZkK^?eElCB{{L@U+Hn{ewfE|%k7r_;H&r#4-r#g9BU z2a3qXd>ul5035gaY_8?sx>28OeD!!JK>{PhQWw{$J5s7+hUGuiQnCrBio+_z_4ARP zig%QCOQhrbcHHCp9&^OCN%aM?Vv&3@7de)l)ZZ zG}?etSe(d=AWfc`qL8owMv4 zmue7o5bYeDj}^~dS+WV-7+0u*K1zkxs)e>Xg?%0j)N&5f^HkmNRx#qC-vije!hku9 zWr`)P)`%-%85i^J*p?y|9dGyDi%Cdz10S7UhT7_Np-5QWPwSBwT<8w^Lq+2Ahk z6|Z`JUv&}&yRmdg=NDZGKG2mA84K2Xc!?oj1g+#F<(ZHS9OvI31SxX4w0OA(k{&Ey zZeLKoV^5Ym(k!muE_*|VQ!RRSFWL@ylRuU(AF(={mr{J5eELiJhx4ngOlmp6<2Yqp z3Zy#gr@0qv*Eo}Qv2>k(dvdmOByy)fePG<^y*s8ux(W?g>C!V=ky)UeE8Uylra4bc z6{%_7k=eRe6a`Hq#e0fuf*3I z`AcyW`5vdMJx?6EbKd`U<1VS zS1eG_Vjm4j*6m;UYdli zVY$USwNr)eRa<~_B9Po|P3VAY{O&AY9d1um%!N7V@$!8B?uYaeh-kg#-}_X`y756Q zC2+ZC@bTShc13kV%O2&IP3<0Muo#jYWIX~q3#q^T~0 z3s3Gw?&>hbK@0`Ig}7SKQStIMHLW93b+MHeUlQK$64P5!r%uVz%{<4w(#Zg}_FP4L z_EPlof0Q;WgUg$hs8Wz;!dk$|*0mMgf{cyY&D_#^TPr58M;9|__$0Y)Ubeo{9JK9~ z!1ruk9;okH=r&hWfb)_ID@!=A)EeZLmV&o#S3`A;5g%bm$}KR*9YcgpbYz6bl|zK~ zY_P-~bp|ETnWJ>-|Bsm!tFnT#9U(Ifa53MYAB>ADWN001&Ka$})rv?1j9CX4f7qE5 z>9$y{FW60Ieru+TlX))-bEdfJ{>mT6ygWF`m||KrWk*`{c>m*#(Tdo>jc)zkN#?M< zBmC$&w8y;sh@C=iNoCQ27<0^bDQu}cNr(4wLDsUEh=6K&S9O{zhH|)?=tQH|f7=51 zsEJxs*>sEA$Y~-2^E9!}ru$Q^Q&3N_Zv9b8re(X0P+7g%piS~wk(a;Qi=jR_XS#_& z#{r4u3jmbW+F$}4PLe5POzr_9xJOXUMy=E{r(pVYiER1}H~jP3u(+(IyFc#y7%My3 z>TDR*?z&q%pgY1S$B)tNy5O$X-qqGKx3e$W&P{582OS+9Bqo)cN;h#2JdMmZq>;3& z^;^`gi%AMDldi73Y6_#iKQAOb1ViKJ5?%sx>v2~i^Ohh25VSRo<7^pEKBHh5Pchv^ zao@)IMzY&LxfNt49@M%zz;y;w7CA`@_FGhT&-CQ4FE0u_R?N5eIpIl0hpLe&3*;zq zJ(d>u#2PokU?T4rpesw(_rZR_slY7{VQ2U25J)O~9CsA&A~eb(FGsTN^i)W+udBY+ z04`hj0pI69oPPVe{njo_f46R)Rj1CL3ZCW;If z>Wip0I~_ng&)7|Q>Tt%2lZqx$i!nsYMe7wnCdpiB9)U2u-=pDmWEB*z`&IwavHqGz zT1xJ|-DT6!6y6dqyL2d~nUr1;F*L_g*L4hXheE+H>g8M+7Z`Mk(iAN148PT<%_&(Y zavPFGwQ|>Se_Qa%#)p8QsE#rd489CF*=a0lopFfk0C*I5Hr?@sHQYJz3iZ}mERX7? z4&k{9(khUKSt+dX`VzQFB7%zfyKSGOQ^tf!E5kLbCeNvf)wS4}s|k`z)K#S?xV75p zFQX~Hm(0Cw=`(z{-fKlHS_CSn_AN>a_ihnH_UY24*nNjx68)=Dm6}3 zzWVEOY9}=O9Eub^6O?epXsj*sCzb|KIHGD!*}{)89z$I&RE>S~$6A@jBtsp=q7t|& znOwFNTUfRc+O2_1Ed@tdmL?Q&yozXO313(iAQCpv7h~pM}XB^OviwlJO`rGi;ud<^0Y-_S$Thb;;>`IV8DsM9G zrBg-9za9?xq{9I*tp&I7c4fV8xf^M$?|dW2gmc}gD0|vSQvzU!ShwEIHRg8BPrI?u zkbUJx1;z03jW}1QD)BfQoIpAN&`5-RD#~YblFZW=7l2EM$cPeC-p*<|t@7CjHPa!L z=CufrEC-$eWQLgk`7K}CKew3UXLjHo(m}VUEy*0@;rca-%9CO9^CD+)TkXVYpmmfn z_O5%J>P1-_obS^E=l`+lB`*sA_8pqMZEGEGQ}xH@O$l=a&hyN_?SHuGKMba$YC9>~dT^0& zvLZ=0Nq5=oan^&{N`s{`2c`thfphJ7U=D3>>Cm`bb5H^>*rL55jo50ca68|@V3>T$ z3Yc7E8P6@gr9GocIn&sC@qelUch@Ue^jQ2aKswKU{XnPil5IY6kG47_o^Mha%EM(Dp_i7F$E z2%q&4WnPFOcWf$}tOZiP>Oz1vTUa_tnmnJiX^x%<$A+^=NJvB6iB-@&i z@#Vq*&@LKrsoj$A?9>YDokl-erW-m{5Lng;GoWs%GBl0fnkN3VMQhABFX}Q@ZyW0g z5K?yJm^^D$pOPkzdWa}*jqFn{ODcW!s3Z3NEfimzB}UW>3_c8e8uS$Vk*?6_UAHAKnS&6Qn`ELJN{ z*LkarD@7W@*AQj zSVGmIj%tyG$2xe>bW85(nbXe@@d~))^4+*uml;jNa?d<1>FtwS5 zvru-^6mu7O45Kq876Pw*o={378MT6>*QlNLaT7P`Ujs%JgCv)Tk39o>N0tat_~qGu z9V8>P2c#6!y@@PBi+r-WdxN%^&G{yJ%dB?d%=P;(pahD8TJUzS-ib4_8M0iI!rBdt zssNt+6C<9u(5hE44d>ra*k?xk=p}j2>2n?9_iXx|hc<-Vz2@re^HS_>KOH>dB{w~h zB%z>hBkpWmcQ%=hu9{HqqitCUzIl#-Zxc-LZ|Rk^S6=C=!8ErpXgxBE0R8N&oCpW~ zH=+_U8L}J49QjB0>;So}MZy;r1O7FZxz+F%%=ck{qcvZwXp7|j4t+GhC!*0}GPwYi zda93}VzG?mK%60`4e5O5F>zT-Umw!K9m#s%NB#XP#NT_!R5J4yIJPyIjdtp|6r@MZZpoD@#@ard` z8^fiaJpOYD(T;}C*)7(M{t9q5Z?T+cS1Ih=?%`^86)3lRUq+al0#i>fMX9GYLUAiYuGx*|NI1kJ%t}vOx|x+tpcbT# z!B|&g^RkcpzzPNvjV)bsT773@YRT@@huE0j%Wx7c1i0(Cih%l)+RA zzQO9(*A2ndMXT@OrNGt2>aLUh9OCuEG~cn}%{`}2(kLfAr9lcT#1-czM%2m`Xvo@` z?_W>gP);1nhoOo?o{IV4LHO*4v))FH-Wd26;u--}Qp2)wiiJC3#jMWb{aU84bzq>W z>NmXJ*y27qgccikY^8wic6uFkd+K-Q? zMTYQ3Ge!0J&^$?8i6KYkQ-~+B88A4F!s#r!qB`uu_ zmKpIR)n`0K)r7oCiTP9fbuK~-#PZ?9EV)^`F&*>043EE+cg_{JP;Mg-ec7CHo>cre zbSrYkbHhc_zcVvqoFA2C9VA*dc3y;jwV~J#d0T-FsNsAiS%c^2OW(~kN1wBOFItu7 zr<~&Urah4Lj?{>%4p?Dd@o?mT*mG_f#Oui}kiVlf zfZ(srK`hb+k{_@(b6x9hfM54t_P5*X)&O7oUa}9*&+ES3%~B%ZzjDkAo zjG{8wj3Dulyd^ei>_6pG^#HR&!!GZeG-=0$n4==HaVedI#1~SEYAJb2QXBU%{l3Mt z@ZWwXx~3#eh9o!zXawtowwU81mb2qRk?ZmBbLKupBuyDa=ZJKtlH8J=S_N2xT|4VN zt7k-6RmLt;^t(R;KJLDgcJ@B~tJN=y{Z%6O&0i6({GRts#(g9TxnlHlLGEV5^OOO^ z5-8ucimw^yPUnWZMJlAq)#I61+P)@h&#~SG!}QGi7?5NLc587W z0U7*DI$Y0-R)cgQ?8>f4SeL8*d*->wOYo0gT35T+he3_G9_!U?iT(LJP=0kfP!yFw z5mHL1P22q`h?l$F(4r7g;BM@y>0c#z=a-fzmCL5W%?30tFG zv+h)A8gVY1;NgR*C4mwQf?ocQoh&;W7#RE~;#oJ1or7|kqC!v}zDB$)-6z0_7_0{# zwD7SoTo^L)X|LiKnNN^xi(kO9y41~28oU!M-{0>DSo~ZR>I(%B(zoHmq*u#|Wvsb^ z9<9a&l1g)N5FwU4n`!;X9Jb< zzh320MLJys5aG~l2vpoQQQPl1AfeU3EKyd&H`LU;azU`c)qJ5eY|A3`A>wS<<$-a1 zqZL00(V}7h6EtkTE96KB*a8hjRlFM_MdnVcTKM}yX?CwATA>O8Cf@a}EbMZ# zTq?7F^Ev-FA67jVCSgBzX|msTD$z>~(1?mfDujp&OO2yf;Fg7|11BNNl5{#Dgt0^} zFp7$MAkFDwaG-i{j>hwX`zTxfCBR592BE?3%6ZYs2$`9h)|kW<5@~38{fJgdgziDw zaFd%_*p!y|Li2u5!M^5O!TP%GOBAU9DiVHcb%unOHuFTInPnK=F&NV~tx7@QxX7hq zED%h~;>98I)vQW1LVqDue~=Kw@*GXnSwWg?a(1m#-D*KN%rNE^ZNqn;$gpJk zqpw2XVTyJrEjVJz9(c5gBq5q?X7+SRI7!i0oo3)27ejh*#(HSx;uM}?RWIg`6pJr6-l~(ozTYZ`~lM>T=Yt# z#iqKY5pFJo{!zEq@qQbmGh{}<#5h+?&OA#3G$_dzD^d4NZq$qb_qRC+a@5G)(VFT8 zsnoBQTSkyCbSmPG>#9*Od6?*D1C!wHS{}I^p0vQ~C|+4og}|XESfyZx?`T>VWcIbP zSPpUCrbH@+L|v79lAEt_Lw49Jx=yozRxiDJX-|EjBK@#AKdQ}`8_yR$rcQ|#0MG|3> z_uu%fEE^jNQP5yO>?lQ`J9upO2MlZu{sUh9j@E`}6Hd;52;2Nb9)NeK@#fu1jXK&8 zyzOC_57e4oH1>_@@p0OG26qk|{4+OYuDv0e=CgEgX3YCJpVWcHBLdHZUZE+VZ?6kE zk{(YEdF}M|PuGf)?s`KXAT(nRkDEtNH8uj6x{TAi`KNYXZ^T~vBjnJLCe<`)1EHcH z``fO%BO{R`*U#pi9D;u2N`4JSf3#l&g6KNSs<&%b2DKL3el*z}=0RKn^@MDdnpG6* zNDwCE=X57b6j;en>#|``z@dQ&uTU>2^34}S7%3NrvPl;rVX5n~QQHnUmyJ9(l}7-L z>q}ub6k_`xb4ReNUa^NXi`o~7-$ubB$RS`0S~%CF5;@6>L1|D`q!V&$h&Ty_hLu6V z6;6zzNnsV5qU=MWT_GVE`hFo@7!%^0NuCPY+y1FUw@l*C50q8+1O)(&6-*_jp*hz)F6Q9xKpO)wy`9Va z@0ZZU1DHkamuusc_StI;1I3as1nupMv=Mw)RqO2S{d~EF2Vv0psFL+1N^PW#zL3N~h6e zc|rjRSgP>Zx0Y7X%DCdAI}QAtO(FGtWga~(CtV6rv^+ud7q^m zwdT%rG03P*S}RA8a-9+QFRUV%lvbYqH0V?V|0R_Klfr?s0W4369o@sd)aPdXi$n;k zp!I@g4ITW7_~GH>^hBNd`OZ}i*c0&UZ4n6@z3xnk>d88gVI3&B6Ax0Waay}_Womd)nxiBR(qjn-liYuVJ?;iQ&Bt;RL zoz{>jP_^&Dg~BOr+`5(8kSJWa@4;Mzrw^K~a9$%68&kp7h?G*~X(jsX&%jRcDBJf? z#3pH}(T5BpL7~)fZp%w{RjG;##!NTm{wIo0*s5#g*yAF~f?MF9;0M^=x@D0j&0T@8 zY}jw(kkjUX`i`~efnDS$7*t(cNPG2aJncRWCxL++%iVz>`Oet3k>j+zY zZI*h@m3|y9jk~_0Lh09Y$Q~MPpgo%atz?=y7=)7&yX# zm>bg=`riJndC*j#KeF*jg9+6MVWZS=aJ3D~roH`tXZh zOcK;J>|rIF5dDYDcN+biBtp2r+?@Q09lT4Pfte3T-#8LezHebW z$F}+dERNs;7$KBww2yWD4|DOc(zDr1pQv><4u;F5+EZ(&fu(T5^YK%Y-X%xWqgdDl8ra;E(-y$$(N{3@1qG$D zhS1s4HeVNzlW00#Fa^+a)DVuK>tRpNs|caXqG&0ZiB{~ret6xMfKMg|ymBOKq_8y+z*qlmZ0XpVNOWuN0= zcP{ctqGZw1%IOJ2teLKIZjxS~zZrioA6`DTpLf^m+prt&2MkL6QBir_a)oa^9<3e( zy4Y@qhH9@8Ip9XGPAfUwCm{5_5S{o2roOYi5f{n2@poo1B%b|0bcuSwmEdR4Mc`mHC4poFCDH9nil@DOi4YVg!e?6)|{@@lh? zkFFRn5C{5T)ZC%oZn=3*^gJ@CUYiIGWA~ZySkZuLCa8enKQ9g**0{>fpu|mIImB7R z_@(w8TjISE27|w_MStV(Y|DX;40dd7(}_Md)DyQsBByx#(f@n9=jKG%dV3S0$k|Jr zY&|N!aZ==dt@)7i$BvpZW-)-6pyfgaez89pPKlN~;0L8BOT8f}2>~a8kG9=PE0=l) zzVUGV{6x5foZgb8O~uf*1vRC7vdO7Ug)2Wyc-prQlBj@81STONRMiqQ-N}r6wnYiu z*FaYE8=a~HFP`KVv7QX^wjDzdz_uGBil!nJ8FHzUGst5(zN0-Z9}2w5eK%h_{#og? z`+P0#m2pjZY1-<0G9(eV?xFylM3POiht`lO3T1ImQM4`>BJc^)CG6mh!YdskzM%W6 zSVq{X_M2M^_l&MzpO*Ha8-U6s|!hSp> z2*9~{eOyZm=J2Z2Cfx$gXQG)9lBkHfx)ULSWk~vke1{uj?1N{2@dZhEEoY>{h#n|p zjvLdsa&CA?D87B;@cIVJWh{0y>^uF8WK$wQY@bq1zSH&hJ=fRbw&uqrkq$$hmtwd2 zcCqE&VcHejF{XxkP2_vW02$B2C(w`~l7=XYhU=sYG#d^5KP_GDeTatzL z&Glh059^KWLf|8u@L1vy7mo64ZQU5Zz?9#Z;}&by50lK;HRtCZp9YCjz>EKD2pG;J z3d{>}^bOWPf^wAxN;u^W;d-ahw}IyC6HuHD9D1Cw7!*GzkD7Uz`?cU3^eay+Ud$@bO0K-0p zx4u2Xdo0_ONF-K+PF&ZAsnXVdVrSfkL6%_21L|CR5#b&6<>XP@?(4#`Jr82Ri$REXA!DtOC#@H#O=j6X#^-5UD*Hu)AU}6jAf-9`+NyL30#$ydhWzN6V5;7-icSl8(mZsU0M{c^P zEwM9C+V2jzLX!{}6!xXn607KmOB`0yo*JZ9uzzDOR)Kwtl(5Aww^)V$Hd&nf{h?3r z&dnY@Rqe35)d2}ZGYJy^-z?2D{Wv4@4OJt)-sPQ|DifbwbsO=i`U??e zC!WX0m5x})gk*159l$)754o{_9!=He%vM;h5~9%_(s_f&PE?MVZT(J0T5EXZHucw3 zYkDwIP8qo^B^9b~q}0s&X_4J~YXa^wK7o2n@3#;I<8|q_E7(9W%~*mHhRJ06P3u!w zM$-!`lM=8>g!OtbOY^97^Xmeen{CW7=9BMIAB42*iCAdqm=4K7lL5dMikebhRJwUZ z>91k5;q+}8LS8h9ikD)V+Rlj~8-!;ad)ArH=;j40k#($>&Zh;8yXMU-7+GcFC&rfm zrORvUZTV#d39&*6Cu`P<af1MHJbHTq@_QZKq%@pF4Q!7VdI?w-F{32IOogcCDQ8@PAhr5=0y!s&E5bFBb-;`ucebsr^X!PNQkc;K{?rv;9iB^gcuyJl)0yM2Et++C}bzc<2w z+GYUra`*c*HhT)9k47M3`wy`1lSBw-8|eN1%mDqQdbh>w2G5GT>zvjUlH?{DzwxR3 zU1uXk(bhqko0ZNa&S^A?o_b2pTAoN6$gGF?@FopIfzH^-j2@##70T=&mCD^By3>dG zgsW&y(;qCM$rhE1#=x9@`gdOf1lhoDF3R8KAzTPVLTL1N$Y*RXBCFxQ^o6mX?&#-sv}UivW^7QU6L7ZsqPCC}XhcTEi9UN}=*r_K_HFZ?9I-Ri)Ss zv-UNpJoL^RPg{V3oOhQ%>UY6sT!DT6H)c4}IW#cJAh4UX6KJFkZeLyn$Xm zaG(N-#`&4Z+kX*RsHhhpMwPo#m2tAjf|pIhmWhna3J_V=927XAOq5kjf&>uwV4-Uv zbv6+-#%179bScFU?|j{2^}d|P+omdpasEK>mc{yHNYLwVCr9u2*HLqVzd z&~VdLxamh5NhL~>>7l&p#SDH~Y7Yq?Vrd$~lc?g${ZM(rKe0tX#0PIVbcwjXJJUJH zS0lmi(Lq8020A1+JUuX~Nc)*2D~5yQhM{5*X0@Ss6lIXr-6VjWKv^r54$)LP>J zKT=G3^hBTxJCfldnTn3HqlN$Y(SlA6!YDDe=}r-*;s86kxByUBeCez_^qTyA$mb02G@=N0`u2_;oqS-{`6+%a zc6f2hPA@FZXU`i-K6{>OPmxbD_}m0`=u(5^HQ)~}jLp7sGwWsf4G5B{X~1}l)?N=P znw3n?NsYs^R1FjLJx=2hO__qO5$E@WNfN4V^6KT4`nqO4z0HYkx$Wb=nxCjped_McIHFl+&e7gGeoE4y-0+ad@_>Ik1~LeRg<; z22~XHs|wL1y2456b9}x^9~fmFeU8tePeozBs!-^2ZYg~rY=u7c)H%1HPDNqAsu1ez z=e8jf<-`AY`YknyvE5&3p6U#_Ds`igVi%1x*ey6^wT+xihqSu~zf`+!_H11moMxUE ziAVpmb@FUpu8ks>iC&85?sS|+{kC|IDM}LPJBa&KI*KCo3Ep&a6S{rKbl|8_C|}a~ zH)=swR2Ue&3JJvfIq?P|;L%nMbxAcV zQH|tUsbVjC)HkiZnN!S46?5^SgJ0X^V{w&YR;rk%g_(j}V(p=Is;eBs!@nsyOYT*X z`;JhPFe}zHg@jBsju5Y{T8f$`suR~rzE+Me#M7TV-+i^)iM7>srw%YXIeQ~TCG!?O zhk?vq2{URt>c4n<{05>klqMvKrlU<|&~k)o0w&^}3|QniXm_327bq~0)|!2R1Y=#j z*_Tw9u42fmYY(NmUXN6Uvdh&4g^*1^%ipEyN)oDSieGcJx}w)$r{W$Psc8lz`pAdC3M0*iZVa{0#Hi>1QY-O00;p6O!Gpc4vE-Y6aWBHcK`qv0000sH83(? zX>N37a&mQWbYFC3b963YHZ|>C`*Yj2vi?0Y`5%yTdK0^mY{|}}w{F_wJlcBF*pBR+ zHg`JXp-4z#O_3}gwv{<^|Mv6k0wDO%gLa%IX{b;3~B zJD&Kdh?8iXI8%YcQ6i;CqfvJ5B=TD^i*n&Qp-80Xr&;0;^Gpgq6He%DMv0h4oJ`DlyyW3Ccm3xS^Vwh=K1;g#yHG3qGY@o zC?e_R_h1Nr=BYxa{x}3jSp#O?D^tU+sZCF#70WZ%fE&4$Vf%hS|{4K1l|G(Wo@}Nt; zM8$3tW{#Vo@+cCp4n4}P>B9|Aa*tC8T)h03D$#Ox(o{}|f%KHvc8?xCgwI7&Q4-Rr zACA-WDDt}KBh7;h=NoRck)Lkr=HO^k@i3i|NCH2E*Mg!uk?FUh8;I^ybki--Jr~_c zkE$;E{YU@Df5S+`&KNc?9S?nw3&1<6|8^wKeNUPeVy(ZuE!>HdY`RgfzM8;!;%Aa| z7Jz{ZG4caCO*1e<3LpBRlgw7okry!uWa_v{)RzA-8#wxoA>OT03u?3gzzmg&BJFz z??JD}ZE%$cN-}G-8b_uL_w!2>#Ucug58+zQ6+KCK3=2txOcHR5|I(b91%?rcIFN*s z5HfojQ+qa%?x~Rl!3ahb$TPr}$Py<`#o8bFG~OHn$lQtedffoab2-e%V`?+OVAF4n z;9o^)rcni5deCgj8qa`@Dclx=@|_@uegv(_#sVD zn61(YdZG@d5VZ!5Gy|L%pc2j~)AMA)oM1XgRbRy2G0OjuNGJFQ zQ?u-la}wUtB<2LZr$=hWRT;38DL~Hrsk~z}us2#zof+^kdtXSlK3S+*m5R0B$Y$QI zi)o%_ikuUqBvi}yK^#XZ=&AuLwmafCM(nqRN2rm&rh-6?g3ZQ)thSdj*5V}1%=OX) ztpy;pv$D;K0|Z7tB0TyDVG+%o$2dlr>SS>6>f}tiSp+s-y*WAt|7?QJ5I}QR%>gIG zxVfsFkS;TQ^3oH8BF>5D!|D)P^`1yGEabyBL2BUPQr znxC!z{Q1CC@1VjHNQ27IRB@x5_H9$Dltr1GqOX8th;xL1Aw(JkY&~c^czrVTvu3|k z80OO<1|5wG8G#;2@%AkUwA8NOrX8AeL>G!2u_B!_1QmrvX0zCLoq%R2cjCuNI!~MO z1|hVJe2>8?j|qAFlr#k*4WSRWmI{5xNZmHrZY%Yj_Y(WgRpq{O-GcX|3+D-F0i>`_ zczFWnrtUgI`OVY8%iFh}pSXc^lDXq$x^$WRe{KKO!O=R8+m=0}GVTyAKJv#o+;A!p z&(EOa4F7`9Gy`fl=lF+U$Xw1-h7L79&ESQE8}DQioltCP0L@dOb~=AZ#h=+qYB|+ZcfoH8nyGBP;-oz`cm& zojIqF$OIM*hEncG1&f49IzYN>;v*I6u=fN(bWT#$i(cR5B`Ja4g+l=pOWx*<}?;xH;K~f8Rn(xSt2!d3vN;L^-9j>kP2mk6pH4MA~hOvAwq(=B((xp z4v{7`j{6b%fUq)vv`&rwxLCB$P=cPt|Mb+aPbAp=fg=<{k%4A;s+>hsYxiNB2#FEF z=we-pV!#O@i7Hm5R6Il+cxs4nDHkUaW_YHHsZ=EtE=H*?M&zHThKMRvUcz&$ zzQBV+(K}m2BcKwuTIs$nKeIJe$5i&NR%R-PwlcFrMQ*j|zF{GJSG`csc;`0DZL70d zE5j77IZ<(qC3;^8(BOXx=Z1Y#ETv=f!=Dd33cg`+MO)ChZ}i7)?-OLW9805Bk^^gS zQOyz4Z|so28jVExxAP5|3rsUTrHX#J;@$sOUDPXzZnKv%cx4gI`Gxt>Lgj=`jF+3P zQHkPZ6`$)A7e$lgEK#D{mtwjy-+||dfBxRD7RD3D4lGagY6$%BqE-`BP3k@cUKEd? zB9n0t&*vJ46cfw~nr#ERpw48F$`YidsW~h$6#Ai0t6%?}^ok{f$-^-%tmudVI;A=9 zj;0-ACbGnlSQEu04by-HcWgkyNM~&*b7W{gJG+4xBX8mN=Afcxi>G zS~|AnsL`^r@^7}MdQ}CM;~^a#!Dv(j=;ld+Vp1n7Rt1@?S)EHzlHknG9BJ$zhCy8u z@Ny(lBt8gzC?=I>T8)dzq%w9A7G4+OYB`laGRn@S4DBFOn#WG7#5in<;WZ`jG=R8w zk|vDwwVn-Je=B-V*s}Xi*tWNxKpa+5Cvb{V49M_dfbAO*>WaB9=6O)n+qWhp?Q6 z1kdH$akgSywtyO&mc0-+N6KCdE-=61*42>iy}?L=X86B{g>7fLOYb>qJ%|-Z(Ymkg=&x)5iy7#eN$BC&0(DS zuk)_yQBh&$bYR1VMxap5hZGhKHqg~#({44;_cDGW+S>S8Du21*6N?|;@QI7|hHqiQ z8h>+C?`8aRJQ6u+x@$M)JE9AiA)2e4v1!6PVRQ|~b}6L&IL7ulqU>s8dvByQQ@K4< zR`OZT<^D)f|6V+{wls{giAn>T@h@|u|KJdnD;{MfvpQ&CVcuBxM~ER*Ox&!jwApUv zZ5?88U#$WSZBREc#}%ElojgfijaDDqId9^et2pTLFvya*Jc@s!anYCK5TE00wb~&* z^o-RE)k+6CA;be1;{lo(CxuYT|EH-y-NM#s(^TaHsfkW+)iP~cHSN#I4W@Vm#${Jr znq;&0J$kl~y~;?Ve0R8JczlnSZi3IiJty`o1N>Z5;>YFY^%Fa$24DIPr|k>e@Y7i^ zxl*n4!k)PCg|dMyGZW)^ZXZvua!Og;)xu5aF;jAOmDXO;Wg^KAAl0M8DzBWfH?2s|d3@`&#>e!VF7DiQ z&27~k$}FRWeu4=oC$()Z;j~l>4`+1#-TA)`o}|~Ema+VrxTVwUCvEk7r#pX{dx3_39J z>Mac?Q4e6m(yI_^bAkz}+8;kK*|?dh-cG1F{~E-2zrS8}Ui&2F!OI`oc>8ZQqyS+CBDAbrrGW)MB8pdrG!%S?Bl#!dQHchGll903U=@^0dBr&Hz~Yv zM(S$A4!3J!m18P0C^uoVDnY(oxMEh=E#Ad=PhU-BES-#>*TgYBKwCDSCh>0FYgOrA zFw>5T(O`KE!V&9++*|s}rnl;J4|OPMQE>x-10jMWJlY^h=Z)=gC;V6j@VdeZ3Y7*I=KWba0%EweXDfT!Z%+pG-ZHpJ%%Eb%?^NNdC&gR}GZebi5a1?v(D9u?X z-XW{LY=RC==1-dsT2GrG(bD|u_rR&?CzO~6H=oRu#&3<9S`C%`wNn~+xtY?gfzuB% zrL|9=?KjeAukL*kPTz7R`)S-YzqkJ(ma+F3FYZGDH z7gVmABx>RMpw8Q-wsidE>7;LLcf+W{@q46}nt2`Ox?Nu9i%3c_S(AN=A?4bhNGoLW z_|r^FEix{fj$$*ouQbfn}k|+ z^v>mDsBR)*FSPcUWxQkfIqp^ApCDL7_FDN?fqG?Y)%&~&@ck`{KJmGrpE}vX3Gc;)_(ttZp34+vn1Au1i$rMy8`RTYon#eh zv1$3Qy8z*sw&F6I!asWG_O__SIZs)3OTg0VWGKW}?$8R{Qfa&kX{BMes!E}WfFMQ2 zXeJZ0g{!*ls5aYYUixYE?a;_>ozB&ngsE(q=+Jqn2OP|R7t(xLLVZ($k)p) z?x2X}I1k8tzzVk_b{y{v+v{t(6p=+|Oij_?u#&4LQ4VTE%xvc`H(2;!uJu$}-yhh|j8exe-( z{DT)qFOEgGTC9|u(dG%+GGnFKiMpD1$GDA=<7A2GEYn2S-o#sy;L_ihIy$7iP3C9U z&ZSU0iPHy4+VF*wX2j@}pJSn%7^lSaCi3;H#059GsHBoAkH$3VkCudIpk83n549EJ zgNmo=Exzj_z0e{RT@`4k7+u}{j1Z7==5ayd%Pt9cy-uGVAcF zWjn4XDj4m{E8rqYTv>3}7yESO_R|=fwWt3ss9k$xL*=E& zh8`9o+jeVY(|mrx=w=QpC^r|~t_W}VvIFHRY94b%&2C*rvn{o{1nV@R6Sg*uuiGSsBMX?SlJ8J)nBPA7IAwIT%;>YXoar&EBEbQ zrH}Fk=X0L+u50OKT}w{~>o2cCOO*xBg8jtT=6$$ey}Cm>gfc2I?VSr@LiK7X&3esJ zGi8-SZnG!3I-<`YASrXr9obxHWgVzK8dQgw{{m1;0|XQR000O8%7phqipM9WoHYOd zv?&1qAOHXWHZ?;qGGAqQbY*U2Wn^D(aAR*|WpiJ2Wpi{cVKy~m?0tQ6+s4)J|DN%8 z*fhS56pXjk|xuPwwshQTZoFVo2=ND`Ir-Bp~4@g%*R1S5g3gGm&LEFDa5 zf=Tp8u}Ehk3=%Pk`f)a$#J$-x67f_7Nq;|`h*8>)2MfTVv{}-RCSrOOiD@($Wg;E$ z!{1K66Mu`6Xc7#?+gWcIhvIb{MoAWl0H`S?yNddvM{u~rUx|iuNdulz01l>cnlwZd z7WU}}m!s$oCp5(LEw!@f$#5xxK< zc)W>+L(z-GEQu%|f`Y>+z6Nc9 z2w^&_l}A8=VVYbro5*Yg3F3|iB1xwWk%7oRT}`LsKko0}+}u36OlFVL$>sh~0?GFO z41(~lN)=HSUnZbvn!=zm*c?P3^!qWX6yzLqk6J!79Hz+Gpf{5!%i`pcfQ=}TtW*qU zNhnLi(*=kEoNEXo=nW&S;gdI~=h`q72ffiG`qwPZ;%UT$ z5)<^A$^!6lLmZ#|zlL~m_K$`*fA>~Agnb+fvgPKWn(FmN1fBavWqBI|5Su_IoeW|$T=LcPQ zeL4~aHGPB_vzs*SH-RIY4X1d16sC`6ANN&pP_!>;7>!8G!#F{`0f^yMl>JdOhoU(W z&CD0g8_}GL=2eSw*L{9g|Mj0F731I%z83|3U?LfzmLMwDh9b=)nopyIWS6a1@Fwm@ z8kN}b+HDbD1(W?S9qz6Ma5Et*ARP`t`CJTQwy|sqF37HWaS}`x%i)0HG0Afjgp+h# z#xL1JfqM+?_=OT|gsC__6;18!J^1=8ks1%+CrLa_C(;yxFoXw@8Bd~1z<}hX3#43R zn1T(%T|9z@R6%~HZJ|N6Wde7l`u6P+!RxeIREFzj^4E(jx*SExbeCN;BC7|G%T$A4 zw6D{2EYd{R33xZ-jQxn(mpFlg!&yK){%13$9d$B+7!RYV^kw6VM^{n!QHzGEMKC#x zu2Bt(=_D9uV&|vXXuRJ;#T;IVZ+E%S+hG)B5!D*H2}nc~Ooj`Fo1vi`NexeCTsLIg zKyZx;wpBwxG6%j$HE#>{e)#Py7%D(f|0|`evsdS@-ZiM=09RCXD7A6Lm4@MLLK4%> z5K}&;I%I%4B7`C{1|B5=Ik;3F6WUM183~+;0eLZ?tC}uFm=G5#)MU8$iVD7rLa2C% z8dh?}Z%|rMEH!_PYPBz39KA%gXadr>(q*{ci@`9sPrkW8lEI?&9gx8A<6*E|lNz9KR zA`WJ*D0pGHHAF}zq1#XagB~Hu37DKQwTE~DLIw-{A!A9`P_U84BXJf{JxTJH;M5CL z0+VdoU|H}>i4`xh2z4ukJ&1v_D_|l7BS@K>5mctA+dq;t85}YVhj}KIB?zI_*)Sjv z4hB;deNC7W1R0se^@v-sKTM)v_y>k&$f2s1T5*(RT`EpBUnPcvscPTiQS_D8!116a zI};EiCY(oHB}BQy$yBlP1KIfdT``(vQwc5@W+YTY_vv_?!h;mUlI(`~fsO2aUQJ0( zvMEeWa=~U}8cuC5-jlrj#6vdK?+am{5o+gNuGV!5gA|giwfEB zwD%LBGc}+BI0z!ZDRB?T-&Auh+rj(yY`zq`#}{O?d8JF-qI8(o(Eu+K$Ocu4{|uB} z#l095T*16RL;D$OvGfK2Wy&r(g&cTJs1=+;b4)Dxg`yU(sWFX`J~srC4iH6=BUl~8 zmoxaxC>o{Up$XkDpgF2^&_3PZ7pX(NR*l#~R!a-0p5*r_nxq#LrKwz0b~4p*ctbqs zz%CCT@0JAnVgcLGlyl9t{6pZtD(pFDz`uVlM~%k^fuIG5Q*3N_ySN%63NCv z7;T~=r6o@QmZhktW1!254YaJOqv1e}9l)2#Xt@obmMiX4BTKd8{d<(ZC`d$+%$Te| z|M~KW9anb&xnuQ^I$7jovd5T-lhe20^UqX2YW>{w!;5sR{8LrNY54IbLPhqFz~&HN zyf|y%*Lg#ny?H^f-@HH(3p#r+8fOL%R9=n>v`#+W3@=IuOZ7hIQ==4*WQdw^?J`TK z`#X{CgzQ*wES^PEG6yP^qzS)7Zu&EdDHhhMm1eoq^q#3|r6F3+4muwjB*kam!AGu3 zqu|=qJJ6l!5H!T;IYI6r2DzLd@HUMGM{Zmjab+*#e5o)*=@(Pxv5J%JPU#-?bU()9AOBKF)TlI4zht{mGI=0@WsY**xmAU|u*PK{Nk%@@h{AeCtS;^ku}zb)TGG#jKN^c~ zT~W~(9oik4&xpoSLaqZOeY;ZL6`+#H0fnRrP-LVU9JyLO$S`w2BB=^w7)+=Rj;7Uc zLKjZB1WpKjOe!IbVh0kEsvw~oJww-*LXATrteV5|(1C}fDtO~z4o=cn4e;6(*>$zZ zXpn3GSFe@YwJS9wEdy08I90=}v{tfi9%rFQElFh!mD$kfpVX2dBNG3oB|jd4;Pw$R zqV5rS?{t>Qm`0Rydx#29>!N~I$to4e=p$42SSHI88}RRZ0_ucR`xJV~Orb0kZyCZ@~~%74;ibxBKni-|`qQm5uYV zfU~Fd$7T1Zk_?L-Fx~n>>W_1lDJm4j&(p_bE-=mPBV~+>86W;4QP>$pvkHrDT}>Ox znW>pb2g()+1P2@DjRB?lE&B?hNaeU7H9tJ^hVZUb(uj(|8hIhQ;9ljsj1H8k+I#%^m*^9%`SfZ)MgV*Bg zogclQq3B(OO?UWWZ6vy*C-y8+R3VJg$ufj^%?Jq>BPE2A{swr00Z(cC7~K-!8&zttIu_2|FfXiz;Cgsyml9W7KA}o|KVryrrc5btPR+OeX=; za&df-CYsm@+A50ij+^wVRDc{dFEAKvp%942#b^|gL=co3zv!>wH!CFC5Yo=K)Z=!9 z{(An_Ue^lB?F858vQs%tB~M!W6veU(@1mv?YiMjsO;H`f4e(|jw}zZcZ69@{cl7x2 z&vJC+X9^Ig#=5ZM^UeNcPWK9=dQ1?pGBWH2BH$+inI?-*ZMp35E=+^e*@l{}0 zpJl3d2a36jf@&2Rj;pwrq!ToUbPSl%v?k4`@Ek(UZY`Dmt*KP@S|&hFVQj$8d<8pl zYT?W9Gq2!B;h%57(&9J7(xRTF#Re<|^L1E?`pWps%-fgXF@VoC=C?D$VDVdLaB({Z zKdohyVDQuUS7A@;k8)9NU2m7NQgM(s-Gu8Eb_;Ng`EP(94@IrH|P|uwOB5gtz)UK82z3da*K5&x2#E)vil@9lHI5AEhIPWb2R?%XoB^|_i4UXb%*ZK zZR$EDy2kwXB|Jpxn^>QW$Zsh|;QXDLAa&fnu~7Ag+Rp7lEnOYP2vKi->e?2BtQ1(fVMuOD4c%Z}v#O zL_aPgM;ABggm(v+#g!?~88+zco}a%Dd7<2FRGK@{i_iYdi_bXA1=4a8v7|WcSBy`$ zDo0ZA&5ZdMS7SPaRu*AVjafO|k45VUA+4G746fmj3ESl(y!zP3%4&3R%!wQx^jW2px z)-=m{pVC+U)|B?brp7!l`)$pB&<{mk%=oBTK84J_%}<fnI;!-UkX$Uqd zc!#8`g1xJ_wCs16?TB%$ZAfz_*sB59nnOMNx3P>-wd;;q5>`#=XKDW$E?|CvWBzx z6YsdADcUt=b;~p)(OmAG)mV!tN4(@1+a4OKwJ*jLpci;jR%6mpn;D3Ps5psf zKOZclpYIaN_p8ggZ%PE{HO|F75e7Impqoa6lbwAFG}5j2i5}AegW^)n;$o6M==6$2 zq5ul#1N<^LW7{;VZ7PbxBgS8xj+aM_n_v#I>$Mu+`u)`KO6Q@vSJ zZ5-y^dU#YJ>^{q3Oh-P1a!q~E$I?%m*>XcbWz;@bK&K+eSXV@$$BSlh4*#VwVkxX0nv6-qOJL0@VJ&X z=J*E9QL`uqW^h^nGF{0aS2SF?tivOPWp0{Zk=AC0O0;ak5R=91JU=lY@O?QuWH+1W z?D+{XKUGx|ggis#hG;<`G&h!Pd3m*baWhw}ct@#V!_Hy*y-cyQ2fh6PL&N8}WT z2zoQD5za%zs^A9aPfRE%q)d5`nRhh|0d6mXak)cHHGzqY>6)ZC6{?$2qx<)$PS`pS zBK@pxXGtmRliu^7bac(0vZN$|+dkS?4 zuqr-C8u;I83_eu`I1GS_p)}637|@#B3DKcHt70q4`;a+ks;yH1K#!XI#|LQ1J0uDz z2Jr`(AGb3^>>p?+O*eul;;D4f&^)yM6MuxAD=!<2u@U{Sw@6ZV)4+u)5>d+#n}+;1S8h|8jBz zjhh9nf0mM~ipZ=j`O{iWuGE^W*e1g?r_>0EUk&uD!6#MOB(hdCZQ;{?gaHZJ7FaD9 zYEo|Kb^r-0*YfX;`L1eh)KEEXo^y_Nz*a{zIfqhaTvX+z;`3(*C@l*wDcvrVmbv%* zT|zrvik3d6pvv9!yIn$zKZVWodbHid0-R!E0Y2hE&v2AyH`Ie3F=CaqFydi`Rj7nJ zTvQ&Hf~Kg7r@0ohqf7Pu4JgvZi}Q1Lc*QH=h+=1e2A~Z&1VIn<)Q>2A#X#*D1;A|L z4*{bIp<(~x(^yGDB{$|}c4fqsrROY7jx0L2lto8P1v;`ot#ykD zK$m%U;?KqAx=yjns!x)PD(e9=(^U9Sg{T*y$ffBrM3V=vy#4zR_<1khzWxC}@2#5P z!ILLB!&oyv<&L^#AjNS7(@IKAChK&b+2y+3Vx>E`Uk8En+6WPmWMq22iQ>yln!1Zk zrdbID6W%wq+F0aaf7D+FXFOaK;VhWa9F95jlNbN<@x^>9j-+ryz}>EszntZPR}jAJ zxzp~`)yS%(F(^tSPS%n}QE4oSl1>-)>uyP>WqyBEojP#3ccfDXaIjpb^Iu=5m@_VW z{wz^D(cMxj>mKv%DOc-U;q=pp&jXYbxT+6~aODR+Eb;AYnZvQIz^RK079@A#dJWC< zQ#!%aszHpT^1Lt{MpCc13!4xA-!*TNIhj^V$H6j@&}(y;VeOr@olUawYM#a63h~^t=*O#e*^YR<$iW<+FRG zA<+1zu>(U&kEaUow<8Ax73>Wj6r8-pQ1IHDgXmZw{IyE8tx{fHM&HWVD!lWocgD}w zk*#(z$BhppxS*4R>p0+y%Nk9s;js!sx2B@-bBz8SV{F%8Y^@a8wivw{j0Y8Mj!DXg z_U!|{O%y?qhj@tJ=d7n5w^;6?bZp&zM$1Yuw`L6p?s$Lt(~sV6X=9s5SusN4Od2?? zd%N9enFUC?8&ZlhdK22hMmsF&gk0YCW8P)@UHVbKG3|Yk0m>@d*8E&=kVg<#m7Az? zx(s8&t70IL^WrcVh7{G<3?{Yw`L+D{Tk=QSfi`5&cNsLil=TnVO5;SiK`d#TKaKS| zean_8f>*^IV;T(Z#+tICwA*EAPmHwN>so~+ZQAp-o|t8SHGyU}tj% zJGU_>vWe|Xine&TeId^)FDwJ6`ykp(irPIPztDP6{n#o$dgVtebG!W5DL;10j|b() zL%UbvEer4Gd^WYZRjOE0^01`jqFmDL!^oCl60YAe6f8|%CSc8UD~0CGl+0wS4r?pV)V>-nJcye)UxQtr$a((+s^sdcU1 zePQ~w5M0wQJREM`yo!+fU@7JUc>fnTpb|sve z^g&H}3oF>G(!H8=zb3t1lisOG@7AOr)TAHQq(81ne^Qek)TH-n(!-kceocB*lRl_P zZ}n>AUz6_Fq_=C*J2mOun)HL3^uwC;$2I9sYSM$6^j=MRRFgi?>F(G_OVu+p^J3k@ zohH@|Z1OJJO2r)3D5fUeuSsv$q<3o4yEW+tHR*>n>5psDpVXuWHR-*Y^spwqUy~ly zqz`J+TZ0<;*QEP3>Ft{IPEC5ZCjFo${jeteaZUP@n)IM1y;qYS)};4q(xaO60n(ko zmo9cJ`_nR?GL9s6a5o~~KfhZ^bFYSGq%U9l=$t0ShiRBasymdayv302+>p2E?pgx~ zZTe&e z+HGl4@(Utb7W8k9zp*&{=A@LeK+4N+j1r%<8sdBU^?`mJJ!_S&A=4X5$|_vaGsB(j zH2fe}lBkm$mQ9!dJl5P5&qdRl&M+VbIOlJ984KUTuI~M%&R>JXbrT7BuOnTsz0RzR zesIsJRyY0`^dM?BN%H+$r~j~*3XF$VLKs>J*P%U>3g!HN1lzj?zL~OT9LrY@5`>d) z_PpIyv)Mb)aPwey`BK8NxX<6pjRo!k!*%Ax@88pIs5cnr?&$0QsQ0&d?B)J8uXeck z8Xh;Vbh-Iw^tm5wpX=Bjcf5(mX(m6P)6LoI{zIJZhg&+`!D@Fq{;ck1ncFbs&3fs_ zT{Rj&a|h~-=P;P@hQy#?*JYbl`}`aa(J(7>?|GFpkVm;5Y#culS5ZhkAyxYA{U@@CJhbhJ*f(kRWLf3#d0 zDddS2$V)L$arCixc#&E0y`Qgy7ql(;Il442U*WH_=^`wx8>3~P&J;;MbSA3IazQh! z8Wbg6d?`=RFRfc#QnJ;uOBNUZEi33b1wB*HLfenFMB9(H<=tXXt1&yR)c&nDy$#$C*)WxuZUqNcQ|sn@8J^Boto7N7GLRQ1o;)C;p*ejfB zzgQu8%H^qCE{PJ^G&KW$w7tBz5jiMYiN=YN9H93x zQHJR+xKUqTf6S++8W}|WJ87w*lK-~VpH(SawBu09e_Qg;tCY=Kc_`(-?fmCe%I`b| z@c&(70RIb)51haIAewah*FF)A-*lgqd}z!q9e94bd|HA%4Pjj^TR3>f8l*jB6@Bum zZ}JVYp;&gv5*M{`J7ZnlZg~t5h4Pc9oYXzfP4eBOwwu%`Dyx84a_ASY_#)ZxjYA7Q zibv~* zvaw>iD-~1WD&~N6H+j#iNb@Vw+D_Uke>pJMk==!g0A_`74sNTN!&_+PaHVF*c7H9s z7{7V^rM2?-?mWlywyx2qfzO3Z$umSPC?W-xj#t;1U`~WC#=Liaqi{HP~YH6iD{9Aj1-@b(w z+BH&G#}$BZOJ7jnU9_DqEc{Am2*Lr>iw{7d`kg1=R~%SFN86W#Z6ot)QFXjBs_(_ln}gjP-^qs}ItglU zy(O;4ei_#Za2?W#=Z3%UE6^pMw!{~18l?`-x^KEc#?12*1c7oj010}Al&17Q_l=yDv z4V!x4UEtip18*tXEj;ixhO?aqZtoSFd*Ig(fTYsf@5Jlm{7G4O_4d%BhM(@7c=_tZ zcYnjW$iJS_BT{KeC&1C7=FGiaobLfxq_YV}3t!V+<3tc={9fG!@DwSLxSCGKf85{4 z**~+i>S`yKD$_?ds`ciLZ%@u&TSfZSXy zK#1Zb`9@EXoM8R6Ld8b|2a=Lag$1LoXk9AZb;BwmpYjdc>nUP`s-Oh>PQ85-iJMLlRTwC z`kOV9x4`!M{8?TDL)lQEI2&2+UdjRU+FcL55=hh$<(V&2*cA$&ad8u5dfR+yTC#?q zbb|h_ygf@zMSdtD)cpKB_*8?HGUO<6m3J78VRFkZQ8AzlPjyD~f#nVtxW>f-eOHie z2UHCpWqUl+3UErdYPG-oxaY%6v)_%v6+Q~ZD`H(%l6n~J$MncG)4RXgDJe0_U2i{E|UrtcDw8q(q0cHE2|Cu1oa+@m-3 zSelEn9u1u`lI$%g6;&`tNq&C$^4ixfIaX+9?~5j)Xuz3$%;OxZ(gVIIp z$_d>}F4lGp)@3*i1{YqZXjarJQL1jJO)9lpGTF`CaVjkt}o$dBhUzrd`@?A|+BT;}^c3NFu8a zq9{fvXKxUpoWJ1+1urI}V)L`|c+LmwoSPVQi<$!ld5~I(`#j^V5A2giFG){ex0rCu z>mCQmKvq-V4ah{-qF-ipIM|*}S@CBZ>qJXvHFsr^XSdeP_Pok7?N(DPg}fHcEA_!t zv#7SGySj1i1*_L&_Y2&z-`UTe_3T^EZR@#XJ$J3=1MB&)AVq`UJbTu&Z#}oI=Z^K< zwVn^k&+ZYFyzY0dfR*cU z$o~0>3VoeR{oPi?En5)|Q_?hmQZ4l(z?3&d7p)oj_=3oi`ekN$y>mle<(!u>ap$tD z20G=qmC30+$wEP+OnxoR(DoKoQxsvG$zWTuHkrw&)gVm4(ZZ|K?KSx7v`&NQK2>Y* z)oDqC$hV#>Zl^(@S*<~2@@r^j4Q@g8HW~!*dJV#n9W9)mZLh)8vpNl;$6Bqy)3cHW zk#9X&+)jf)vs#15^*~W5kI&XoRhkSJlv#E2X?|^z&gjr36qbi>tE*|#K|V~x^`yMY zH%`X0DFK*eD4ZW~l9>}u05YW+yM7$%{W{{I`cfJZb1$TaeZ5n3Cegd~8{4+saneDD z9ou?i+qR94osMnWM#p?Rw%*wO`v2`Q&faI7JxWmv*YX_q|nRaK0F_zaG$e6}gR%gWsaRD=K`seV_pzh#ma zukO6I7oDyiubwlJi%9ZPA83{UPRItBD;}nN z1ir?0htK|{)&o%MU#$_q^oLWoM6|soE%w4)DKgjY`%ou_4SKzsBp3X=%NhrlDtl^a z8ccf9vM=u&T_JY9WH}S#4?XC#Vv|FSCIa7@L9hh|t{+pW@-++2>Q9s<)*%7I9`J|e zJ;yiLxzgG-zO$)23j=_*1%fGbS9+Z!YRIPuWZszHi~0hx2_`D0O=DEDNn{)$?~!y6lwQn3knv8qt@7Wu0wNm6BG3Wl@1 z?q0U)wZq^A?FHxGAdL!}ibZ4|ux54{t#2p7NE)OT8(w)HO>59Wfr5Z(WZwJN+yFr# zK3>6>Y)fYbJ8l$m7zIUdFr8J4eqIY6Eo%H2HPfJjlAZgV1WLh~L}Qc^+# zn&#lFm}Jgcp7Ixxy2yTVWR<~$K-OSiDoaChvNQe-PnmB~bO&+~O;*Fo7Z50jyLc2*h ztmudEWBkItQs4_06cg)W#_>HAfQ?GhC}K}XIKz<()Feg7#AC|JT5N2L_DQ$W|YqL?duIh(yzE5Cm*`B0J? zhpg0A(%#*jNQ^c6qkZ5tkm_xOB8zBI+4*wC90ot5 zxCR@Nfv&thfP&WSdqhddRI`+{@x)D#A>zT`In^zGZa~xfUdLbR4`HyTJ0Q52E-$#y;J)6UkX}M=tCY_iiAk zyv@zPv_mTHk~XB5@wN#eaL{8`%fxsQzpJo`K(1%=XfXAu9^i$s%szoZ%K@9ZCliM` zT0?$phw)jlo?tOX{V2CM^)yp_K&kYIKH#d{I+qa4xNSLuHCRQB=$mDxh(AxWjl9td z{fPrOm**j#a!=baR@sj&)LSxnnNYS~;#1fevY6e@__peLg=yxMZ1;z_(NG4506e&> zjH;+NFAWWxQWvnX+Cg3KFSgkm*!_$7`hYEp%qK;aS(1sFW}w{PW-3L5Mc0h%&b*zF zElciX;}!tXMw7>-)Q?WiO>EzB6lI83P9;1+=vwB$L)fu|_j?LYy{&WW8r_W0h~|); zMiV|9P&_w5UaXuod}986__QOxKe!fmXKI9H-Y4uXpCPJFI^RhmA(%WXVk4Ll9s>8H z$oF`U&nYyZZkYGeuWPrgo}n1<-X6l<#9C}a5gUMPX^_w^28ANg&(PeLp^sj}O{LW- zSBU~5UXafh5#0N?>_$}PWbfMdS1XD`;dULbdXB9QU(EaSHu4wH-zhZBRD79*e7V)< zkOu)(LkIDflB-x{`A@aV@<}GVuJS!A>5*kb*S1aKI+meI`~rvcF(tSC10^mkh0t{w zdotZhKPeg6(CmkQ`2mB|*mrsKy9iCCHzN#fM4+lcoZKVG9H3KT)+IFDk;!X zP}S@viUkQ^wMNzrIi|&|q4Z9mS2KR+&_BG}J2eYleFhK3VYVM)Rd(b4mCG=V5N~g6 z;ahXs!_3&{Zoa72{d#H5rmw=?e{USxHW0P54woGy*A`t<0cOR#k|Td9$x9rcZpnb$ zD6H0BV&)IC031d_Xl*&h#eLDf)qGcW?%Cv=1;^SFc0l$RKou?ES4_B?>sbz@3@~9j$NY-*96V3TejJPCqk7H7 z;<>a@cq((I6*D^emucTCEp}|kXy0oqrdY~#`U+G%dkYZAzqj3Bi;cKU+=n0`GRwy8lvU}M`1d3M-dIizZUQg9j2y5GqZC7I+;EGH-92w!fboPDGGo$@>~x5&^k9_c#M(%*61v+ ze=rb4857Tbm58*M$nrW3nUp5oYJv<2riXU^X3{|X`@Zj7zGGXrK{{;@G-J-vAYq>l zDMV5bLJ}$pZgzj^KgHi15~;L?jzhg53yVbtoLoj1m`1@d)=^NI+!PkXup;d)40>WX zE~7M8_EthbD-XjCqUW(P{vwi?H^c~l|J`O`!CHaKDOtEA6$)O~EedSwGckK*Csg_Q zTE=a9%28VI(S$a~*iIMa72iS#g{A|CM%j1?;02kShw|S*` zU_7U3@~`TfX{6{8?4;d&9{wA89mVAFFOvI67i6hZux(&m7aBu+#&dIW5~G@ODydxt zM`W@uU+>0#O_l-X`l)*H!?y+Zn&ywl`pvZZ-4;-lPlHpOLqYFmAyIp93`C;19dyZ8 zxRb5Q81$KC*?(T{5TRx~SBo@qa?AhD8^ulQwj8uoy=YFcmj8RLPDU)1r}Ouyi>r17 ztV{Qfw*}0VH)!?Pe8J+wCv2Hs^J=%zU^rYO1V9U_jir zVe=Amhp#?9$djs&QQ)mUxDN8COk!?S_2M-;KPF-CZdPv8hl;Qu9fT1yr40Z3Yoyz^ znDpbMOfYQG(|h(`ICO%rC=B*rYX!`Bck#L*wHe@U!eHqgc=|n|K7UP=>+y1~#KUit z%+@5s^Ae3#&($3b|MJNZLX+o?&LyN5AX9N3@r?)dfSlHCA3iYZf1)rBPqPUIvG_J1 z+a^H95KPF$=uZ3)xo}mD>w)WoCy?z)QDVtRNH#M+x`&Ps;Yva~T=_1pKnl#Xrrr!H zoe~?#W8YkTZAn|4ziQDP2R$Fuv&P<7 zQ2UE}RAFNHP|kX0PGSVs9Bbxr`7(FCi&)?@Adm4JLkfZkAMn`wYr|tOg1Hg3{WJ#E z#d)e&1pNhc?Y}Rmq91ZdR)!6?QMe)2&{oS+fQ*5IRajcipPD*ey-V);dY#*U|E#Zk zym0W(voAE-v{@i0$lO*+EyurzA$Fe}Qn!e!8JmBel%sXK5TGGE5Bpr+C6M%));@<5 zFC`83-8NSvEJ?5=NG6jFKyLgCKK|iC7MRY=iL%qL?LO>-(L8|Y`&xVcUg%&p+Ovn0 z@Xh_3gBd=%Xv%%w)#7ue301Ua>A_FLLg~|S+K~Op7kbm*W_uzu=LvW(O}8f~kmUCI zOS!PLNurB@(yBdEF20W&UzyN!+@tDMNbBD<$``R`J^n3Cb(P$4z{{$>+;5&|&Ysbo z4u7sK*Nvvv3^=I=3a2!{V=B4Z-<*>gnezJ*#2`0uDG6TpXX z>3nRbJ2M#AMGP1i;=i3;wpJ!)_AX}3uAZ(VemX9Ml8r}v6xXCbo+;QM3MC(7k7K{@ z!es?B<`hVgBsFR}tb-Al#s}KxT*6p^>b6-NQq?!X4mbU@!Yru3mH_~O*KG9}s6Wr3 zPSB!Hp{}&;I2|~BY`|=Ri~q^p)0zEC61XeWhb^zOqW(BU_4Y{$47jYMc>81tczN>- zrDZ<5=%ptm=>k2B&9H+R}ai&W_oyM7NZmnR?jCEWTAB+J5@Hj>Ct-O=Qp$mS;*9B;{jJ>Sl4l+vT<`u;KpdTyx%xOjj zCbQyVl8;57MbK<_dqGMOiu7*oqTA}K+TLOm!RhByEvDuhie+DD2SPmd;bLk}I|&vi z;(_ywrDLBcc+QL1PI`pO_iok>cxQChcv*S1qzf1kK&-nZwvDK)C7lRubNqU#^{K|6 zVtHWJIlvAn+{Qyn{9`$%aIId$c=KkWY&J_a);it?L0u}^ZzUqM>+q+GAq%Gamt@>M z=HBy-<+`C!#uEVtk-qb!5TF}UOLA*I{Fh|>3nnJZU!W9^It?tId7ayOHY_$w;F{@S zbfEdH*_-DN_+&%;m_pyeGLPwCL*|%j`wU%F@iFIa4BOnhXu-E8&T+sGGU3^~R>&^s z{V}D=YKGh~N{QtO6gA?l)k=Sq!1V9nW|!cJA>AwYj+%@=cD+_2nCuYxF{w|V_TUku zJww~uw*nWINt8^tCbnhOkKEubXPzjRiVKCRrIW(}=ZU~V2A+2mii^S($(Xi1P zHbrVDy*ilrKv4^z9dqj9EJJ@JbNf&@#wqNZV@1e7;n=>RPLpsj9zbd0F=Rh>z(Mu} zLB4@7M3pXoCkogH31Tn@$*zee20(19Nxk6P7Kki=y?ev~yC7tDn4g+VL+@MFBsW>~ z-U^DRt#n~|g7>>Z{1pI>_6I>A1mVIgd<4XtSBq=&UrAOJr;Y|Bkai3#9?0{)B`Ht# z5VvT>hjp?u934wH(<%g}w}XG!Dk1NZ?L2pYRfFNGKPXHSBC+XlTG^C#91Q%jn z-{&V*al{H)V0En=aUke0`DUlnb9~h}OGjnZJezi20i*lsY!op1lt-%{p4wAbP>N`9 znxyr8QCR;70-+gjHNdm}o&NJ?ytSBqINCxB3Xmnh25pjCnZuFkg`y9IZnttnC%10g z<~LaSe5D7(5^)2F0vI>>rxEKV@30LHg(W!uI0pkE>QbsZcbRN0C0A?~y6&~M;DfH| zQaHMEyjP9Q^oSh?Q0l|!Ze%l*D?BtEGF%Uh%ku$Y*L&BC5Rh6lKWl#3Qs8WZDsRgB z(t`RIF%KIJ&7n1`gBCA$(Mhc)mhGWwO;!_#q7jB&ihUw?#9Y{`99u0X1<07rrg0V! z*wJ(lQo5;XSV@2qny9Um_F^dXc3I(qmjkPWV0vIs zK0?W5SzF#^<6YGgaO7e64fp|iJyQt(Iz)Q3SJ(JQapviWubzu~Zf*wttoJ8#_u*w= zQzGXVKsWGHJy1XAx|!}AcCWs(C}40PosehwK^V`&o>e{xE{l_maX{fk9Rh1Hod~PX zE%J!x0R?BItwN1q3&?==Ul#aA?$sL3n0=I?I3^X?p&JZ+4QAv7G36VqOq>3rP$2Px z7hVvp7pQcvO!Zo4f4wcLpZXQk#(Ha_IP3|DvQK-@ZZd2CjjwFVcWO|IwAE|zH2j)l zUm1XYcYHx%o1-xb*w0b;uttl2*VRw=%AQFB3>bdyT+Zp;x3RC zxGS1`y8wEMT%&q^frRpsx}t7EioiFPocaZD9n3o;<`kA2vCv2?)?Mm>ffa7RV7B|2 zgMb(uf1acjKb-AuCBCkbFp2eudC`(j-V2~2##}>Z4|=ZB0{xgSN#MeZmy0qVxEq=U zjif7TW!i1UF=MYKCD(5an8RRmkWl|P`p$%YZCe4Tc2J-lrF>D*-hZoZ&EY3AbD0r)*j*lN*%>qhgC2ZOB@``n<1vA zk#A&$1hAS$3}gc?7X;~wA%mM=Bdgf_nDv!2j4 zN#}-w)oDFbRXnyHTx)(^#~7bmoGLhBhnNP%wd{hP>kJvOTwd9cUk;&Zpbj~ZE}~mt z>K_%fr#!tO!Vv?yjaF4enfpbkEwj^A-Oxm# z3KH{Q3spwvP-u0Y~bV{N5#4fkos52feEIm?b*r0PvUerdeUA_DL@)mZoQ7xD(U#Y*HO4D(y z)KAqUKVqueU8A$m6-lBI;6X$c)ORGWaCRwXTV8Ja#3N@L;+C0lrh>^hl+lESxI7Ll zA3rK1D-h`Alu=vD_qAJBL~y+M9)N~P?FEG&5*3!js2kz) zoihZDKk--18n5ba+2&~8UoAx#uB;q_=e#ZO7vued@@Uik_t`Sm* zQ!&UP%D@bup6@ypB0*`T7(`HH;jNkzlF0ND!+PT7qmpOeVWT@V(0mv$om<33gz;Zn z8DXZPOoj+YJ=4&N)`Wl;>(1xq8MiYgk({`|QX^@Xre)+g>v7^}YK5MaKoE?xA38HO z!nVx4gg{|okaC=hZ%T1F!DESk6f=}^mMf?fEfF-X%l3FVRO#Rqah4+p znH_*J=b}Kur*(4l>YDkNGBlsGCd)yj%bc~q#9tZ&!V0d;Vu9~VBhVq5dx!0r`a-Ao z(e`x1et4#`C!TY?8ufUjEe%FeH^jvgA|r0fkK7*wV2U>+fGye6n%KI`nxdw!%#k%cv&Y_lK zMK_ju8sqEAufyY*y0C{_i(9v1ImS)hWWH)G?YfgevG(JDpW;!}W=&N~z4M=VlGSuN zY!OcySg9pm6pYxGN zX;VH?FXG9yN2%s%O{vPWDPDi3Oy@t*d)`&U#cyLBbPnSqC@2q=ok$Vw>XH2(obV#+ zV&RE|N};pPJAMnLGNzTaH3$1XL9+9ajAJiu zkf@vjr3<|H;kHNY9T4>rJc%9IM2Y~|@EkTx6*17~GL9uQqs7Q9^JU`dR_|mlw9=g* zta(WHokd>^#re~P8N3hGR36+^UD8Nz?*$iI#E%0QbCVy&te(!p<;;_Pmpz{>uI(2b zKKT_7rcj1DLB66`nb6NySwwFqLh_R=>(ny{9p8UPi-O6lfcn&eGZB}yk> z(=sn?4!sIYN|1ez{kPzGEZ;R{zBWiK#?0rh>+s4 zung#LskEjZIeO~HhA$~f;-?nexZxv2Ju|5uDJw=UcaJPNYNcLuajMvAFd{U7#P?ms zuA9m!i`q`hz<_TU??L6RC?StW!Sms{hW+V31?$dCNsXMM^o~qtcga}(<=t!MuFS9= znyA;E!!~kZ6&>knxv6+HMyY|Hq1t48e7{3W`yex2y&;lGoPB((0aR>TaIYqEot9UF z<;y~i=PZh{s63Jkul>1sUk`ZSmrP;W*ov!xNX03s%Pd1izDz*nZ*LHT#7MI>I zad)*8%B<*#MFm{NFs;jc`^&OYet2Un!$n~|zc%MIXC#<_3-79KWl2B7@296$?9Pi8 z)=FC@;1ml?%#1`yU}q8Gnr`gDh(6oPDGr$)Dh#K3(0e}zP)+p#Jb=*6VJN5Bq5g-EX>g2u(Nr0c3AxT~yw$^1?lJe^tI;iv7t-v$BMlaBQaSqhGW~_u zHEMtPnu)PS(jJ)&>Y3+B#U3)AGFaiJMn^R1|mh;XfHlFjdKQE!N zcPkH-v2r3`x|#C1ZxTz9d3!uU;kwu`AiSgY9i!vIm$UfexoJ0*?4NhA}Rn6S$O{yDnO3?AD-$iymPd43rr^aa^`&-C&kWT3e@v7&B7vUbkwb zWM;3VM4nZ;r=IC$?E%cRN4xnv`N7lKa9!`Kknc9jt-);}Pvqi(C+7QTxWh;p5!aP}5I2 zH?b~4lNH#(MM>>RHJ(TEe&DJnvUC>umr_zk#qV8SKj}L71%BA^e!qTKDv5zt`xE9`JjB3*=b%Hy2E;S&z z52g$RCIUaNV`@Sb=PV&5#y=MM3Y&$=Tkl)Zx4o~&x8h(5 zA51=i*PF1PLu8H=USRrl7t4m;ymVS;T@>m1%~GLqAbd&1Q+K=}f%V&tkNAimtzumV zw>(I^2WhKTmh-KYE}<${hcq%pG)gwG3WoLa8hXop`dryM0CD*y`so7920~UE-sjCE~Zqd3zh)Zxgbsh*-10_~iDq$qzN*0ySvAu`R-o27dR2+5ksrYjgP|5grCd z+wl$lNz&s>F=BOS7v$4=u}#KJm>Lx2QU!p!d`r!0k0?SXTUj>=MC!qa-FswS!6=xA+(Z~M%wcn#shB5le}A zq63JmSK)!PTs2zh+F!fs$s)Xy?-*&cao}%Jh_@TEpsC`t#j(Ow-iOS+LBfVcT4CCT zy$x{SC6|~laiMb3lLa}X*s+z@=^E+60Vm$qSr}g?i#dg;`1;h1ZQm-=FU71KaA_V)`u0PAY2@FY;rodEYuKhK>S!fjiyAbQ<$d~R z;x!(3D2H&Dx7Iy>=dm*0rOSH;oxrU7u)e7N?MNtCeZ>Cd+J2LDm5fe?Qqh+jswKV3 z6WO!fXabNWHPoBWpW_Jg*}igF7VIb79?2d_ysPO6PO#3)4-hYsJUf z)f2A=>g_nN7I5h~Z;JAx7;`CP%Lx98B(}WF(CYh&U619Q$!&Pu3((3RYoyy5hY%9LD6@M3t{TT*iKzFu?vzHQ&wH`VNLq%dvhnwG#WvRbW))9##SlgY z8&3p2w%=(E!#Nj5W$Be~HlD1LG5JuSH&7ndS84S?ldKxqv0x-^6>5Jk}y;`$io>EOc zy?6)Vb-cu7%az3}TVf#-j*w^(`ld#rNk?|7AjiH2_aQ6W&09X`r7$ReG{H5`AO&d! zQ}T(geU_EN3jDF2@uq>%|3|Ur(i3$>J)dec_4cwMbta=-h<^dBH~*Q(hcsyFj*ulp z;NqPsZylD}GGby0-UY-^IjqD7W~Q4#=Z}+UHJaMwQU|k%o7*UGb5&G{KpbPkDNO+J zQ*W8f@9g-hfAFtB@mL-l*1Dv0C07oGO4kXs(BL5%0Xug=p&2uE5$=IVlz5JU3i`qt z#qr0xE*Fso5%-?lR?dIsc8vT6rbYa zDjNZHrg4(|HLdl$t^&b)#bWKxhe7F}U{U6S0@n=h85>&7>OZA1^eAL{{_FSwCiQh6N>GReU?=Y*yy| zMfMvc?!7BX4M>-GrCgxotlaezDS0>KiNfJ}Th|#RV;~lSuguVZ@NFyuf368=YQkYfbllG{lecfyG;swCz$ckMU2d zvO4;^PBd+(+}<4#(a$q1gA@=Y0<~DkF<@-AoV6a!=rrD1&R8A59njB}jg5ItCcj<( zd6ZwOgKdQ$&@ryCu{Dy;Qz@otg%V2iJ*Y%Ie?*Lz@CdLZU@cwb$TPC_n=&0D!Uj{C z>n57zH#qBEkCNCkX(`(QmyKi<8Ht!d~tR26yE4%1f=ESpwM+lw*Er6~N&1uE)H zsl4O@a4rl?4lj^WkHA0gF<< z`p%k!RnJYT!~QxchMQ6TmuF2B8~?WG!<&~ynv~KrVrB14HvA_?aqB zTrxf3fFI6mU>|IcWf&XN2;uf}B)%R-#G(6cUpHsN*xhgu-x*7Q=2CBHV9#jQ1Ujfe zDmejTw>zM3IH_}0+0{|dl00U(;u3L9?1N?WuP^98sUvxR{sT09QIw7Dk@x-c57)G|3 zc7AX7lUoAn$d*4V%T3=81iO4|7`=lfo>K6$+$o2vcT!AxhHPWof5$v#q{!!?wodbVmRUN*jIqq+?U5-n#PCc_*7e<(wlr#5YBY_hblGH&Y0Jj0#S^P&!mldUTJ&-X}uPi=vGlc z{w*q7>H`=iW%GBtN=x`@lbWFI2o+pcucRNYTNs_0Yv7^3JIRh^2lr z$-!y&b9RRMc}|a;SX#ap$F%XAhe^9avA#L9>k#d&gkx@=XKodo|BEtW!#SXsm85@) z=TKm`e|g3UV>lbICcdN0yCft+Z4jI+=A`5vL!Q}OMy7GM6;HqIkTgHm*9cp_fndOf z-pLP$zn6E$4)V3D3OvxTfYk7=-qUe=xfy5Uh&{<=WCtIm%blBotSG#@JcyCHSgG@n zDJQemHC=K68$&{xn7{V5{`sn7V%YPCP6PIkfwz}uBl@08NCk;K+fx=i5i-Id^JN$o z9%uS=P7_*7ePiGc^J53TByq9+^V=)_yL`HWMO(qo2-4)Pel5x##~nswEfq|nd(HFQ z8&K_8q+K{Hlkxr&iOWe*+}mXl-G6Re z>;0SN;c+IwGt%=Fc=RLt5(CbA#@!v4nDJujeo~gzc#Khe#$PF?N*Igfa)s-hgI%$r zVdapXj6K74tlpHr%P4koT4qCp{XxQ|i+h(NR`Ik}Ed;O5v#atU2s_HRHzDnpm!N8@ zJqQ1eR2nd@Tlbvwhnke-@Ev7UH;84~mM+49n@FW~wuhr{mGjvGGZgVT#|FJAApF2{ zgjHXBXTwBG{uyC^3yimOt|VO=F``3A*n+M?*7n5K=3e3KLu+O!|yNak}eAjZH@=y z58vsei6tv3ld;D|73{6@!!gUP-jNr}F2|+1_bRF`0C%ARi~`L>25rL2^$;r)+GBtx zN4~+}zR=>{Ay3{K^*o$!yPz)SX_?^j0NlK$U9d+x7;`=11VWa6iP zV_PcRGfXIo;^7V%y74ocW$9n)ABD-(r_HlAgM_!=Zuj*xs{fCiJ_M35(gM=>@SdG2 zk|IN{eQf#}WO_(a=scs0{pb$nCp;D1w*}c%l{|*>5XiDz)M;jRK@xFZeL%87Vn{D* z$%Aye&8&|QV;rGgOBuvXMc?M4Mq2+gcWBG*yXmaFuPKP^zt4J>MeHC z(-tJc^xr8FNf@U+sdztU14XlLspFq)MzRMZs8;v7G$CCN>q$gEOHIge?TV-8wLS3S z2V0(Y?7jcY#@MDC?S)XMbHT-?U_zGAGOl%1ybEGG9Hgo`kEO3K z=d3~zuHE~yhMgy&Vl-p9MpX@SFYy(b4mM#otI?9evR|&=_!y7X#rS-PW*B2sRot8? zo>ZjdPJA4RCnQ9QrjsbVc)@mh-5U6nHmp+$0E@(P9Iw#Vp)OVGT}AT7PIl=gn49rU z7av5lAD5ruB`?$oAFduC-VT)6wZQEA$IxVbk) z3rZf268}-0J?_RTqD^LXb5&3k70gm5WM3TwY~aul+08wtuz8Lxsy33+CpN@Y*gZv< zkKHP(-*iD2}}+@I0q4lxYLyfMpR*_`nmC*R(#NuJc0f3Ix!x0`wm49J{(51thJJdGE*UlM2 zXkSO8;Ud4-Ma`DmfU5huJ*s+T_FcR~PnkK543E`y{32;Jxlwr=L+NxsFl)~B#z=rR z2I04a+T7~RM$L4SEI_GGkXkUgQc`u&N^ypnjXFFTHVWARc3}TT*}bb=Np=JhtHyI^ z4Lip+--{Cy^A45NG10-t)oVr+O7I5h>**`#o1+s|>UN>Ug;J8l1^089D7|xpK~vL@ zqR|5<%|x+(y^?{P5gpW1Fa*lfE0sPOC9_w=j;hIEF?fn4>j`D^$m@r{L!VF)-|!`f zTBG@HHBegfpQ{x&vb`#Ot8KitCo-fyWHjA5mCTrVqC^qHfn)GFCB487e@bOrd(VZ4 z@#SJ@Ihc&D8f^Mc?9=U#J~014rP|lqURcMZX>ZZ3Jp~ESr@M_boV3*iHLZ%+Q)ND= z%q!z_efz=NAP|BPNSi_=>0d#-P441;9i}H@umduCWyOZXTFtnHaK(;;4mw}}Sb|=fKrSJdj`XU@2 zDC6VJQCG_^ao8bG&Prfj%{AJcknd!{+gs?}Esn8{`F_+kn0?{2QRtud5a6^+AO1Tt z)SR<2iv@id1CU&ZGk8yU+roqwztWq`Mt`(xUE%;8Y{lFERJ9!zXul1~2@E=+UoVZS z`x{DISgz#Q&b6(~QGF^@b+R>%VKawBPN(zPj7*WO{5AS`{uW#A?%GEAO%Di@&&^aLns~t#Ga{Bv--kb4F!>lJBP>(BK}%Y;bk_31SuN%_E2$gr zKzuQ3q@gy+H7bCd=YRF| zd-3<4x?*@kxw}gSPQP4y*m_H5ymR>o#Wf5D74ebz2d`UR3F!y?`z;o<@Bl0PlJsHY z{@|Y^Zvh3bwYi~ibr}c|I4cN#Oz)qgr>E=hk7`Q;WC3$>^NZ(pHgUpp4?q?TleDWJ zv~Xn|C_B9vk@V&NGIQtc`Wmd$dSmVC8zhqJa~b&9yE}Yg!dgFG&pz)u1<<%cVJUsM zyFb-|-e=0+4Dx1?F%t2F1%Dgp$*}>tK{uA}W3n^7x&btZ!7T>8@sg|!rNFn-h|`e| zP}^y!gmG@yY+k9%eV32$$cmo6x#l8bzOVlqbyxP*Cs&uD_J)GPj73{M*67w2M#lNK z{c_UTVlTlI0CNrgI@Sa>+u}X9aq6sQdLWAD*Mpb)6jE}@yNFB9mp7kTu;d0C$%kN9 zcd?x-$wa6)jc0g(BhCwiebO%2pczfmmQlxZEGaZXLFhCM znxWdJ5)npkHamwtJ?cE@UN832CeLp?A9(n%NqlwicK7BIEFNIO%lYo^4Q<>o{@Xy; zw^yLA4ET(`>dr(vv{z(Ll27yYc=L|(Y`pgJwr!p;!-_ta0}t>Ff*Opp%86`>zR^VvDTyX?tv<%`mp?Ea5I|-ncQIXgHZZJ#QI~2>YC613>+$O(xsoeve9J zjFCRgXS^Sx>>X?@g(QT{T(V{~OC%pj4E!F#=Yjf>sXw3FcbzNqb*HR<;iizXK+^1U z{`*VB{if2Bi|TK?zuA?`q_b0qS)_-~N%kLVc!#Q=bMh%PmD%!#V_kw_Z^uUn*Dqpm1z5&%S?YQ>zgIKHM2-lr%W8bX0ljavCWjZMK+y}7v8Ix zw)qeHkqf0nI{^8kU|c7e$&ze$CxPZkHcF$*@rt<*B~$lrzttC%I)1QTH7@3^x@<%R z(lgOjEkOB!rmZTEkuu=1Y3l`Rqj43t3@CJ}(Vxc#Jyd?dzdy^~vN4L&=gAFx&Wk*R zS&xHX^zdA-sL;2%n|)sOA{?WII30mAqzIa0)iEOb0NXylXT3aS<@&)V5mv7i5CSym zLDn>JI;e62=hCP{9(8oN9v_FIz4}coKm%`Vm}ZX5Zy`DRT1&9vyrep{q1^Q?+VS>o zq+UOUmcTXJR)&7~WkaX6rR;Q_aKdn5YCETpNE73(hz&C1^RD5%RmksY^X~2rDB8j& z`nK<}l61Q{8@u?@d6-Yt@eStdln|5ml$oXN7#B~8tD(XvCb%1&W?Ll!87Cua(GF`# z8}a3b!hxLJ7ckq+nL-BA3U}b}(Of$-Cu>w#Sztjbx%+3b1Jo=1c$>n0K$zTtv7zQ6jL|6EI`?jLzf=%AP7%pt<@_G}#AeB9p)Vr0$+2l$~< zo>D2E-g|odyL+jHdvflI7|q)%#>p}1yJo52k|LD+4u8f;Z{&O#`Fk3l;Dmw?Yc)YF zS|gjwRvCm$qTQHxgGC1(XK?SYUO1PPIB-d1G>K(Bf9h zgZft$hayP_pWcW=@FZLGPld|Oa%W=tgOZ2bz2*p%n=4}WNwv z7#vQX@K#c_3%J%PdRq?60Nb%5A@a7J2HfRP>J-qksjq;}LjovyV;QIKe#1Wz=hT!n zeYBzlIZBJc@x*59(fyfqJA$&#(5x`>)V^BJY4?D)KC-OY8~e`FQ(XmYHZtRDc$DYa zazS(O!ZIi&eW`baNS<6p6En;6wZfpIPU;sy0n)ew_Ktnt5MQGo<8J6`yX#}u@z@99 z-0SqKQJ0_(h|A`0@fWg^EI0%f*gyC&7#x^Q#FNNUxQ}J97#Nr~B?K7Wzv_P-WMuz! z<@)}QLt^e`Z{lj@U~gpm{}4$2r^^3ERQ_+3_J7*{SLOf9SN@+O{~HD6zeS`0{}K8B oXQKR1wg1g||KDnq@&7L$zLG37%zqw2{W~$h!N3N4{&V+#02Ht@@Bjb+ literal 0 HcmV?d00001 diff --git a/6502_functional_test.a65 b/6502_functional_test.a65 new file mode 100644 index 0000000..aaef2a7 --- /dev/null +++ b/6502_functional_test.a65 @@ -0,0 +1,5597 @@ +; +; 6 5 0 2 F U N C T I O N A L T E S T +; +; Copyright (C) 2012-2013 Klaus Dormann +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . + + +; This program is designed to test all opcodes of a 6502 emulator using all +; addressing modes with focus on propper setting of the processor status +; register bits. +; +; version 23-jul-2013 +; contact info at http://2m5.de or email K@2m5.de +; +; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; command line switches: -l -m -s2 -w -h0 +; | | | | no page headers in listing +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex +; (code_segment) and enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; Please note that in early tests some instructions will have to be used before +; they are actually tested! +; +; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled. +; Tests documented behavior of the original NMOS 6502 only! No unofficial +; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will +; not be tested. Decimal ops will only be tested with valid BCD operands and +; N V Z flags will be ignored. +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceeding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 28-jul-2012 1st version distributed for testing +; 29-jul-2012 fixed references to location 0, now #0 +; added license - GPLv3 +; 30-jul-2012 added configuration options +; 01-aug-2012 added trap macro to allow user to change error handling +; 01-dec-2012 fixed trap in branch field must be a branch +; 02-mar-2013 fixed PLA flags not tested +; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0 +; added test sequence check to detect if tests jump their fence +; 23-jul-2013 added RAM integrity check + +; C O N F I G U R A T I O N +; +;ROM_vectors writable (0=no, 1=yes) +;if ROM vectors can not be used interrupts will not be trapped +;as a consequence BRK can not be tested but will be emulated to test RTI +ROM_vectors = 1 +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 +;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow +;change) 2 requires extra code and is not recommended. SEI & CLI can only be +;tested if you allow changing the interrupt status (I_flag = 3) +I_flag = 3 +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, $50 (80) consecutive Bytes required +; add 2 if I_flag = 2 +zero_page = $a +;data_segment memory start address, $5B (91) consecutive Bytes required +data_segment = $200 + if (data_segment & $ff) != 0 + ERROR ERROR ERROR low byte of data_segment MUST be $00 !! + endif +;code_segment memory start address, 13kB of consecutive space required +; add 2.5 kB if I_flag = 2 +;parts of the code are self modifying and must reside in RAM +code_segment = $400 +;RAM integrity test option. Checks for undesired RAM writes. +;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k) +;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM +ram_top = -1 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +; +; my_error_handler should pop the calling address from the stack and report it. +; putting larger portions of code (more than 3 bytes) inside the trap macro +; may lead to branch range problems for some tests. +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +trap_cs macro + bcs * ;failed carry set + endm +trap_cc macro + bcc * ;failed carry clear + endm +trap_mi macro + bmi * ;failed minus (bit 7 set) + endm +trap_pl macro + bpl * ;failed plus (bit 7 clear) + endm +trap_vs macro + bvs * ;failed overflow set + endm +trap_vc macro + bvc * ;failed overflow clear + endm +success macro + jmp * ;test passed, no errors + endm + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to allow masking of status bits. +;masking of interrupt enable/disable on load and compare +;masking of always on bits after PHP or BRK (unused & break) on compare + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + eor #(\1|fai) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + cmp #(\1|fao)&m8 ;expected flags + always on bits + endm +eor_flag macro + eor #\1|fao ;invert expected flags + always on bits + endm + endif + +;macros to set (register|memory|zeropage) & status +set_stat macro ;setting flags in the processor status register + load_flag \1 + pha ;use stack to load status + plp + endm + +set_a macro ;precharging accu & status + load_flag \2 + pha ;use stack to load status + lda #\1 ;precharge accu + plp + endm + +set_x macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldx #\1 ;precharge index x + plp + endm + +set_y macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldy #\1 ;precharge index y + plp + endm + +set_ax macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;precharge accu + plp + endm + +set_ay macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,y ;precharge accu + plp + endm + +set_z macro ;precharging indexed zp & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to zeropage + sta zpt + plp + endm + +set_zx macro ;precharging zp,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed zeropage + sta zpt,x + plp + endm + +set_abs macro ;precharging indexed memory & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to memory + sta abst + plp + endm + +set_absx macro ;precharging abs,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed memory + sta abst,x + plp + endm + +;macros to test (register|memory|zeropage) & status & (mask) +tst_stat macro ;testing flags in the processor status register + php ;save status + php ;use stack to retrieve status + pla + cmp_flag \1 + trap_ne + plp ;restore status + endm + +tst_a macro ;testing result in accu & flags + php ;save flags + php + cmp #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_x macro ;testing result in x index & flags + php ;save flags + php + cpx #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_y macro ;testing result in y index & flags + php ;save flags + php + cpy #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_ax macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne ; + endm + +tst_ay macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,y ;test result + trap_ne ; + pla ;load status + eor_flag \3 + cmp \2,y ;test flags + trap_ne + endm + +tst_z macro ;indexed testing result in zp & flags + php ;save flags + lda zpt + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_zx macro ;testing result in zp,x & flags + php ;save flags + lda zpt,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_abs macro ;indexed testing result in memory & flags + php ;save flags + lda abst + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_absx macro ;testing result in abs,x & flags + php ;save flags + lda abst,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +; RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. +; uses zpt word as indirect pointer, zpt+2 word as checksum + if ram_top > -1 +check_ram macro + cld + lda #0 + sta zpt ;set low byte of indirect pointer + sta zpt+3 ;checksum high byte + sta range_adr ;reset self modifying code + sta tandi1 + sta tandi2 + sta teori1 + sta teori2 + sta torai1 + sta torai2 + sta chkdadi + sta chkdsbi + sta chkadi + sta chksbi + clc + ldx #zp_bss-zero_page ;zeropage - write test area +ccs3\? adc zero_page,x + bcc ccs2\? + inc zpt+3 ;carry to high byte + clc +ccs2\? inx + bne ccs3\? + ldx #hi(data_segment) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(data_bss) ;data after write test area +ccs5\? adc (zpt),y + bcc ccs4\? + inc zpt+3 ;carry to high byte + clc +ccs4\? iny + bne ccs5\? + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne ccs5\? + sta zpt+2 ;checksum low is + cmp ram_chksm ;checksum low expected + trap_ne ;checksum mismatch + lda zpt+3 ;checksum high is + cmp ram_chksm+1 ;checksum high expected + trap_ne ;checksum mismatch + endm + else +check_ram macro + ;RAM check disabled - RAM size not set + endm + endif + +next_test macro ;make sure, tests don't jump the fence + lda test_case ;previous test + cmp #test_num + trap_ne ;test is out of sequence +test_num = test_num + 1 + lda #test_num ;*** this tests' number + sta test_case + ;check_ram ;uncomment to find altered RAM after each test + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page +;break test interrupt save +irq_a ds 1 ;a register +irq_x ds 1 ;x register + if I_flag = 2 +;masking for I bit in status +flag_I_on ds 1 ;or mask to load flags +flag_I_off ds 1 ;and mask to load flags + endif +zpt ;5 bytes store/modify test area +;add/subtract operand generation and result/flag prediction +adfc ds 1 ;carry flag before op +ad1 ds 1 ;operand 1 - accumulator +ad2 ds 1 ;operand 2 - memory / immediate +adrl ds 1 ;expected result bits 0-7 +adrh ds 1 ;expected result bit 8 (carry) +adrf ds 1 ;expected flags NV0000ZC (-V in decimal mode) +sb2 ds 1 ;operand 2 complemented for subtract +zp_bss +zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f db $7f ;test pattern for compare +;logical zeropage operands +zpOR db 0,$1f,$71,$80 ;test pattern for OR +zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1 dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt dw abst-$f8 ;indirect pointer for wrap-test store +indAN dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2 dw ada2-$ff ;with offset for indirect indexed +sbiy2 dw sba2-$ff +zp_bss_end + + org data_segment +test_case ds 1 ;current test number +ram_chksm ds 2 ;checksum for RAM integrity test +;add/subtract operand copy - abs tests write area +abst ;5 bytes store/modify test area +ada2 ds 1 ;operand 2 +sba2 ds 1 ;operand 2 complemented for subtract + ds 3 ;fill remaining bytes +data_bss +abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f db $7f ;test pattern for compare +;loads +fLDx db fn,fn,0,fz ;expected flags for load +;shifts +rASL ;expected result ASL & ROL -carry +rROL db $86,$04,$82,0 ; " +rROLc db $87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $61,$41,$20,0 ; " +rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fnc,fc,fn,fz ;no carry in +fROLc db fnc,fc,fn,0 ;carry in +fLSR +fROR db fc,0,fc,fz ;no carry in +fRORc db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo db 0,$ff,$7f,$80 +absflo db fz,fn,0,fn +data_bss_end + + + code + org code_segment +start cld + lda #0 ;*** test 0 = initialize + sta test_case +test_num = 0 + +;stop interrupts before initializing BSS + if I_flag = 1 + sei + endif + +;initialize BSS segment + if load_data_direct != 1 + ldx #zp_end-zp_init-1 +ld_zp lda zp_init,x + sta zp_bss,x + dex + bpl ld_zp + ldx #data_end-data_init-1 +ld_data lda data_init,x + sta data_bss,x + dex + bpl ld_data + if ROM_vectors = 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + endif + +;retain status of interrupt flag + if I_flag = 2 + php + pla + and #4 ;isolate flag + sta flag_I_on ;or mask + eor #lo(~4) ;reverse + sta flag_I_off ;and mask + endif + +;generate checksum for RAM integrity test + if ram_top > -1 + lda #0 + sta zpt ;set low byte of indirect pointer + sta ram_chksm+1 ;checksum high byte + sta range_adr ;reset self modifying code + sta tandi1 + sta tandi2 + sta teori1 + sta teori2 + sta torai1 + sta torai2 + sta chkdadi + sta chkdsbi + sta chkadi + sta chksbi + clc + ldx #zp_bss-zero_page ;zeropage - write test area +gcs3 adc zero_page,x + bcc gcs2 + inc ram_chksm+1 ;carry to high byte + clc +gcs2 inx + bne gcs3 + ldx #hi(data_segment) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(data_bss) ;data after write test area +gcs5 adc (zpt),y + bcc gcs4 + inc ram_chksm+1 ;carry to high byte + clc +gcs4 iny + bne gcs5 + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne gcs5 + sta ram_chksm ;checksum complete + endif + next_test + +;testing relative addressing with BEQ + ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr) +range_loop + dey ;next relative address + tya + tax ;precharge count to end of loop + bpl range_fw ;calculate relative address + clc ;avoid branch self or to relative address of branch + adc #2 +range_fw + eor #$7f ;complement except sign + sta range_adr ;load into test target + lda #0 ;should set zero flag in status register + jmp range_op + + ;relative address target field with branch under test in the middle + dex ;-128 - max backward + dex + dex + dex + dex + dex + dex + dex + dex ;-120 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-110 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-100 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-90 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-80 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-70 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-60 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-50 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-40 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-30 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-20 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;-10 + dex + dex + dex + dex + dex + dex + dex ;-3 +range_op ;test target with zero flag=0, z=1 if previous dex +range_adr = *+1 ;modifiable relative address + beq *+64 ;if called without modification + dex ;+0 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+10 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+20 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+30 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+40 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+50 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+60 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+70 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+80 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+90 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+100 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+110 + dex + dex + dex + dex + dex + dex + dex + dex + dex + dex ;+120 + dex + dex + dex + dex + dex + dex + beq range_ok ;+127 - max forward + trap ; bad range +range_ok + cpy #0 + beq range_end + jmp range_loop +range_end ;range test successful + next_test + +;partial test BNE & CMP, CPX, CPY immediate + cpy #1 ;testing BNE true + bne test_bne + trap +test_bne + lda #0 + cmp #0 ;test compare immediate + trap_ne + trap_cc + trap_mi + cmp #1 + trap_eq + trap_cs + trap_pl + tax + cpx #0 ;test compare x immediate + trap_ne + trap_cc + trap_mi + cpx #1 + trap_eq + trap_cs + trap_pl + tay + cpy #0 ;test compare y immediate + trap_ne + trap_cc + trap_mi + cpy #1 + trap_eq + trap_cs + trap_pl + next_test +;testing stack operations PHA PHP PLA PLP + + ldx #$ff ;initialize stack + txs + lda #$55 + pha + lda #$aa + pha + cmp $1fe ;on stack ? + trap_ne + tsx + txa ;overwrite accu + cmp #$fd ;sp decremented? + trap_ne + pla + cmp #$aa ;successful retreived from stack? + trap_ne + pla + cmp #$55 + trap_ne + cmp $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + next_test + +;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ + set_stat $ff ;all on + bpl nbr1 ;branches should not be taken + bvc nbr2 + bcc nbr3 + bne nbr4 + bmi br1 ;branches should be taken + trap +br1 bvs br2 + trap +br2 bcs br3 + trap +br3 beq br4 + trap +nbr1 + trap ;previous bpl taken +nbr2 + trap ;previous bvc taken +nbr3 + trap ;previous bcc taken +nbr4 + trap ;previous bne taken +br4 php + tsx + cpx #$fe ;sp after php? + trap_ne + pla + cmp_flag $ff ;returned all flags on? + trap_ne + tsx + cpx #$ff ;sp after php? + trap_ne + set_stat 0 ;all off + bmi nbr11 ;branches should not be taken + bvs nbr12 + bcs nbr13 + beq nbr14 + trap_mi + trap_vs + trap_cs + trap_eq + bpl br11 ;branches should be taken + trap +br11 bvc br12 + trap +br12 bcc br13 + trap +br13 bne br14 + trap +nbr11 + trap ;previous bmi taken +nbr12 + trap ;previous bvs taken +nbr13 + trap ;previous bcs taken +nbr14 + trap ;previous beq taken +br14 php + pla + cmp_flag 0 ;flags off except break (pushed by sw) + reserved? + trap_ne + ;crosscheck flags + set_stat carry + trap_cc + set_stat zero + trap_ne + set_stat overfl + trap_vc + set_stat minus + trap_pl + set_stat $ff-carry + trap_cs + set_stat $ff-zero + trap_eq + set_stat $ff-overfl + trap_vs + set_stat $ff-minus + trap_mi + next_test + +; test PHA does not alter flags or accumulator but PLA does + ldx #$55 ;x & y protected + ldy #$aa + set_a 1,$ff ;push + pha + tst_a 1,$ff + set_a 0,0 + pha + tst_a 0,0 + set_a $ff,$ff + pha + tst_a $ff,$ff + set_a 1,0 + pha + tst_a 1,0 + set_a 0,$ff + pha + tst_a 0,$ff + set_a $ff,0 + pha + tst_a $ff,0 + set_a 0,$ff ;pull + pla + tst_a $ff,$ff-zero + set_a $ff,0 + pla + tst_a 0,zero + set_a $fe,$ff + pla + tst_a 1,$ff-zero-minus + set_a 0,0 + pla + tst_a $ff,minus + set_a $ff,$ff + pla + tst_a 0,$ff-minus + set_a $fe,0 + pla + tst_a 1,0 + cpx #$55 ;x & y unchanged? + trap_ne + cpy #$aa + trap_ne + next_test + +; partial pretest EOR # + set_a $3c,0 + eor #$c3 + tst_a $ff,fn + set_a $c3,0 + eor #$c3 + tst_a 0,fz + next_test + +; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI) +; testing NOP + ldx #$24 + ldy #$42 + set_a $18,0 + nop + tst_a $18,0 + cpx #$24 + trap_ne + cpy #$42 + trap_ne + ldx #$db + ldy #$bd + set_a $e7,$ff + nop + tst_a $e7,$ff + cpx #$db + trap_ne + cpy #$bd + trap_ne + next_test + +; jump absolute + set_stat $0 + lda #'F' + ldx #'A' + ldy #'R' ;N=0, V=0, Z=0, C=0 + jmp test_far + nop + nop + trap_ne ;runover protection + inx + inx +far_ret + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('F'^$aa) ;returned registers OK? + trap_ne + cpx #('A'+1) + trap_ne + cpy #('R'-3) + trap_ne + dex + iny + iny + iny + eor #$aa ;N=0, V=1, Z=0, C=1 + jmp test_near + nop + nop + trap_ne ;runover protection + inx + inx +test_near + trap_eq ;passed flags OK? + trap_mi + trap_cc + trap_vc + cmp #'F' ;passed registers OK? + trap_ne + cpx #'A' + trap_ne + cpy #'R' + trap_ne + next_test + +; jump indirect + set_stat 0 + lda #'I' + ldx #'N' + ldy #'D' ;N=0, V=0, Z=0, C=0 + jmp (ptr_tst_ind) + nop + trap_ne ;runover protection + dey + dey +ind_ret + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('I'^$aa) ;returned registers OK? + trap_ne + cpx #('N'+1) + trap_ne + cpy #('D'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + next_test + +; jump subroutine & return from subroutine + set_stat 0 + lda #'J' + ldx #'S' + ldy #'R' ;N=0, V=0, Z=0, C=0 + jsr test_jsr +jsr_ret = *-1 ;last address of jsr = return address + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('J'^$aa) ;returned registers OK? + trap_ne + cpx #('S'+1) + trap_ne + cpy #('R'-6) + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + +; break & return from interrupt + if ROM_vectors = 1 + set_stat 0 + lda #'B' + ldx #'R' + ldy #'K' ;N=0, V=0, Z=0, C=0 + brk + else + lda #hi brk_ret ;emulated break + pha + lda #lo brk_ret + pha + lda #fao ;set break & unused on stack + pha + set_stat intdis + lda #'B' + ldx #'R' + ldy #'K' ;N=0, V=0, Z=0, C=0 + jmp irq_trap + endif + dey ;should not be executed +brk_ret ;address of break return + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + cmp #('B'^$aa) ;returned registers OK? + trap_ne + cpx #('R'+1) + trap_ne + cpy #('K'-6) + trap_ne + pla ;returned flags OK (unchanged)? + cmp_flag 0 + trap_ne + tsx ;sp? + cpx #$ff + trap_ne + next_test + +; test set and clear flags CLC CLI CLD CLV SEC SEI SED + set_stat $ff + clc + tst_stat $ff-carry + sec + tst_stat $ff + if I_flag = 3 + cli + tst_stat $ff-intdis + sei + tst_stat $ff + endif + cld + tst_stat $ff-decmode + sed + tst_stat $ff + clv + tst_stat $ff-overfl + set_stat 0 + tst_stat 0 + sec + tst_stat carry + clc + tst_stat 0 + if I_flag = 3 + sei + tst_stat intdis + cli + tst_stat 0 + endif + sed + tst_stat decmode + cld + tst_stat 0 + set_stat overfl + tst_stat overfl + clv + tst_stat 0 + next_test +; testing index register increment/decrement and transfer +; INX INY DEX DEY TAX TXA TAY TYA + ldx #$fe + set_stat $ff + inx ;ff + tst_x $ff,$ff-zero + inx ;00 + tst_x 0,$ff-minus + inx ;01 + tst_x 1,$ff-minus-zero + dex ;00 + tst_x 0,$ff-minus + dex ;ff + tst_x $ff,$ff-zero + dex ;fe + set_stat 0 + inx ;ff + tst_x $ff,minus + inx ;00 + tst_x 0,zero + inx ;01 + tst_x 1,0 + dex ;00 + tst_x 0,zero + dex ;ff + tst_x $ff,minus + + ldy #$fe + set_stat $ff + iny ;ff + tst_y $ff,$ff-zero + iny ;00 + tst_y 0,$ff-minus + iny ;01 + tst_y 1,$ff-minus-zero + dey ;00 + tst_y 0,$ff-minus + dey ;ff + tst_y $ff,$ff-zero + dey ;fe + set_stat 0 + iny ;ff + tst_y $ff,0+minus + iny ;00 + tst_y 0,zero + iny ;01 + tst_y 1,0 + dey ;00 + tst_y 0,zero + dey ;ff + tst_y $ff,minus + + ldx #$ff + set_stat $ff + txa + tst_a $ff,$ff-zero + php + inx ;00 + plp + txa + tst_a 0,$ff-minus + php + inx ;01 + plp + txa + tst_a 1,$ff-minus-zero + set_stat 0 + txa + tst_a 1,0 + php + dex ;00 + plp + txa + tst_a 0,zero + php + dex ;ff + plp + txa + tst_a $ff,minus + + ldy #$ff + set_stat $ff + tya + tst_a $ff,$ff-zero + php + iny ;00 + plp + tya + tst_a 0,$ff-minus + php + iny ;01 + plp + tya + tst_a 1,$ff-minus-zero + set_stat 0 + tya + tst_a 1,0 + php + dey ;00 + plp + tya + tst_a 0,zero + php + dey ;ff + plp + tya + tst_a $ff,minus + + load_flag $ff + pha + ldx #$ff ;ff + txa + plp + tay + tst_y $ff,$ff-zero + php + inx ;00 + txa + plp + tay + tst_y 0,$ff-minus + php + inx ;01 + txa + plp + tay + tst_y 1,$ff-minus-zero + load_flag 0 + pha + lda #0 + txa + plp + tay + tst_y 1,0 + php + dex ;00 + txa + plp + tay + tst_y 0,zero + php + dex ;ff + txa + plp + tay + tst_y $ff,minus + + + load_flag $ff + pha + ldy #$ff ;ff + tya + plp + tax + tst_x $ff,$ff-zero + php + iny ;00 + tya + plp + tax + tst_x 0,$ff-minus + php + iny ;01 + tya + plp + tax + tst_x 1,$ff-minus-zero + load_flag 0 + pha + lda #0 ;preset status + tya + plp + tax + tst_x 1,0 + php + dey ;00 + tya + plp + tax + tst_x 0,zero + php + dey ;ff + tya + plp + tax + tst_x $ff,minus + next_test + +;TSX sets NZ - TXS does not + ldx #1 ;01 + set_stat $ff + txs + php + lda $101 + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $101 + cmp_flag 0 + trap_ne + dex ;00 + set_stat $ff + txs + php + lda $100 + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $100 + cmp_flag 0 + trap_ne + dex ;ff + set_stat $ff + txs + php + lda $1ff + cmp_flag $ff + trap_ne + set_stat 0 + txs + php + lda $1ff + cmp_flag 0 + + ldx #1 + txs ;sp=01 + set_stat $ff + tsx ;clears Z, N + php ;sp=00 + cpx #1 + trap_ne + lda $101 + cmp_flag $ff-minus-zero + trap_ne + set_stat $ff + tsx ;clears N, sets Z + php ;sp=ff + cpx #0 + trap_ne + lda $100 + cmp_flag $ff-minus + trap_ne + set_stat $ff + tsx ;clears N, sets Z + php ;sp=fe + cpx #$ff + trap_ne + lda $1ff + cmp_flag $ff-zero + trap_ne + + ldx #1 + txs ;sp=01 + set_stat 0 + tsx ;clears Z, N + php ;sp=00 + cpx #1 + trap_ne + lda $101 + cmp_flag 0 + trap_ne + set_stat 0 + tsx ;clears N, sets Z + php ;sp=ff + cpx #0 + trap_ne + lda $100 + cmp_flag zero + trap_ne + set_stat 0 + tsx ;clears N, sets Z + php ;sp=fe + cpx #$ff + trap_ne + lda $1ff + cmp_flag minus + trap_ne + pla ;sp=ff + next_test + +; testing index register load & store LDY LDX STY STX all addressing modes +; LDX / STX - zp,y / abs,y + ldy #3 +tldx + set_stat 0 + ldx zp1,y + php ;test stores do not alter flags + txa + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx + + ldy #3 +tldx1 + set_stat $ff + ldx zp1,y + php ;test stores do not alter flags + txa + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx1 + + ldy #3 +tldx2 + set_stat 0 + ldx abs1,y + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt,y + php ;flags after load/store sequence + eor #$c3 + cmp zp1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx2 + + ldy #3 +tldx3 + set_stat $ff + ldx abs1,y + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt,y + php ;flags after load/store sequence + eor #$c3 + cmp zp1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tldx3 + + ldy #3 ;testing store result + ldx #0 +tstx lda zpt,y + eor #$c3 + cmp zp1,y + trap_ne ;store to zp data + stx zpt,y ;clear + lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstx + next_test + +; indexed wraparound test (only zp should wrap) + ldy #3+$fa +tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp + txa + sta abst-$fa,y ;no STX abs,y! + dey + cpy #$fa + bcs tldx4 + ldy #3+$fa +tldx5 ldx abs1-$fa,y ;no wrap on indexed abs + stx zpt-$fa&$ff,y + dey + cpy #$fa + bcs tldx5 + ldy #3 ;testing wraparound result + ldx #0 +tstx1 lda zpt,y + cmp zp1,y + trap_ne ;store to zp data + stx zpt,y ;clear + lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstx1 + next_test + +; LDY / STY - zp,x / abs,x + ldx #3 +tldy + set_stat 0 + ldy zp1,x + php ;test stores do not alter flags + tya + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy + + ldx #3 +tldy1 + set_stat $ff + ldy zp1,x + php ;test stores do not alter flags + tya + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy1 + + ldx #3 +tldy2 + set_stat 0 + ldy abs1,x + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy2 + + ldx #3 +tldy3 + set_stat $ff + ldy abs1,x + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldy3 + + ldx #3 ;testing store result + ldy #0 +tsty lda zpt,x + eor #$c3 + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + eor #$c3 + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tsty + next_test + +; indexed wraparound test (only zp should wrap) + ldx #3+$fa +tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp + tya + sta abst-$fa,x ;no STX abs,x! + dex + cpx #$fa + bcs tldy4 + ldx #3+$fa +tldy5 ldy abs1-$fa,x ;no wrap on indexed abs + sty zpt-$fa&$ff,x + dex + cpx #$fa + bcs tldy5 + ldx #3 ;testing wraparound result + ldy #0 +tsty1 lda zpt,x + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tsty1 + next_test + +; LDX / STX - zp / abs / # + set_stat 0 + ldx zp1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx zp1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx zp1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx zp1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx zp1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$c3 ;test result + trap_ne ; + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx zp1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx zp1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #$41 ;test result + trap_ne ; + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx zp1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx abst+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldx abs1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx abs1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx abs1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx abs1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx abs1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx abs1+1 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+1 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx abs1+2 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+2 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx abs1+3 + php ;test stores do not alter flags + txa + eor #$c3 + tax + plp + stx zpt+3 + php ;flags after load/store sequence + eor #$c3 + tax + cpx zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldx #$c3 + php + cpx abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldx #$82 + php + cpx abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldx #$41 + php + cpx abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldx #0 + php + cpx abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldx #$c3 + php + cpx abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldx #$82 + php + cpx abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldx #$41 + php + cpx abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldx #0 + php + cpx abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldx #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + stx zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + stx abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp data + stx zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs data + stx abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp data + stx zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs data + stx abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp data + stx zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs data + stx abst+3 ;clear + next_test + +; LDY / STY - zp / abs / # + set_stat 0 + ldy zp1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy zp1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy zp1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy zp1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy zp1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy zp1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy zp1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy zp1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty abst+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + set_stat 0 + ldy abs1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy abs1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+1 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy abs1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+2 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy abs1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+3 + php ;flags after load/store sequence + eor #$c3 + tay + cpy zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy abs1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy abs1+1 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+1 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy abs1+2 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+2 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy abs1+3 + php ;test stores do not alter flags + tya + eor #$c3 + tay + plp + sty zpt+3 + php ;flags after load/store sequence + eor #$c3 + tay + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + + set_stat 0 + ldy #$c3 + php + cpy abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + ldy #$82 + php + cpy abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + ldy #$41 + php + cpy abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + ldy #0 + php + cpy abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + ldy #$c3 + php + cpy abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + ldy #$82 + php + cpy abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + ldy #$41 + php + cpy abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + ldy #0 + php + cpy abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldy #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + sty zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + sty abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp+1 data + sty zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs+1 data + sty abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp+2 data + sty zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs+2 data + sty abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp+3 data + sty zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs+3 data + sty abst+3 ;clear + next_test + +; testing load / store accumulator LDA / STA all addressing modes +; LDA / STA - zp,x / abs,x + ldx #3 +tldax + set_stat 0 + lda zp1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax + + ldx #3 +tldax1 + set_stat $ff + lda zp1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,x + php ;flags after load/store sequence + eor #$c3 + cmp abs1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax1 + + ldx #3 +tldax2 + set_stat 0 + lda abs1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax2 + + ldx #3 +tldax3 + set_stat $ff + lda abs1,x + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt,x + php ;flags after load/store sequence + eor #$c3 + cmp zp1,x ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,x ;test flags + trap_ne + dex + bpl tldax3 + + ldx #3 ;testing store result + ldy #0 +tstax lda zpt,x + eor #$c3 + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + eor #$c3 + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tstax + next_test + +; LDA / STA - (zp),y / abs,y / (zp,x) + ldy #3 +tlday + set_stat 0 + lda (ind1),y + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday + + ldy #3 +tlday1 + set_stat $ff + lda (ind1),y + php ;test stores do not alter flags + eor #$c3 + plp + sta abst,y + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday1 + + ldy #3 ;testing store result + ldx #0 +tstay lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay + + ldy #3 +tlday2 + set_stat 0 + lda abs1,y + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt),y + php ;flags after load/store sequence + eor #$c3 + cmp (ind1),y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday2 + + ldy #3 +tlday3 + set_stat $ff + lda abs1,y + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt),y + php ;flags after load/store sequence + eor #$c3 + cmp (ind1),y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dey + bpl tlday3 + + ldy #3 ;testing store result + ldx #0 +tstay1 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay1 + + ldx #6 + ldy #3 +tldax4 + set_stat 0 + lda (ind1,x) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt,x) + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx,y ;test flags + trap_ne + dex + dex + dey + bpl tldax4 + + ldx #6 + ldy #3 +tldax5 + set_stat $ff + lda (ind1,x) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt,x) + php ;flags after load/store sequence + eor #$c3 + cmp abs1,y ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx,y ;test flags + trap_ne + dex + dex + dey + bpl tldax5 + + ldy #3 ;testing store result + ldx #0 +tstay2 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay2 + next_test + +; indexed wraparound test (only zp should wrap) + ldx #3+$fa +tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp + sta abst-$fa,x ;no STX abs,x! + dex + cpx #$fa + bcs tldax6 + ldx #3+$fa +tldax7 lda abs1-$fa,x ;no wrap on indexed abs + sta zpt-$fa&$ff,x + dex + cpx #$fa + bcs tldax7 + + ldx #3 ;testing wraparound result + ldy #0 +tstax1 lda zpt,x + cmp zp1,x + trap_ne ;store to zp,x data + sty zpt,x ;clear + lda abst,x + cmp abs1,x + trap_ne ;store to abs,x data + txa + sta abst,x ;clear + dex + bpl tstax1 + + ldy #3+$f8 + ldx #6+$f8 +tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect + sta abst-$f8,y + dex + dex + dey + cpy #$f8 + bcs tlday4 + ldy #3 ;testing wraparound result + ldx #0 +tstay4 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay4 + + ldy #3+$f8 +tlday5 lda abs1-$f8,y ;no wrap on indexed abs + sta (inwt),y + dey + cpy #$f8 + bcs tlday5 + ldy #3 ;testing wraparound result + ldx #0 +tstay5 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay5 + + ldy #3+$f8 + ldx #6+$f8 +tlday6 lda (inw1),y ;no wrap on zp indirect indexed + sta (indt-$f8&$ff,x) + dex + dex + dey + cpy #$f8 + bcs tlday6 + ldy #3 ;testing wraparound result + ldx #0 +tstay6 lda abst,y + cmp abs1,y + trap_ne ;store to abs data + txa + sta abst,y ;clear + dey + bpl tstay6 + next_test + +; LDA / STA - zp / abs / # + set_stat 0 + lda zp1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda zp1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+1 + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda zp1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+2 + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda zp1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+3 + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + set_stat $ff + lda zp1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda zp1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+1 + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda zp1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+2 + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda zp1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta abst+3 + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + set_stat 0 + lda abs1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda abs1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda abs1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda abs1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + set_stat $ff + lda abs1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt + php ;flags after load/store sequence + eor #$c3 + cmp zp1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda abs1+1 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+1 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda abs1+2 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+2 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda abs1+3 + php ;test stores do not alter flags + eor #$c3 + plp + sta zpt+3 + php ;flags after load/store sequence + eor #$c3 + cmp zp1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + set_stat 0 + lda #$c3 + php + cmp abs1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda #$82 + php + cmp abs1+1 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda #$41 + php + cmp abs1+2 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda #0 + php + cmp abs1+3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + + set_stat $ff + lda #$c3 + php + cmp abs1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda #$82 + php + cmp abs1+1 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda #$41 + php + cmp abs1+2 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda #0 + php + cmp abs1+3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + + ldx #0 + lda zpt + eor #$c3 + cmp zp1 + trap_ne ;store to zp data + stx zpt ;clear + lda abst + eor #$c3 + cmp abs1 + trap_ne ;store to abs data + stx abst ;clear + lda zpt+1 + eor #$c3 + cmp zp1+1 + trap_ne ;store to zp data + stx zpt+1 ;clear + lda abst+1 + eor #$c3 + cmp abs1+1 + trap_ne ;store to abs data + stx abst+1 ;clear + lda zpt+2 + eor #$c3 + cmp zp1+2 + trap_ne ;store to zp data + stx zpt+2 ;clear + lda abst+2 + eor #$c3 + cmp abs1+2 + trap_ne ;store to abs data + stx abst+2 ;clear + lda zpt+3 + eor #$c3 + cmp zp1+3 + trap_ne ;store to zp data + stx zpt+3 ;clear + lda abst+3 + eor #$c3 + cmp abs1+3 + trap_ne ;store to abs data + stx abst+3 ;clear + next_test + +; testing bit test & compares BIT CPX CPY CMP all addressing modes +; BIT - zp / abs + set_a $ff,0 + bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,fz + set_a 1,0 + bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv + set_a 1,0 + bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + set_a 1,0 + bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a $ff,$ff + bit zp1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv + set_a 1,$ff + bit zp1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + set_a 1,$ff + bit zp1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + set_a 1,$ff + bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + + set_a $ff,0 + bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,fz + set_a 1,0 + bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,fv + set_a 1,0 + bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + set_a 1,0 + bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a $ff,$ff + bit abs1+3 ;00 - should set Z / clear NV + tst_a $ff,~fnv + set_a 1,$ff + bit abs1+2 ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + set_a 1,$ff + bit abs1+1 ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + set_a 1,$ff + bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + next_test + +; CPX - zp / abs / # + set_x $80,0 + cpx zp7f + tst_stat fc + dex + cpx zp7f + tst_stat fzc + dex + cpx zp7f + tst_x $7e,fn + set_x $80,$ff + cpx zp7f + tst_stat ~fnz + dex + cpx zp7f + tst_stat ~fn + dex + cpx zp7f + tst_x $7e,~fzc + + set_x $80,0 + cpx abs7f + tst_stat fc + dex + cpx abs7f + tst_stat fzc + dex + cpx abs7f + tst_x $7e,fn + set_x $80,$ff + cpx abs7f + tst_stat ~fnz + dex + cpx abs7f + tst_stat ~fn + dex + cpx abs7f + tst_x $7e,~fzc + + set_x $80,0 + cpx #$7f + tst_stat fc + dex + cpx #$7f + tst_stat fzc + dex + cpx #$7f + tst_x $7e,fn + set_x $80,$ff + cpx #$7f + tst_stat ~fnz + dex + cpx #$7f + tst_stat ~fn + dex + cpx #$7f + tst_x $7e,~fzc + next_test + +; CPY - zp / abs / # + set_y $80,0 + cpy zp7f + tst_stat fc + dey + cpy zp7f + tst_stat fzc + dey + cpy zp7f + tst_y $7e,fn + set_y $80,$ff + cpy zp7f + tst_stat ~fnz + dey + cpy zp7f + tst_stat ~fn + dey + cpy zp7f + tst_y $7e,~fzc + + set_y $80,0 + cpy abs7f + tst_stat fc + dey + cpy abs7f + tst_stat fzc + dey + cpy abs7f + tst_y $7e,fn + set_y $80,$ff + cpy abs7f + tst_stat ~fnz + dey + cpy abs7f + tst_stat ~fn + dey + cpy abs7f + tst_y $7e,~fzc + + set_y $80,0 + cpy #$7f + tst_stat fc + dey + cpy #$7f + tst_stat fzc + dey + cpy #$7f + tst_y $7e,fn + set_y $80,$ff + cpy #$7f + tst_stat ~fnz + dey + cpy #$7f + tst_stat ~fn + dey + cpy #$7f + tst_y $7e,~fzc + next_test + +; CMP - zp / abs / # + set_a $80,0 + cmp zp7f + tst_a $80,fc + set_a $7f,0 + cmp zp7f + tst_a $7f,fzc + set_a $7e,0 + cmp zp7f + tst_a $7e,fn + set_a $80,$ff + cmp zp7f + tst_a $80,~fnz + set_a $7f,$ff + cmp zp7f + tst_a $7f,~fn + set_a $7e,$ff + cmp zp7f + tst_a $7e,~fzc + + set_a $80,0 + cmp abs7f + tst_a $80,fc + set_a $7f,0 + cmp abs7f + tst_a $7f,fzc + set_a $7e,0 + cmp abs7f + tst_a $7e,fn + set_a $80,$ff + cmp abs7f + tst_a $80,~fnz + set_a $7f,$ff + cmp abs7f + tst_a $7f,~fn + set_a $7e,$ff + cmp abs7f + tst_a $7e,~fzc + + set_a $80,0 + cmp #$7f + tst_a $80,fc + set_a $7f,0 + cmp #$7f + tst_a $7f,fzc + set_a $7e,0 + cmp #$7f + tst_a $7e,fn + set_a $80,$ff + cmp #$7f + tst_a $80,~fnz + set_a $7f,$ff + cmp #$7f + tst_a $7f,~fn + set_a $7e,$ff + cmp #$7f + tst_a $7e,~fzc + + ldx #4 ;with indexing by X + set_a $80,0 + cmp zp1,x + tst_a $80,fc + set_a $7f,0 + cmp zp1,x + tst_a $7f,fzc + set_a $7e,0 + cmp zp1,x + tst_a $7e,fn + set_a $80,$ff + cmp zp1,x + tst_a $80,~fnz + set_a $7f,$ff + cmp zp1,x + tst_a $7f,~fn + set_a $7e,$ff + cmp zp1,x + tst_a $7e,~fzc + + set_a $80,0 + cmp abs1,x + tst_a $80,fc + set_a $7f,0 + cmp abs1,x + tst_a $7f,fzc + set_a $7e,0 + cmp abs1,x + tst_a $7e,fn + set_a $80,$ff + cmp abs1,x + tst_a $80,~fnz + set_a $7f,$ff + cmp abs1,x + tst_a $7f,~fn + set_a $7e,$ff + cmp abs1,x + tst_a $7e,~fzc + + ldy #4 ;with indexing by Y + ldx #8 ;with indexed indirect + set_a $80,0 + cmp abs1,y + tst_a $80,fc + set_a $7f,0 + cmp abs1,y + tst_a $7f,fzc + set_a $7e,0 + cmp abs1,y + tst_a $7e,fn + set_a $80,$ff + cmp abs1,y + tst_a $80,~fnz + set_a $7f,$ff + cmp abs1,y + tst_a $7f,~fn + set_a $7e,$ff + cmp abs1,y + tst_a $7e,~fzc + + set_a $80,0 + cmp (ind1,x) + tst_a $80,fc + set_a $7f,0 + cmp (ind1,x) + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1,x) + tst_a $7e,fn + set_a $80,$ff + cmp (ind1,x) + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1,x) + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1,x) + tst_a $7e,~fzc + + set_a $80,0 + cmp (ind1),y + tst_a $80,fc + set_a $7f,0 + cmp (ind1),y + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1),y + tst_a $7e,fn + set_a $80,$ff + cmp (ind1),y + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1),y + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1),y + tst_a $7e,~fzc + next_test + +; testing shifts - ASL LSR ROL ROR all addressing modes +; shifts - accumulator + ldx #3 +tasl + set_ax zp1,0 + asl a + tst_ax rASL,fASL,0 + dex + bpl tasl + ldx #3 +tasl1 + set_ax zp1,$ff + asl a + tst_ax rASL,fASL,$ff-fnzc + dex + bpl tasl1 + + ldx #3 +tlsr + set_ax zp1,0 + lsr a + tst_ax rLSR,fLSR,0 + dex + bpl tlsr + ldx #3 +tlsr1 + set_ax zp1,$ff + lsr a + tst_ax rLSR,fLSR,$ff-fnzc + dex + bpl tlsr1 + + ldx #3 +trol + set_ax zp1,0 + rol a + tst_ax rROL,fROL,0 + dex + bpl trol + ldx #3 +trol1 + set_ax zp1,$ff-fc + rol a + tst_ax rROL,fROL,$ff-fnzc + dex + bpl trol1 + + ldx #3 +trolc + set_ax zp1,fc + rol a + tst_ax rROLc,fROLc,0 + dex + bpl trolc + ldx #3 +trolc1 + set_ax zp1,$ff + rol a + tst_ax rROLc,fROLc,$ff-fnzc + dex + bpl trolc1 + + ldx #3 +tror + set_ax zp1,0 + ror a + tst_ax rROR,fROR,0 + dex + bpl tror + ldx #3 +tror1 + set_ax zp1,$ff-fc + ror a + tst_ax rROR,fROR,$ff-fnzc + dex + bpl tror1 + + ldx #3 +trorc + set_ax zp1,fc + ror a + tst_ax rRORc,fRORc,0 + dex + bpl trorc + ldx #3 +trorc1 + set_ax zp1,$ff + ror a + tst_ax rRORc,fRORc,$ff-fnzc + dex + bpl trorc1 + next_test + +; shifts - zeropage + ldx #3 +tasl2 + set_z zp1,0 + asl zpt + tst_z rASL,fASL,0 + dex + bpl tasl2 + ldx #3 +tasl3 + set_z zp1,$ff + asl zpt + tst_z rASL,fASL,$ff-fnzc + dex + bpl tasl3 + + ldx #3 +tlsr2 + set_z zp1,0 + lsr zpt + tst_z rLSR,fLSR,0 + dex + bpl tlsr2 + ldx #3 +tlsr3 + set_z zp1,$ff + lsr zpt + tst_z rLSR,fLSR,$ff-fnzc + dex + bpl tlsr3 + + ldx #3 +trol2 + set_z zp1,0 + rol zpt + tst_z rROL,fROL,0 + dex + bpl trol2 + ldx #3 +trol3 + set_z zp1,$ff-fc + rol zpt + tst_z rROL,fROL,$ff-fnzc + dex + bpl trol3 + + ldx #3 +trolc2 + set_z zp1,fc + rol zpt + tst_z rROLc,fROLc,0 + dex + bpl trolc2 + ldx #3 +trolc3 + set_z zp1,$ff + rol zpt + tst_z rROLc,fROLc,$ff-fnzc + dex + bpl trolc3 + + ldx #3 +tror2 + set_z zp1,0 + ror zpt + tst_z rROR,fROR,0 + dex + bpl tror2 + ldx #3 +tror3 + set_z zp1,$ff-fc + ror zpt + tst_z rROR,fROR,$ff-fnzc + dex + bpl tror3 + + ldx #3 +trorc2 + set_z zp1,fc + ror zpt + tst_z rRORc,fRORc,0 + dex + bpl trorc2 + ldx #3 +trorc3 + set_z zp1,$ff + ror zpt + tst_z rRORc,fRORc,$ff-fnzc + dex + bpl trorc3 + next_test + +; shifts - absolute + ldx #3 +tasl4 + set_abs zp1,0 + asl abst + tst_abs rASL,fASL,0 + dex + bpl tasl4 + ldx #3 +tasl5 + set_abs zp1,$ff + asl abst + tst_abs rASL,fASL,$ff-fnzc + dex + bpl tasl5 + + ldx #3 +tlsr4 + set_abs zp1,0 + lsr abst + tst_abs rLSR,fLSR,0 + dex + bpl tlsr4 + ldx #3 +tlsr5 + set_abs zp1,$ff + lsr abst + tst_abs rLSR,fLSR,$ff-fnzc + dex + bpl tlsr5 + + ldx #3 +trol4 + set_abs zp1,0 + rol abst + tst_abs rROL,fROL,0 + dex + bpl trol4 + ldx #3 +trol5 + set_abs zp1,$ff-fc + rol abst + tst_abs rROL,fROL,$ff-fnzc + dex + bpl trol5 + + ldx #3 +trolc4 + set_abs zp1,fc + rol abst + tst_abs rROLc,fROLc,0 + dex + bpl trolc4 + ldx #3 +trolc5 + set_abs zp1,$ff + rol abst + tst_abs rROLc,fROLc,$ff-fnzc + dex + bpl trolc5 + + ldx #3 +tror4 + set_abs zp1,0 + ror abst + tst_abs rROR,fROR,0 + dex + bpl tror4 + ldx #3 +tror5 + set_abs zp1,$ff-fc + ror abst + tst_abs rROR,fROR,$ff-fnzc + dex + bpl tror5 + + ldx #3 +trorc4 + set_abs zp1,fc + ror abst + tst_abs rRORc,fRORc,0 + dex + bpl trorc4 + ldx #3 +trorc5 + set_abs zp1,$ff + ror abst + tst_abs rRORc,fRORc,$ff-fnzc + dex + bpl trorc5 + next_test + +; shifts - zp indexed + ldx #3 +tasl6 + set_zx zp1,0 + asl zpt,x + tst_zx rASL,fASL,0 + dex + bpl tasl6 + ldx #3 +tasl7 + set_zx zp1,$ff + asl zpt,x + tst_zx rASL,fASL,$ff-fnzc + dex + bpl tasl7 + + ldx #3 +tlsr6 + set_zx zp1,0 + lsr zpt,x + tst_zx rLSR,fLSR,0 + dex + bpl tlsr6 + ldx #3 +tlsr7 + set_zx zp1,$ff + lsr zpt,x + tst_zx rLSR,fLSR,$ff-fnzc + dex + bpl tlsr7 + + ldx #3 +trol6 + set_zx zp1,0 + rol zpt,x + tst_zx rROL,fROL,0 + dex + bpl trol6 + ldx #3 +trol7 + set_zx zp1,$ff-fc + rol zpt,x + tst_zx rROL,fROL,$ff-fnzc + dex + bpl trol7 + + ldx #3 +trolc6 + set_zx zp1,fc + rol zpt,x + tst_zx rROLc,fROLc,0 + dex + bpl trolc6 + ldx #3 +trolc7 + set_zx zp1,$ff + rol zpt,x + tst_zx rROLc,fROLc,$ff-fnzc + dex + bpl trolc7 + + ldx #3 +tror6 + set_zx zp1,0 + ror zpt,x + tst_zx rROR,fROR,0 + dex + bpl tror6 + ldx #3 +tror7 + set_zx zp1,$ff-fc + ror zpt,x + tst_zx rROR,fROR,$ff-fnzc + dex + bpl tror7 + + ldx #3 +trorc6 + set_zx zp1,fc + ror zpt,x + tst_zx rRORc,fRORc,0 + dex + bpl trorc6 + ldx #3 +trorc7 + set_zx zp1,$ff + ror zpt,x + tst_zx rRORc,fRORc,$ff-fnzc + dex + bpl trorc7 + next_test + +; shifts - abs indexed + ldx #3 +tasl8 + set_absx zp1,0 + asl abst,x + tst_absx rASL,fASL,0 + dex + bpl tasl8 + ldx #3 +tasl9 + set_absx zp1,$ff + asl abst,x + tst_absx rASL,fASL,$ff-fnzc + dex + bpl tasl9 + + ldx #3 +tlsr8 + set_absx zp1,0 + lsr abst,x + tst_absx rLSR,fLSR,0 + dex + bpl tlsr8 + ldx #3 +tlsr9 + set_absx zp1,$ff + lsr abst,x + tst_absx rLSR,fLSR,$ff-fnzc + dex + bpl tlsr9 + + ldx #3 +trol8 + set_absx zp1,0 + rol abst,x + tst_absx rROL,fROL,0 + dex + bpl trol8 + ldx #3 +trol9 + set_absx zp1,$ff-fc + rol abst,x + tst_absx rROL,fROL,$ff-fnzc + dex + bpl trol9 + + ldx #3 +trolc8 + set_absx zp1,fc + rol abst,x + tst_absx rROLc,fROLc,0 + dex + bpl trolc8 + ldx #3 +trolc9 + set_absx zp1,$ff + rol abst,x + tst_absx rROLc,fROLc,$ff-fnzc + dex + bpl trolc9 + + ldx #3 +tror8 + set_absx zp1,0 + ror abst,x + tst_absx rROR,fROR,0 + dex + bpl tror8 + ldx #3 +tror9 + set_absx zp1,$ff-fc + ror abst,x + tst_absx rROR,fROR,$ff-fnzc + dex + bpl tror9 + + ldx #3 +trorc8 + set_absx zp1,fc + ror abst,x + tst_absx rRORc,fRORc,0 + dex + bpl trorc8 + ldx #3 +trorc9 + set_absx zp1,$ff + ror abst,x + tst_absx rRORc,fRORc,$ff-fnzc + dex + bpl trorc9 + next_test + +; testing memory increment/decrement - INC DEC all addressing modes +; zeropage + ldx #0 + lda #$7e + sta zpt +tinc + set_stat 0 + inc zpt + tst_z rINC,fINC,0 + inx + cpx #2 + bne tinc1 + lda #$fe + sta zpt +tinc1 cpx #5 + bne tinc + dex + inc zpt +tdec + set_stat 0 + dec zpt + tst_z rINC,fINC,0 + dex + bmi tdec1 + cpx #1 + bne tdec + lda #$81 + sta zpt + bne tdec +tdec1 + ldx #0 + lda #$7e + sta zpt +tinc10 + set_stat $ff + inc zpt + tst_z rINC,fINC,$ff-fnz + inx + cpx #2 + bne tinc11 + lda #$fe + sta zpt +tinc11 cpx #5 + bne tinc10 + dex + inc zpt +tdec10 + set_stat $ff + dec zpt + tst_z rINC,fINC,$ff-fnz + dex + bmi tdec11 + cpx #1 + bne tdec10 + lda #$81 + sta zpt + bne tdec10 +tdec11 + next_test + +; absolute memory + ldx #0 + lda #$7e + sta abst +tinc2 + set_stat 0 + inc abst + tst_abs rINC,fINC,0 + inx + cpx #2 + bne tinc3 + lda #$fe + sta abst +tinc3 cpx #5 + bne tinc2 + dex + inc abst +tdec2 + set_stat 0 + dec abst + tst_abs rINC,fINC,0 + dex + bmi tdec3 + cpx #1 + bne tdec2 + lda #$81 + sta abst + bne tdec2 +tdec3 + ldx #0 + lda #$7e + sta abst +tinc12 + set_stat $ff + inc abst + tst_abs rINC,fINC,$ff-fnz + inx + cpx #2 + bne tinc13 + lda #$fe + sta abst +tinc13 cpx #5 + bne tinc12 + dex + inc abst +tdec12 + set_stat $ff + dec abst + tst_abs rINC,fINC,$ff-fnz + dex + bmi tdec13 + cpx #1 + bne tdec12 + lda #$81 + sta abst + bne tdec12 +tdec13 + next_test + +; zeropage indexed + ldx #0 + lda #$7e +tinc4 sta zpt,x + set_stat 0 + inc zpt,x + tst_zx rINC,fINC,0 + lda zpt,x + inx + cpx #2 + bne tinc5 + lda #$fe +tinc5 cpx #5 + bne tinc4 + dex + lda #2 +tdec4 sta zpt,x + set_stat 0 + dec zpt,x + tst_zx rINC,fINC,0 + lda zpt,x + dex + bmi tdec5 + cpx #1 + bne tdec4 + lda #$81 + bne tdec4 +tdec5 + ldx #0 + lda #$7e +tinc14 sta zpt,x + set_stat $ff + inc zpt,x + tst_zx rINC,fINC,$ff-fnz + lda zpt,x + inx + cpx #2 + bne tinc15 + lda #$fe +tinc15 cpx #5 + bne tinc14 + dex + lda #2 +tdec14 sta zpt,x + set_stat $ff + dec zpt,x + tst_zx rINC,fINC,$ff-fnz + lda zpt,x + dex + bmi tdec15 + cpx #1 + bne tdec14 + lda #$81 + bne tdec14 +tdec15 + next_test + +; memory indexed + ldx #0 + lda #$7e +tinc6 sta abst,x + set_stat 0 + inc abst,x + tst_absx rINC,fINC,0 + lda abst,x + inx + cpx #2 + bne tinc7 + lda #$fe +tinc7 cpx #5 + bne tinc6 + dex + lda #2 +tdec6 sta abst,x + set_stat 0 + dec abst,x + tst_absx rINC,fINC,0 + lda abst,x + dex + bmi tdec7 + cpx #1 + bne tdec6 + lda #$81 + bne tdec6 +tdec7 + ldx #0 + lda #$7e +tinc16 sta abst,x + set_stat $ff + inc abst,x + tst_absx rINC,fINC,$ff-fnz + lda abst,x + inx + cpx #2 + bne tinc17 + lda #$fe +tinc17 cpx #5 + bne tinc16 + dex + lda #2 +tdec16 sta abst,x + set_stat $ff + dec abst,x + tst_absx rINC,fINC,$ff-fnz + lda abst,x + dex + bmi tdec17 + cpx #1 + bne tdec16 + lda #$81 + bne tdec16 +tdec17 + next_test + +; testing logical instructions - AND EOR ORA all addressing modes +; AND + ldx #3 ;immediate - self modifying code +tand lda zpAN,x + sta tandi1 + set_ax absANa,0 +tandi1 equ *+1 ;target for immediate operand + and #99 + tst_ax absrlo,absflo,0 + dex + bpl tand + ldx #3 +tand1 lda zpAN,x + sta tandi2 + set_ax absANa,$ff +tandi2 equ *+1 ;target for immediate operand + and #99 + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand1 + + ldx #3 ;zp +tand2 lda zpAN,x + sta zpt + set_ax absANa,0 + and zpt + tst_ax absrlo,absflo,0 + dex + bpl tand2 + ldx #3 +tand3 lda zpAN,x + sta zpt + set_ax absANa,$ff + and zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand3 + + ldx #3 ;abs +tand4 lda zpAN,x + sta abst + set_ax absANa,0 + and abst + tst_ax absrlo,absflo,0 + dex + bpl tand4 + ldx #3 +tand5 lda zpAN,x + sta abst + set_ax absANa,$ff + and abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand6 + + ldx #3 ;zp,x +tand6 + set_ax absANa,0 + and zpAN,x + tst_ax absrlo,absflo,0 + dex + bpl tand6 + ldx #3 +tand7 + set_ax absANa,$ff + and zpAN,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand7 + + ldx #3 ;abs,x +tand8 + set_ax absANa,0 + and absAN,x + tst_ax absrlo,absflo,0 + dex + bpl tand8 + ldx #3 +tand9 + set_ax absANa,$ff + and absAN,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tand9 + + ldy #3 ;abs,y +tand10 + set_ay absANa,0 + and absAN,y + tst_ay absrlo,absflo,0 + dey + bpl tand10 + ldy #3 +tand11 + set_ay absANa,$ff + and absAN,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tand11 + + ldx #6 ;(zp,x) + ldy #3 +tand12 + set_ay absANa,0 + and (indAN,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl tand12 + ldx #6 + ldy #3 +tand13 + set_ay absANa,$ff + and (indAN,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl tand13 + + ldy #3 ;(zp),y +tand14 + set_ay absANa,0 + and (indAN),y + tst_ay absrlo,absflo,0 + dey + bpl tand14 + ldy #3 +tand15 + set_ay absANa,$ff + and (indAN),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tand15 + next_test + +; EOR + ldx #3 ;immediate - self modifying code +teor lda zpEO,x + sta teori1 + set_ax absEOa,0 +teori1 equ *+1 ;target for immediate operand + eor #99 + tst_ax absrlo,absflo,0 + dex + bpl teor + ldx #3 +teor1 lda zpEO,x + sta teori2 + set_ax absEOa,$ff +teori2 equ *+1 ;target for immediate operand + eor #99 + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor1 + + ldx #3 ;zp +teor2 lda zpEO,x + sta zpt + set_ax absEOa,0 + eor zpt + tst_ax absrlo,absflo,0 + dex + bpl teor2 + ldx #3 +teor3 lda zpEO,x + sta zpt + set_ax absEOa,$ff + eor zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor3 + + ldx #3 ;abs +teor4 lda zpEO,x + sta abst + set_ax absEOa,0 + eor abst + tst_ax absrlo,absflo,0 + dex + bpl teor4 + ldx #3 +teor5 lda zpEO,x + sta abst + set_ax absEOa,$ff + eor abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor6 + + ldx #3 ;zp,x +teor6 + set_ax absEOa,0 + eor zpEO,x + tst_ax absrlo,absflo,0 + dex + bpl teor6 + ldx #3 +teor7 + set_ax absEOa,$ff + eor zpEO,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor7 + + ldx #3 ;abs,x +teor8 + set_ax absEOa,0 + eor absEO,x + tst_ax absrlo,absflo,0 + dex + bpl teor8 + ldx #3 +teor9 + set_ax absEOa,$ff + eor absEO,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl teor9 + + ldy #3 ;abs,y +teor10 + set_ay absEOa,0 + eor absEO,y + tst_ay absrlo,absflo,0 + dey + bpl teor10 + ldy #3 +teor11 + set_ay absEOa,$ff + eor absEO,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl teor11 + + ldx #6 ;(zp,x) + ldy #3 +teor12 + set_ay absEOa,0 + eor (indEO,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl teor12 + ldx #6 + ldy #3 +teor13 + set_ay absEOa,$ff + eor (indEO,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl teor13 + + ldy #3 ;(zp),y +teor14 + set_ay absEOa,0 + eor (indEO),y + tst_ay absrlo,absflo,0 + dey + bpl teor14 + ldy #3 +teor15 + set_ay absEOa,$ff + eor (indEO),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl teor15 + next_test + +; OR + ldx #3 ;immediate - self modifying code +tora lda zpOR,x + sta torai1 + set_ax absORa,0 +torai1 equ *+1 ;target for immediate operand + ora #99 + tst_ax absrlo,absflo,0 + dex + bpl tora + ldx #3 +tora1 lda zpOR,x + sta torai2 + set_ax absORa,$ff +torai2 equ *+1 ;target for immediate operand + ora #99 + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora1 + + ldx #3 ;zp +tora2 lda zpOR,x + sta zpt + set_ax absORa,0 + ora zpt + tst_ax absrlo,absflo,0 + dex + bpl tora2 + ldx #3 +tora3 lda zpOR,x + sta zpt + set_ax absORa,$ff + ora zpt + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora3 + + ldx #3 ;abs +tora4 lda zpOR,x + sta abst + set_ax absORa,0 + ora abst + tst_ax absrlo,absflo,0 + dex + bpl tora4 + ldx #3 +tora5 lda zpOR,x + sta abst + set_ax absORa,$ff + ora abst + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora6 + + ldx #3 ;zp,x +tora6 + set_ax absORa,0 + ora zpOR,x + tst_ax absrlo,absflo,0 + dex + bpl tora6 + ldx #3 +tora7 + set_ax absORa,$ff + ora zpOR,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora7 + + ldx #3 ;abs,x +tora8 + set_ax absORa,0 + ora absOR,x + tst_ax absrlo,absflo,0 + dex + bpl tora8 + ldx #3 +tora9 + set_ax absORa,$ff + ora absOR,x + tst_ax absrlo,absflo,$ff-fnz + dex + bpl tora9 + + ldy #3 ;abs,y +tora10 + set_ay absORa,0 + ora absOR,y + tst_ay absrlo,absflo,0 + dey + bpl tora10 + ldy #3 +tora11 + set_ay absORa,$ff + ora absOR,y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tora11 + + ldx #6 ;(zp,x) + ldy #3 +tora12 + set_ay absORa,0 + ora (indOR,x) + tst_ay absrlo,absflo,0 + dex + dex + dey + bpl tora12 + ldx #6 + ldy #3 +tora13 + set_ay absORa,$ff + ora (indOR,x) + tst_ay absrlo,absflo,$ff-fnz + dex + dex + dey + bpl tora13 + + ldy #3 ;(zp),y +tora14 + set_ay absORa,0 + ora (indOR),y + tst_ay absrlo,absflo,0 + dey + bpl tora14 + ldy #3 +tora15 + set_ay absORa,$ff + ora (indOR),y + tst_ay absrlo,absflo,$ff-fnz + dey + bpl tora15 + if I_flag = 3 + cli + endif + next_test + +; full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags + cld + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #0 ;start with adding zeroes & no carry + sta adfc ;carry in - for diag + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + sta adrh ;expected result bit 8 (carry out) + lda #$ff ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp + lda #2 ;expected Z-flag + sta adrf +tadd clc ;test with carry clear + jsr chkadd + inc adfc ;now with carry + inc adrl ;result +1 + php ;save N & Z from low result + php + pla ;accu holds expected flags + and #$82 ;mask N & Z + plp + bne tadd1 + inc adrh ;result bit 8 - carry +tadd1 ora adrh ;merge C to expected flags + sta adrf ;save expected flags except overflow + sec ;test with carry set + jsr chkadd + dec adfc ;same for operand +1 but no carry + inc ad1 + bne tadd ;iterate op1 + lda #0 ;preset result to op2 when op1 = 0 + sta adrh + inc ada2 + inc ad2 + php ;save NZ as operand 2 becomes the new result + pla + and #$82 ;mask N00000Z0 + sta adrf ;no need to check carry as we are adding to 0 + dec sb2 ;complement subtract operand 2 + dec sba2 + lda ad2 + sta adrl + bne tadd ;iterate op2 + next_test + +; decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, N V Z flags are ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag + sed + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #$99 ;start with adding 99 to 99 with carry + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + lda #1 ;set carry in & out + sta adfc ;carry in - for diag + sta adrh ;expected result bit 8 (carry out) + lda #0 ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp +tdad sec ;test with carry set + jsr chkdad + dec adfc ;now with carry clear + lda adrl ;decimal adjust result + bne tdad1 ;skip clear carry & preset result 99 (9A-1) + dec adrh + lda #$99 + sta adrl + bne tdad3 +tdad1 and #$f ;lower nibble mask + bne tdad2 ;no decimal adjust needed + dec adrl ;decimal adjust (?0-6) + dec adrl + dec adrl + dec adrl + dec adrl + dec adrl +tdad2 dec adrl ;result -1 +tdad3 clc ;test with carry clear + jsr chkdad + inc adfc ;same for operand -1 but with carry + lda ad1 ;decimal adjust operand 1 + beq tdad5 ;iterate operand 2 + and #$f ;lower nibble mask + bne tdad4 ;skip decimal adjust + dec ad1 ;decimal adjust (?0-6) + dec ad1 + dec ad1 + dec ad1 + dec ad1 + dec ad1 +tdad4 dec ad1 ;operand 1 -1 + jmp tdad ;iterate op1 + +tdad5 lda #$99 ;precharge op1 max + sta ad1 + lda ad2 ;decimal adjust operand 2 + beq tdad7 ;end of iteration + and #$f ;lower nibble mask + bne tdad6 ;skip decimal adjust + dec ad2 ;decimal adjust (?0-6) + dec ad2 + dec ad2 + dec ad2 + dec ad2 + dec ad2 + inc sb2 ;complemented decimal adjust for subtract (?9+6) + inc sb2 + inc sb2 + inc sb2 + inc sb2 + inc sb2 +tdad6 dec ad2 ;operand 2 -1 + inc sb2 ;complemented operand for subtract + lda sb2 + sta sba2 ;copy as non zp operand + lda ad2 + sta ada2 ;copy as non zp operand + sta adrl ;new result since op1+carry=00+carry +op2=op2 + inc adrh ;result carry + bne tdad ;iterate op2 +tdad7 cld + + lda test_case + cmp #test_num + trap_ne ;test is out of sequence + +; final RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. + check_ram +; *** DEBUG INFO *** +; to debug checksum errors uncomment check_ram in the next_test macro to +; narrow down the responsible opcode. +; may give false errors when monitor, OS or other background activity is +; allowed during previous tests. + + + +; S U C C E S S ************************************************ +; ------------- + success ;if you get here everything went well +; ------------- +; S U C C E S S ************************************************ + +; core subroutine of the decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, N V Z flags are ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag +chkdad +; decimal ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad flags + plp +; decimal ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC # + php ;save carry for subtract + lda ad2 + sta chkdadi ;self modify immediate + lda ad1 +chkdadi = * + 1 ;operand of the immediate ADC + adc #0 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda sb2 + sta chkdsbi ;self modify immediate + lda ad1 +chkdsbi = * + 1 ;operand of the immediate SBC + sbc #0 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp +; decimal ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #1 ;mask carry + cmp adrh + trap_ne ;bad carry + plp + rts + +; core subroutine of the full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags +chkadd lda adrf ;add V-flag if overflow + and #$83 ;keep N-----ZC / clear V + pha + lda ad1 ;test sign unequal between operands + eor ad2 + bmi ckad1 ;no overflow possible - operands have different sign + lda ad1 ;test sign equal between operands and result + eor adrl + bpl ckad1 ;no overflow occured - operand and result have same sign + pla + ora #$40 ;set V + pha +ckad1 pla + sta adrf ;save expected flags +; binary ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC # + php ;save carry for subtract + lda ad2 + sta chkadi ;self modify immediate + lda ad1 +chkadi = * + 1 ;operand of the immediate ADC + adc #0 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda sb2 + sta chksbi ;self modify immediate + lda ad1 +chksbi = * + 1 ;operand of the immediate SBC + sbc #0 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp +; binary ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; target for the jump absolute test + dey + dey +test_far + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'F' ;registers loaded? + trap_ne + cpx #'A' + trap_ne + cpy #('R'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp far_ret + +; target for the jump indirect test + align +ptr_tst_ind dw test_ind +ptr_ind_ret dw ind_ret + trap ;runover protection + dey + dey +test_ind + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'I' ;registers loaded? + trap_ne + cpx #'N' + trap_ne + cpy #('D'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (ptr_ind_ret) + trap ;runover protection + +; target for the jump subroutine test + dey + dey +test_jsr + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'J' ;registers loaded? + trap_ne + cpx #'S' + trap_ne + cpy #('R'-3) + trap_ne + pha ;save a,x + txa + pha + tsx ;sp -4? (return addr,a,x) + cpx #$fb + trap_ne + lda $1ff ;propper return on stack + cmp #hi(jsr_ret) + trap_ne + lda $1fe + cmp #lo(jsr_ret) + trap_ne + set_stat $ff + pla ;pull x,a + tax + pla + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + rts + trap ;runover protection + +;trap in case of unexpected IRQ, NMI, BRK, RESET - BRK test target +nmi_trap + trap ;check stack for conditions at NMI +res_trap + trap ;unexpected RESET + + dey + dey +irq_trap ;BRK test or unextpected BRK or IRQ + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + ;next 4 traps could be caused by unexpected BRK or IRQ + ;check stack for BREAK and originating location + ;possible jump/branch into weeds (uninitialized space) + cmp #'B' ;registers loaded? + trap_ne + cpx #'R' + trap_ne + cpy #('K'-3) + trap_ne + sta irq_a ;save registers during break test + stx irq_x + tsx ;test break on stack + lda $102,x + cmp_flag 0 ;break test should have B=1 + trap_ne ; - no break flag on stack + pla + cmp #$34 ;should have added interrupt disable + trap_ne + tsx + cpx #$fc ;sp -3? (return addr, flags) + trap_ne + lda $1ff ;propper return on stack + cmp #hi(brk_ret) + trap_ne + lda $1fe + cmp #lo(brk_ret) + trap_ne + set_stat $ff + ldx irq_x + inx ;return registers with modifications + lda irq_a + eor #$aa ;N=1, V=1, Z=0, C=1 but original flags should be restored + rti + trap ;runover protection + +;copy of data to initialize BSS segment + if load_data_direct != 1 +zp_init +zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f_ db $7f ;test pattern for compare +;logical zeropage operands +zpOR_ db 0,$1f,$71,$80 ;test pattern for OR +zpAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1_ dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1_ dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt_ dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt_ dw abst-$f8 ;indirect pointer for wrap-test store +indAN_ dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO_ dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR_ dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2_ dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2_ dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2_ dw ada2-$ff ;with offset for indirect indexed +sbiy2_ dw sba2-$ff +zp_end + if (zp_end - zp_init) != (zp_bss_end - zp_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and zeropage data + endif +data_init +abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f_ db $7f ;test pattern for compare +;loads +fLDx_ db fn,fn,0,fz ;expected flags for load +;shifts +rASL_ ;expected result ASL & ROL -carry +rROL_ db $86,$04,$82,0 ; " +rROLc_ db $87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $61,$41,$20,0 ; " +rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fnc,fc,fn,fz ;no carry in +fROLc_ db fnc,fc,fn,0 ;carry in +fLSR_ +fROR_ db fc,0,fc,fz ;no carry in +fRORc_ db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo_ db 0,$ff,$7f,$80 +absflo_ db fz,fn,0,fn +data_end + if (data_end - data_init) != (data_bss_end - data_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and data + endif + +vec_init + dw nmi_trap + dw res_trap + dw irq_trap +vec_bss equ $fffa + endif ;end of RAM init data + + if (load_data_direct = 1) & (ROM_vectors = 1) + org $fffa ;vectors + dw nmi_trap + dw res_trap + dw irq_trap + endif + + end start + \ No newline at end of file diff --git a/6502_interrupt_test.a65 b/6502_interrupt_test.a65 new file mode 100644 index 0000000..e116592 --- /dev/null +++ b/6502_interrupt_test.a65 @@ -0,0 +1,969 @@ +; +; 6 5 0 2 I N T E R R U P T T E S T +; +; Copyright (C) 2013 Klaus Dormann +; +; This program is free software: you can redistribute it and/or modify +; it under the terms of the GNU General Public License as published by +; the Free Software Foundation, either version 3 of the License, or +; (at your option) any later version. +; +; This program is distributed in the hope that it will be useful, +; but WITHOUT ANY WARRANTY; without even the implied warranty of +; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +; GNU General Public License for more details. +; +; You should have received a copy of the GNU General Public License +; along with this program. If not, see . + + +; This program is designed to test IRQ and NMI of a 6502 emulator. It requires +; an internal or external feedback register to the IRQ & NMI inputs +; +; version 19-jul-2013 +; contact info at http://2m5.de or email K@2m5.de +; +; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; command line switches: -l -m -s2 -w -h0 +; | | | | no page headers in listing +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex and +; enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceeding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 19-jul-2013 1st version distributed for testing + +; C O N F I G U R A T I O N +; +;ROM_vectors MUST be writable & the I_flag MUST be alterable + +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 + +;NMI & IRQ are tested with a feedback register +;emulators diag register - set i_drive = 0 for a latch (74HC573) +I_port = $bffc ;feedback port address +I_ddr = 0 ;feedback DDR address, 0 = no DDR +I_drive = 1 ;0 = totem pole, 1 = open collector +IRQ_bit = 0 ;bit number of feedback to IRQ +NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available + +;typical IO chip port B - set i_drive = 0 to avoid pullup resistors +;I_port = $bfb2 ;feedback port address +;I_ddr = $bfb3 ;feedback DDR address, 0 = no DDR +;I_drive = 1 ;0 = totem pole, 1 = open collector +;IRQ_bit = 0 ;bit number of feedback to IRQ +;NMI_bit = 1 ;bit number of feedback to NMI, -1 if not available + +;decimal mode flag during IRQ, NMI & BRK +D_clear = 1 ;0 = not cleared (NMOS), 1 = cleared (CMOS) + +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, 6 consecutive Bytes required +zero_page = $a + +;data_segment memory start address, 4 consecutive Bytes required +data_segment = $200 + +;code_segment memory start address +code_segment = $400 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +success macro + jmp * ;test passed, no errors + endm + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to set status +push_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + endm + +set_stat macro ;setting flags in the processor status register + lda #\1 + pha ;use stack to load status + plp + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page +;BRK, IRQ, NMI test interrupt save +irq_a ds 1 ;a register +irq_x ds 1 ;x register +irq_f ds 1 ;flags +nmi_a ds 1 ;a register +nmi_x ds 1 ;x register +nmi_f ds 1 ;flags + +;fixed stack locations +lst_f equ $1fe ;last flags before interrupt +lst_a equ $1ff ;last accumulator before interrupt + + org data_segment +data_bss +;concurrent NMI, IRQ & BRK test result +nmi_count ds 1 ;lowest number handled first, $ff = never +irq_count ds 1 ;separation-1 = instructions between interrupts +brk_count ds 1 +;expected interrupt mask +I_src ds 1 ;bit: 0=BRK, 1=IRQ, 2=NMI +data_bss_end + + code + org code_segment +start cld + lda #0 ;clear expected interrupts for 2nd run + sta I_src + ldx #$ff + txs + +; load system vectors + if load_data_direct != 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + +; IRQ & NMI test - requires a feedback register + if I_drive > 1 + ERROR ;invalid interrupt drive! + endif + if NMI_bit < 0 + if I_drive = 0 ;totem pole (push/pull, 0 -> I_port to force interrupt) +I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + and #$ff-(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_port ;interrupt next instruction plus outbound delay + endm +I_clr macro ibit ;ibit = interrupt bit + lda I_port ;turn off interrupt by bit + ora #(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR +I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + ora #(1<<\1) + plp ;set flags + pha ;save to verify + php + sta I_ddr ;interrupt next instruction plus outbound delay + endm +I_clr macro ibit ;ibit = interrupt bit + lda I_ddr ;turn off interrupt by bit + and #$ff-(1< I_port to force interrupt) +I_set macro ibit ;ibit = interrupt bit + lda I_port ;turn on interrupt by bit + if ibit > 7 ;set both NMI & IRQ + and #$ff-(1< I_DDR or I_port to force interrupt + if I_ddr != 0 ;with DDR +I_set macro ibit ;ibit = interrupt bit + lda I_ddr ;turn on interrupt by bit + if ibit > 7 ;set both NMI & IRQ + ora #(1< 7 ;set both NMI & IRQ + ora #(1<. + + +; This program is designed to test all additional 65C02 opcodes, addressing +; modes and functionality not available in the NMOS version of the 6502. +; The 6502_functional_test is a prerequisite to this test. +; NMI, IRQ, BRK, STP & WAI are covered in the 6502_interrupt_test. +; +; version 23-jul-2013 +; contact info at http://2m5.de or email K@2m5.de +; +; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ +; command line switches: -l -m -s2 -w -x -h0 +; | | | | | no page headers in listing +; | | | | 65C02 extensions +; | | | wide listing (133 char/col) +; | | write intel hex file instead of binary +; | expand macros in listing +; generate pass2 listing +; +; No IO - should be run from a monitor with access to registers. +; To run load intel hex image with a load command, than alter PC to 400 hex +; (code_segment) and enter a go command. +; Loop on program counter determines error or successful completion of test. +; Check listing for relevant traps (jump/branch *). +; Please note that in early tests some instructions will have to be used before +; they are actually tested! +; +; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled. +; Tests documented behavior of the original 65C02 only! +; Decimal ops will only be tested with valid BCD operands and the V flag will +; be ignored as it is absolutely useless in decimal mode. +; +; Debugging hints: +; Most of the code is written sequentially. if you hit a trap, check the +; immediately preceeding code for the instruction to be tested. Results are +; tested first, flags are checked second by pushing them onto the stack and +; pulling them to the accumulator after the result was checked. The "real" +; flags are no longer valid for the tested instruction at this time! +; If the tested instruction was indexed, the relevant index (X or Y) must +; also be checked. Opposed to the flags, X and Y registers are still valid. +; +; versions: +; 19-jul-2013 1st version distributed for testing +; 23-jul-2013 fixed BRA out of range due to larger trap macros +; added RAM integrity check + +; C O N F I G U R A T I O N +; +;ROM_vectors writable (0=no, 1=yes) +;if ROM vectors can not be used interrupts will not be trapped +;as a consequence BRK can not be tested but will be emulated to test RTI +ROM_vectors = 1 +;load_data_direct (0=move from code segment, 1=load directly) +;loading directly is preferred but may not be supported by your platform +;0 produces only consecutive object code, 1 is not suitable for a binary image +load_data_direct = 1 +;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow +;change) 2 requires extra code and is not recommended. +I_flag = 3 +;configure memory - try to stay away from memory used by the system +;zero_page memory start address, $4e (78) consecutive Bytes required +; add 2 if I_flag = 2 +zero_page = $a +;data_segment memory start address, $5D (93) consecutive Bytes required +; + 12 Bytes at data_segment + $f9 (JMP indirect page cross test) +data_segment = $200 + if (data_segment & $ff) != 0 + ERROR ERROR ERROR low byte of data_segment MUST be $00 !! + endif +;code_segment memory start address, 10kB of consecutive space required +; add 1 kB if I_flag = 2 +;parts of the code are self modifying and must reside in RAM +code_segment = $400 +;added WDC only opcodes WAI & STP (0=test as NOPs, >0=no test) +wdc_op = 1 +;added Rockwell & WDC opcodes BBR, BBS, RMB & SMB +;(0=test as NOPs, 1=full test, >1=no test) +rkwl_wdc_op = 1 +;RAM integrity test option. Checks for undesired RAM writes. +;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k) +;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM +ram_top = -1 + + noopt ;do not take shortcuts + +;macros for error & success traps to allow user modification +;example: +;trap macro +; jsr my_error_handler +; endm +;trap_eq macro +; bne skip\? +; trap ;failed equal (zero) +;skip\? +; endm +; +; my_error_handler should pop the calling address from the stack and report it. +; putting larger portions of code (more than 3 bytes) inside the trap macro +; may lead to branch range problems for some tests. +trap macro + jmp * ;failed anyway + endm +trap_eq macro + beq * ;failed equal (zero) + endm +trap_ne macro + bne * ;failed not equal (non zero) + endm +trap_cs macro + bcs * ;failed carry set + endm +trap_cc macro + bcc * ;failed carry clear + endm +trap_mi macro + bmi * ;failed minus (bit 7 set) + endm +trap_pl macro + bpl * ;failed plus (bit 7 clear) + endm +trap_vs macro + bvs * ;failed overflow set + endm +trap_vc macro + bvc * ;failed overflow clear + endm +success macro + jmp * ;test passed, no errors + endm + + +carry equ %00000001 ;flag bits in status +zero equ %00000010 +intdis equ %00000100 +decmode equ %00001000 +break equ %00010000 +reserv equ %00100000 +overfl equ %01000000 +minus equ %10000000 + +fc equ carry +fz equ zero +fzc equ carry+zero +fv equ overfl +fvz equ overfl+zero +fn equ minus +fnc equ minus+carry +fnz equ minus+zero +fnzc equ minus+zero+carry +fnv equ minus+overfl + +fao equ break+reserv ;bits always on after PHP, BRK +fai equ fao+intdis ;+ forced interrupt disable +m8 equ $ff ;8 bit mask +m8i equ $ff&~intdis ;8 bit mask - interrupt disable + +;macros to allow masking of status bits. +;masking of interrupt enable/disable on load and compare +;masking of always on bits after PHP or BRK (unused & break) on compare + if I_flag = 0 +load_flag macro + lda #\1&m8i ;force enable interrupts (mask I) + endm +cmp_flag macro + cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits + endm +eor_flag macro + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 1 +load_flag macro + lda #\1|intdis ;force disable interrupts + endm +cmp_flag macro + cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits + endm +eor_flag macro + eor #(\1|fai) ;invert expected flags + always on bits + I + endm + endif + if I_flag = 2 +load_flag macro + lda #\1 + ora flag_I_on ;restore I-flag + and flag_I_off + endm +cmp_flag macro + eor flag_I_on ;I_flag is never changed + cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I + endm +eor_flag macro + eor flag_I_on ;I_flag is never changed + eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits + endm + endif + if I_flag = 3 +load_flag macro + lda #\1 ;allow test to change I-flag (no mask) + endm +cmp_flag macro + cmp #(\1|fao)&m8 ;expected flags + always on bits + endm +eor_flag macro + eor #\1|fao ;invert expected flags + always on bits + endm + endif + +;macros to set (register|memory|zeropage) & status +set_stat macro ;setting flags in the processor status register + load_flag \1 + pha ;use stack to load status + plp + endm + +set_a macro ;precharging accu & status + load_flag \2 + pha ;use stack to load status + lda #\1 ;precharge accu + plp + endm + +set_x macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldx #\1 ;precharge index x + plp + endm + +set_y macro ;precharging index & status + load_flag \2 + pha ;use stack to load status + ldy #\1 ;precharge index y + plp + endm + +set_ax macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;precharge accu + plp + endm + +set_ay macro ;precharging indexed accu & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,y ;precharge accu + plp + endm + +set_z macro ;precharging indexed zp & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to zeropage + sta zpt + plp + endm + +set_zx macro ;precharging zp,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed zeropage + sta zpt,x + plp + endm + +set_abs macro ;precharging indexed memory & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to memory + sta abst + plp + endm + +set_absx macro ;precharging abs,x & immediate status + load_flag \2 + pha ;use stack to load status + lda \1,x ;load to indexed memory + sta abst,x + plp + endm + +;macros to test (register|memory|zeropage) & status & (mask) +tst_stat macro ;testing flags in the processor status register + php ;save status + php ;use stack to retrieve status + pla + cmp_flag \1 + trap_ne + plp ;restore status + endm + +tst_a macro ;testing result in accu & flags + php ;save flags + php + cmp #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_as macro ;testing result in accu & flags, save accu + pha + php ;save flags + php + cmp #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + pla + endm + +tst_x macro ;testing result in x index & flags + php ;save flags + php + cpx #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_y macro ;testing result in y index & flags + php ;save flags + php + cpy #\1 ;test result + trap_ne + pla ;load status + cmp_flag \2 + trap_ne + plp ;restore status + endm + +tst_ax macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne ; + endm + +tst_ay macro ;indexed testing result in accu & flags + php ;save flags + cmp \1,y ;test result + trap_ne ; + pla ;load status + eor_flag \3 + cmp \2,y ;test flags + trap_ne + endm + +tst_z macro ;indexed testing result in zp & flags + php ;save flags + lda zpt + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_zx macro ;testing result in zp,x & flags + php ;save flags + lda zpt,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_abs macro ;indexed testing result in memory & flags + php ;save flags + lda abst + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +tst_absx macro ;testing result in abs,x & flags + php ;save flags + lda abst,x + cmp \1,x ;test result + trap_ne + pla ;load status + eor_flag \3 + cmp \2,x ;test flags + trap_ne + endm + +; RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. +; uses zpt word as indirect pointer, zpt+2 word as checksum + if ram_top > -1 +check_ram macro + cld + lda #0 + sta zpt ;set low byte of indirect pointer + sta zpt+3 ;checksum high byte + ldx #11 ;reset modifiable RAM +ccs1\? sta jxi_tab,x ;JMP indirect page cross area + dex + bpl ccs1\? + sta chkdadi ;self modifying code + sta chkdsbi + clc + ldx #zp_bss-zero_page ;zeropage - write test area +ccs3\? adc zero_page,x + bcc ccs2\? + inc zpt+3 ;carry to high byte + clc +ccs2\? inx + bne ccs3\? + ldx #hi(data_segment) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(data_bss) ;data after write test area +ccs5\? adc (zpt),y + bcc ccs4\? + inc zpt+3 ;carry to high byte + clc +ccs4\? iny + bne ccs5\? + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne ccs5\? + sta zpt+2 ;checksum low is + cmp ram_chksm ;checksum low expected + trap_ne ;checksum mismatch + lda zpt+3 ;checksum high is + cmp ram_chksm+1 ;checksum high expected + trap_ne ;checksum mismatch + endm + else +check_ram macro + ;RAM check disabled - RAM size not set + endm + endif + +next_test macro ;make sure, tests don't jump the fence + lda test_case ;previous test + cmp #test_num + trap_ne ;test is out of sequence +test_num = test_num + 1 + lda #test_num ;*** this tests' number + sta test_case + ;check_ram ;uncomment to find altered RAM after each test + endm + + if load_data_direct = 1 + data + else + bss ;uninitialized segment, copy of data at end of code! + endif + org zero_page + if I_flag = 2 +;masking for I bit in status +flag_I_on ds 1 ;or mask to load flags +flag_I_off ds 1 ;and mask to load flags + endif +zpt ;5 bytes store/modify test area +;add/subtract operand generation and result/flag prediction +adfc ds 1 ;carry flag before op +ad1 ds 1 ;operand 1 - accumulator +ad2 ds 1 ;operand 2 - memory / immediate +adrl ds 1 ;expected result bits 0-7 +adrh ds 1 ;expected result bit 8 (carry) +adrf ds 1 ;expected flags NV0000ZC (-V in decimal mode) +sb2 ds 1 ;operand 2 complemented for subtract +zp_bss +zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f db $7f ;test pattern for compare +;logical zeropage operands +zpOR db 0,$1f,$71,$80 ;test pattern for OR +zpAN db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1 dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt dw abst-$f8 ;indirect pointer for wrap-test store +indAN dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2 dw ada2-$ff ;with offset for indirect indexed +sbiy2 dw sba2-$ff +zp_bss_end + + org data_segment +pg_x ds 2 ;high JMP indirect address for page cross bug +test_case ds 1 ;current test number +ram_chksm ds 2 ;checksum for RAM integrity test +;add/subtract operand copy - abs tests write area +abst ;5 bytes store/modify test area +ada2 ds 1 ;operand 2 +sba2 ds 1 ;operand 2 complemented for subtract + ds 3 ;fill remaining bytes +data_bss +abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f db $7f ;test pattern for compare +;loads +fLDx db fn,fn,0,fz ;expected flags for load +;shifts +rASL ;expected result ASL & ROL -carry +rROL db $86,$04,$82,0 ; " +rROLc db $87,$05,$83,1 ;expected result ROL +carry +rLSR ;expected result LSR & ROR -carry +rROR db $61,$41,$20,0 ; " +rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL ;expected flags for shifts +fROL db fnc,fc,fn,fz ;no carry in +fROLc db fnc,fc,fn,0 ;carry in +fLSR +fROR db fc,0,fc,fz ;no carry in +fRORc db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR db 0,$1f,$71,$80 ;test pattern for OR +absAN db $0f,$ff,$7f,$80 ;test pattern for AND +absEO db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa db 0,$f1,$1f,0 ;test pattern for OR +absANa db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo db 0,$ff,$7f,$80 +absflo db fz,fn,0,fn +data_bss_end +;define area for page crossing JMP (abs) & JMP (abs,x) test +jxi_tab equ data_segment + $100 - 7 ;JMP (jxi_tab,x) x=6 +ji_tab equ data_segment + $100 - 3 ;JMP (ji_tab+2) +jxp_tab equ data_segment + $100 ;JMP (jxp_tab-255) x=255 + + code + org code_segment +start cld + lda #0 ;*** test 0 = initialize + sta test_case +test_num = 0 + +;stop interrupts before initializing BSS + if I_flag = 1 + sei + endif + +;initialize BSS segment + if load_data_direct != 1 + ldx #zp_end-zp_init-1 +ld_zp lda zp_init,x + sta zp_bss,x + dex + bpl ld_zp + ldx #data_end-data_init-1 +ld_data lda data_init,x + sta data_bss,x + dex + bpl ld_data + if ROM_vectors = 1 + ldx #5 +ld_vect lda vec_init,x + sta vec_bss,x + dex + bpl ld_vect + endif + endif + +;retain status of interrupt flag + if I_flag = 2 + php + pla + and #4 ;isolate flag + sta flag_I_on ;or mask + eor #lo(~4) ;reverse + sta flag_I_off ;and mask + endif + +;generate checksum for RAM integrity test + if ram_top > -1 + lda #0 + sta zpt ;set low byte of indirect pointer + sta ram_chksm+1 ;checksum high byte + ldx #11 ;reset modifiable RAM +gcs1 sta jxi_tab,x ;JMP indirect page cross area + dex + bpl gcs1 + sta chkdadi ;self modifying code + sta chkdsbi + clc + ldx #zp_bss-zero_page ;zeropage - write test area +gcs3 adc zero_page,x + bcc gcs2 + inc ram_chksm+1 ;carry to high byte + clc +gcs2 inx + bne gcs3 + ldx #hi(data_segment) ;set high byte of indirect pointer + stx zpt+1 + ldy #lo(data_bss) ;data after write test area +gcs5 adc (zpt),y + bcc gcs4 + inc ram_chksm+1 ;carry to high byte + clc +gcs4 iny + bne gcs5 + inx ;advance RAM high address + stx zpt+1 + cpx #ram_top + bne gcs5 + sta ram_chksm ;checksum complete + endif + next_test + +;testing stack operations PHX PHY PLX PLY + lda #$99 ;protect a + ldx #$ff ;initialize stack + txs + ldx #$55 + phx + ldx #$aa + phx + cpx $1fe ;on stack ? + trap_ne + tsx + cpx #$fd ;sp decremented? + trap_ne + ply + cpy #$aa ;successful retreived from stack? + trap_ne + ply + cpy #$55 + trap_ne + cpy $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + + ldy #$a5 + phy + ldy #$5a + phy + cpy $1fe ;on stack ? + trap_ne + tsx + cpx #$fd ;sp decremented? + trap_ne + plx + cpx #$5a ;successful retreived from stack? + trap_ne + plx + cpx #$a5 + trap_ne + cpx $1ff ;remains on stack? + trap_ne + tsx + cpx #$ff ;sp incremented? + trap_ne + cmp #$99 ;unchanged? + trap_ne + next_test + +; test PHX does not alter flags or X but PLX does + ldy #$aa ;protect y + set_x 1,$ff ;push + phx + tst_x 1,$ff + set_x 0,0 + phx + tst_x 0,0 + set_x $ff,$ff + phx + tst_x $ff,$ff + set_x 1,0 + phx + tst_x 1,0 + set_x 0,$ff + phx + tst_x 0,$ff + set_x $ff,0 + phx + tst_x $ff,0 + set_x 0,$ff ;pull + plx + tst_x $ff,$ff-zero + set_x $ff,0 + plx + tst_x 0,zero + set_x $fe,$ff + plx + tst_x 1,$ff-zero-minus + set_x 0,0 + plx + tst_x $ff,minus + set_x $ff,$ff + plx + tst_x 0,$ff-minus + set_x $fe,0 + plx + tst_x 1,0 + cpy #$aa ;Y unchanged + trap_ne + next_test + +; test PHY does not alter flags or Y but PLY does + ldx #$55 ;x & a protected + set_y 1,$ff ;push + phy + tst_y 1,$ff + set_y 0,0 + phy + tst_y 0,0 + set_y $ff,$ff + phy + tst_y $ff,$ff + set_y 1,0 + phy + tst_y 1,0 + set_y 0,$ff + phy + tst_y 0,$ff + set_y $ff,0 + phy + tst_y $ff,0 + set_y 0,$ff ;pull + ply + tst_y $ff,$ff-zero + set_y $ff,0 + ply + tst_y 0,zero + set_y $fe,$ff + ply + tst_y 1,$ff-zero-minus + set_y 0,0 + ply + tst_y $ff,minus + set_y $ff,$ff + ply + tst_y 0,$ff-minus + set_y $fe,0 + ply + tst_y 1,0 + cpx #$55 ;x unchanged? + trap_ne + next_test + +; PC modifying instructions (BRA, BBR, BBS, 1, 2, 3 byte NOPs, JMP(abs,x)) +; testing unconditional branch BRA + + ldx #$81 ;protect unused registers + ldy #$7e + set_a 0,$ff + bra br1 ;branch should always be taken + trap +br1 + tst_a 0,$ff + set_a $ff,0 + bra br2 ;branch should always be taken + trap +br2 + tst_a $ff,0 + cpx #$81 + trap_ne + cpy #$7e + trap_ne + next_test + + ldy #0 ;branch range test + bra bra0 + +bra1 cpy #1 + trap_ne ;long range backward + iny + bra bra2 + +bra3 cpy #3 + trap_ne ;long range backward + iny + bra bra4 + +bra5 cpy #5 + trap_ne ;long range backward + iny + ldy #0 + bra brf0 + + iny + iny + iny + iny +brf0 bra brf1 + + iny + iny + iny +brf1 iny + bra brf2 + + iny + iny +brf2 iny + iny + bra brf3 + + iny +brf3 iny + iny + iny + bra brf4 + +brf4 iny + iny + iny + iny + cpy #10 + trap_ne ;short range forward + bra brb0 + +brb4 dey + dey + dey + dey + bra brb5 + +brb3 dey + dey + dey + bra brb4 + +brb2 dey + dey + bra brb3 + +brb1 dey + bra brb2 + +brb0 bra brb1 + +brb5 cpy #0 + trap_ne ;short range backward + bra bra6 + +bra4 cpy #4 + trap_ne ;long range forward + iny + bra bra5 + +bra2 cpy #2 + trap_ne ;long range forward + iny + bra bra3 + +bra0 cpy #0 + trap_ne ;long range forward + iny + bra bra1 + +bra6 + next_test + + if rkwl_wdc_op = 1 +; testing BBR & BBS + +bbt macro ;\1 = bitnum + lda #(1<<\1) ;testing 1 bit on + sta zpt + set_a $33,0 ;with flags off + bbr \1,zpt,fail1\? + bbs \1,zpt,ok1\? + trap ;bbs branch not taken +fail1\? + trap ;bbr branch taken +ok1\? + tst_a $33,0 + set_a $cc,$ff ;with flags on + bbr \1,zpt,fail2\? + bbs \1,zpt,ok2\? + trap ;bbs branch not taken +fail2\? + trap ;bbr branch taken +ok2\? + tst_a $cc,$ff + lda zpt + cmp #(1<<\1) + trap_ne ;zp altered + lda #$ff-(1<<\1) ;testing 1 bit off + sta zpt + set_a $33,0 ;with flags off + bbs \1,zpt,fail3\? + bbr \1,zpt,ok3\? + trap ;bbr branch not taken +fail3\? + trap ;bbs branch taken +ok3\? + tst_a $33,0 + set_a $cc,$ff ;with flags on + bbs \1,zpt,fail4\? + bbr \1,zpt,ok4\? + trap ;bbr branch not taken +fail4\? + trap ;bbs branch taken +ok4\? + tst_a $cc,$ff + lda zpt + cmp #$ff-(1<<\1) + trap_ne ;zp altered + endm + + ldx #$11 ;test bbr/bbs integrity + ldy #$22 + bbt 0 + bbt 1 + bbt 2 + bbt 3 + bbt 4 + bbt 5 + bbt 6 + bbt 7 + cpx #$11 + trap_ne ;x overwritten + cpy #$22 + trap_ne ;y overwritten + next_test + +bbrc macro ;\1 = bitnum + bbr \1,zpt,skip\? + eor #(1<<\1) +skip\? + endm +bbsc macro ;\1 = bitnum + bbs \1,zpt,skip\? + eor #(1<<\1) +skip\? + endm + + lda #0 ;combined bit test + sta zpt +bbcl lda #0 + bbrc 0 + bbrc 1 + bbrc 2 + bbrc 3 + bbrc 4 + bbrc 5 + bbrc 6 + bbrc 7 + eor zpt + trap_ne ;failed bbr bitnum in accu + lda #$ff + bbsc 0 + bbsc 1 + bbsc 2 + bbsc 3 + bbsc 4 + bbsc 5 + bbsc 6 + bbsc 7 + eor zpt + trap_ne ;failed bbs bitnum in accu + inc zpt + bne bbcl + next_test + endif + +; testing NOP + +nop_test macro ;\1 = opcode, \2 = # of bytes + ldy #$42 + ldx #4-\2 + db \1 ;test nop length + if \2 = 1 + dex + dex + endif + if \2 = 2 + iny + dex + endif + if \2 = 3 + iny + iny + endif + dex + trap_ne ;wrong number of bytes + set_a $ff-\1,0 + db \1 ;test nop integrity - flags off + nop + nop + tst_a $ff-\1,0 + set_a $aa-\1,$ff + db \1 ;test nop integrity - flags on + nop + nop + tst_a $aa-\1,$ff + cpy #$42 + trap_ne ;y changed + cpx #0 + trap_ne ;x changed + endm + + nop_test $02,2 + nop_test $22,2 + nop_test $42,2 + nop_test $62,2 + nop_test $82,2 + nop_test $c2,2 + nop_test $e2,2 + nop_test $44,2 + nop_test $54,2 + nop_test $d4,2 + nop_test $f4,2 + nop_test $5c,3 + nop_test $dc,3 + nop_test $fc,3 + nop_test $03,1 + nop_test $13,1 + nop_test $23,1 + nop_test $33,1 + nop_test $43,1 + nop_test $53,1 + nop_test $63,1 + nop_test $73,1 + nop_test $83,1 + nop_test $93,1 + nop_test $a3,1 + nop_test $b3,1 + nop_test $c3,1 + nop_test $d3,1 + nop_test $e3,1 + nop_test $f3,1 + nop_test $0b,1 + nop_test $1b,1 + nop_test $2b,1 + nop_test $3b,1 + nop_test $4b,1 + nop_test $5b,1 + nop_test $6b,1 + nop_test $7b,1 + nop_test $8b,1 + nop_test $9b,1 + nop_test $ab,1 + nop_test $bb,1 + nop_test $eb,1 + nop_test $fb,1 + if rkwl_wdc_op = 0 ;NOPs not available on Rockwell & WDC 65C02 + nop_test $07,1 + nop_test $17,1 + nop_test $27,1 + nop_test $37,1 + nop_test $47,1 + nop_test $57,1 + nop_test $67,1 + nop_test $77,1 + nop_test $87,1 + nop_test $97,1 + nop_test $a7,1 + nop_test $b7,1 + nop_test $c7,1 + nop_test $d7,1 + nop_test $e7,1 + nop_test $f7,1 + nop_test $0f,1 + nop_test $1f,1 + nop_test $2f,1 + nop_test $3f,1 + nop_test $4f,1 + nop_test $5f,1 + nop_test $6f,1 + nop_test $7f,1 + nop_test $8f,1 + nop_test $9f,1 + nop_test $af,1 + nop_test $bf,1 + nop_test $cf,1 + nop_test $df,1 + nop_test $ef,1 + nop_test $ff,1 + endif + if wdc_op = 0 ;NOPs not available on WDC 65C02 (WAI, STP) + nop_test $cb,1 + nop_test $db,1 + endif + next_test + +; jump indirect (test page cross bug is fixed) + ldx #3 ;prepare table +ji1 lda ji_adr,x + sta ji_tab,x + dex + bpl ji1 + lda #hi(ji_px) ;high address if page cross bug + sta pg_x + set_stat 0 + lda #'I' + ldx #'N' + ldy #'D' ;N=0, V=0, Z=0, C=0 + jmp (ji_tab) + nop + trap_ne ;runover protection + + dey + dey +ji_ret php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('I'^$aa) ;returned registers OK? + trap_ne + cpx #('N'+1) + trap_ne + cpy #('D'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + next_test + +; jump indexed indirect + ldx #11 ;prepare table +jxi1 lda jxi_adr,x + sta jxi_tab,x + dex + bpl jxi1 + lda #hi(jxi_px) ;high address if page cross bug + sta pg_x + set_stat 0 + lda #'X' + ldx #4 + ldy #'I' ;N=0, V=0, Z=0, C=0 + jmp (jxi_tab,x) + nop + trap_ne ;runover protection + + dey + dey +jxi_ret php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_eq ;returned flags OK? + trap_pl + trap_cc + trap_vc + cmp #('X'^$aa) ;returned registers OK? + trap_ne + cpx #6 + trap_ne + cpy #('I'-6) + trap_ne + tsx ;SP check + cpx #$ff + trap_ne + + lda #lo(jxp_ok) ;test with index causing a page cross + sta jxp_tab + lda #hi(jxp_ok) + sta jxp_tab+1 + lda #lo(jxp_px) + sta pg_x + lda #hi(jxp_px) + sta pg_x+1 + ldx #$ff + jmp (jxp_tab-$ff,x) + +jxp_px + trap ;page cross by index to wrong page + +jxp_ok + next_test + + if ROM_vectors = 1 +; test BRK clears decimal mode + sed + brk + nop +brk_ret + next_test + endif + +; testing accumulator increment/decrement INC A & DEC A + ldx #$ac ;protect x & y + ldy #$dc + set_a $fe,$ff + inc a ;ff + tst_as $ff,$ff-zero + inc a ;00 + tst_as 0,$ff-minus + inc a ;01 + tst_as 1,$ff-minus-zero + dec a ;00 + tst_as 0,$ff-minus + dec a ;ff + tst_as $ff,$ff-zero + dec a ;fe + set_a $fe,0 + inc a ;ff + tst_as $ff,minus + inc a ;00 + tst_as 0,zero + inc a ;01 + tst_as 1,0 + dec a ;00 + tst_as 0,zero + dec a ;ff + tst_as $ff,minus + cpx #$ac + trap_ne ;x altered during test + cpy #$dc + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing load / store accumulator LDA / STA (zp) + ldx #$99 ;protect x & y + ldy #$66 + set_stat 0 + lda (ind1) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt) + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx ;test flags + trap_ne + set_stat 0 + lda (ind1+2) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+2) + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+1 ;test flags + trap_ne + set_stat 0 + lda (ind1+4) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+4) + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+2 ;test flags + trap_ne + set_stat 0 + lda (ind1+6) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+6) + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag 0 + cmp fLDx+3 ;test flags + trap_ne + cpx #$99 + trap_ne ;x altered during test + cpy #$66 + trap_ne ;y altered during test + + ldy #3 ;testing store result + ldx #0 +tstai1 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to indirect data + txa + sta abst,y ;clear + dey + bpl tstai1 + + ldx #$99 ;protect x & y + ldy #$66 + set_stat $ff + lda (ind1) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt) + php ;flags after load/store sequence + eor #$c3 + cmp #$c3 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx ;test flags + trap_ne + set_stat $ff + lda (ind1+2) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+2) + php ;flags after load/store sequence + eor #$c3 + cmp #$82 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+1 ;test flags + trap_ne + set_stat $ff + lda (ind1+4) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+4) + php ;flags after load/store sequence + eor #$c3 + cmp #$41 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+2 ;test flags + trap_ne + set_stat $ff + lda (ind1+6) + php ;test stores do not alter flags + eor #$c3 + plp + sta (indt+6) + php ;flags after load/store sequence + eor #$c3 + cmp #0 ;test result + trap_ne + pla ;load status + eor_flag lo~fnz ;mask bits not altered + cmp fLDx+3 ;test flags + trap_ne + cpx #$99 + trap_ne ;x altered during test + cpy #$66 + trap_ne ;y altered during test + + ldy #3 ;testing store result + ldx #0 +tstai2 lda abst,y + eor #$c3 + cmp abs1,y + trap_ne ;store to indirect data + txa + sta abst,y ;clear + dey + bpl tstai2 + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing STZ - zp / abs / zp,x / abs,x + ldy #123 ;protect y + ldx #4 ;precharge test area + lda #7 +tstz1 sta zpt,x + asl a + dex + bpl tstz1 + ldx #4 + set_a $55,$ff + stz zpt + stz zpt+1 + stz zpt+2 + stz zpt+3 + stz zpt+4 + tst_a $55,$ff +tstz2 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz2 + ldx #4 ;precharge test area + lda #7 +tstz3 sta zpt,x + asl a + dex + bpl tstz3 + ldx #4 + set_a $aa,0 + stz zpt + stz zpt+1 + stz zpt+2 + stz zpt+3 + stz zpt+4 + tst_a $aa,0 +tstz4 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz4 + + ldx #4 ;precharge test area + lda #7 +tstz5 sta abst,x + asl a + dex + bpl tstz5 + ldx #4 + set_a $55,$ff + stz abst + stz abst+1 + stz abst+2 + stz abst+3 + stz abst+4 + tst_a $55,$ff +tstz6 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ abs + dex + bpl tstz6 + ldx #4 ;precharge test area + lda #7 +tstz7 sta abst,x + asl a + dex + bpl tstz7 + ldx #4 + set_a $aa,0 + stz abst + stz abst+1 + stz abst+2 + stz abst+3 + stz abst+4 + tst_a $aa,0 +tstz8 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ abs + dex + bpl tstz8 + + ldx #4 ;precharge test area + lda #7 +tstz11 sta zpt,x + asl a + dex + bpl tstz11 + ldx #4 +tstz15 + set_a $55,$ff + stz zpt,x + tst_a $55,$ff + dex + bpl tstz15 + ldx #4 +tstz12 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz12 + ldx #4 ;precharge test area + lda #7 +tstz13 sta zpt,x + asl a + dex + bpl tstz13 + ldx #4 +tstz16 + set_a $aa,0 + stz zpt,x + tst_a $aa,0 + dex + bpl tstz16 + ldx #4 +tstz14 lda zpt,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz14 + + ldx #4 ;precharge test area + lda #7 +tstz21 sta abst,x + asl a + dex + bpl tstz21 + ldx #4 +tstz25 + set_a $55,$ff + stz abst,x + tst_a $55,$ff + dex + bpl tstz25 + ldx #4 +tstz22 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz22 + ldx #4 ;precharge test area + lda #7 +tstz23 sta abst,x + asl a + dex + bpl tstz23 + ldx #4 +tstz26 + set_a $aa,0 + stz abst,x + tst_a $aa,0 + dex + bpl tstz26 + ldx #4 +tstz24 lda abst,x ;verify zeros stored + trap_ne ;non zero after STZ zp + dex + bpl tstz24 + + cpy #123 + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing BIT - zp,x / abs,x / # + ldy #$42 + ldx #3 + set_a $ff,0 + bit zp1,x ;00 - should set Z / clear NV + tst_a $ff,fz + dex + set_a 1,0 + bit zp1,x ;41 - should set V (M6) / clear NZ + tst_a 1,fv + dex + set_a 1,0 + bit zp1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + dex + set_a 1,0 + bit zp1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a 1,$ff + bit zp1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + inx + set_a 1,$ff + bit zp1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + inx + set_a 1,$ff + bit zp1,x ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + inx + set_a $ff,$ff + bit zp1,x ;00 - should set Z / clear NV + tst_a $ff,~fnv + + set_a $ff,0 + bit abs1,x ;00 - should set Z / clear NV + tst_a $ff,fz + dex + set_a 1,0 + bit abs1,x ;41 - should set V (M6) / clear NZ + tst_a 1,fv + dex + set_a 1,0 + bit abs1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,fnz + dex + set_a 1,0 + bit abs1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,fnv + + set_a 1,$ff + bit abs1,x ;c3 - should set N (M7) & V (M6) / clear Z + tst_a 1,~fz + inx + set_a 1,$ff + bit abs1,x ;82 - should set N (M7) & Z / clear V + tst_a 1,~fv + inx + set_a 1,$ff + bit abs1,x ;41 - should set V (M6) / clear NZ + tst_a 1,~fnz + inx + set_a $ff,$ff + bit abs1,x ;00 - should set Z / clear NV + tst_a $ff,~fnv + + set_a $ff,0 + bit #$00 ;00 - should set Z + tst_a $ff,fz + dex + set_a 1,0 + bit #$41 ;41 - should clear Z + tst_a 1,0 +; *** DEBUG INFO *** +; if it fails the previous test and your BIT # has set the V flag +; see http://forum.6502.org/viewtopic.php?f=2&t=2241&p=27243#p27239 +; why it shouldn't alter N or V flags on a BIT # + dex + set_a 1,0 + bit #$82 ;82 - should set Z + tst_a 1,fz + dex + set_a 1,0 + bit #$c3 ;c3 - should clear Z + tst_a 1,0 + + set_a 1,$ff + bit #$c3 ;c3 - clear Z + tst_a 1,~fz + inx + set_a 1,$ff + bit #$82 ;82 - should set Z + tst_a 1,$ff + inx + set_a 1,$ff + bit #$41 ;41 - should clear Z + tst_a 1,~fz + inx + set_a $ff,$ff + bit #$00 ;00 - should set Z + tst_a $ff,$ff + + cpx #3 + trap_ne ;x altered during test + cpy #$42 + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing TRB, TSB - zp / abs + +trbt macro ;\1 = memory, \2 = flags + sty \1 + load_flag \2 + pha + lda zpt+1 + plp + trb \1 + php + cmp zpt+1 + trap_ne ;accu was changed + pla + pha + ora #fz ;mask Z + cmp_flag \2|fz + trap_ne ;flags changed except Z + pla + and #fz + cmp zpt+2 + trap_ne ;Z flag invalid + lda zpt+3 + cmp zpt + trap_ne ;altered bits in memory wrong + endm + +tsbt macro ;\1 = memory, \2 = flags + sty \1 + load_flag \2 + pha + lda zpt+1 + plp + tsb \1 + php + cmp zpt+1 + trap_ne ;accu was changed + pla + pha + ora #fz ;mask Z + cmp_flag \2|fz + trap_ne ;flags changed except Z + pla + and #fz + cmp zpt+2 + trap_ne ;Z flag invalid + lda zpt+4 + cmp zpt + trap_ne ;altered bits in memory wrong + endm + + ldx #$c0 + ldy #0 ;op1 - memory save + ; zpt ;op1 - memory modifiable + stz zpt+1 ;op2 - accu + ; zpt+2 ;and flags + ; zpt+3 ;memory after reset + ; zpt+4 ;memory after set + +tbt1 tya + and zpt+1 ;set Z by anding the 2 operands + php + pla + and #fz ;mask Z + sta zpt+2 + tya ;reset op1 bits by op2 + eor #$ff + ora zpt+1 + eor #$ff + sta zpt+3 + tya ;set op1 bits by op2 + ora zpt+1 + sta zpt+4 + + trbt zpt,$ff + trbt abst,$ff + trbt zpt,0 + trbt abst,0 + tsbt zpt,$ff + tsbt abst,$ff + tsbt zpt,0 + tsbt abst,0 + + iny ;iterate op1 + bne tbt3 + inc zpt+1 ;iterate op2 + beq tbt2 +tbt3 jmp tbt1 +tbt2 + cpx #$c0 + trap_ne ;x altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + + if rkwl_wdc_op +; testing RMB, SMB - zp +rmbt macro ;\1 = bitnum + lda #$ff + sta zpt + set_a $a5,0 + rmb \1,zpt + tst_a $a5,0 + lda zpt + cmp #$ff-(1<<\1) + trap_ne ;wrong bits set or cleared + lda #1<<\1 + sta zpt + set_a $5a,$ff + rmb \1,zpt + tst_a $5a,$ff + lda zpt + trap_ne ;wrong bits set or cleared + endm +smbt macro ;\1 = bitnum + lda #$ff-(1<<\1) + sta zpt + set_a $a5,0 + smb \1,zpt + tst_a $a5,0 + lda zpt + cmp #$ff + trap_ne ;wrong bits set or cleared + lda #0 + sta zpt + set_a $5a,$ff + smb \1,zpt + tst_a $5a,$ff + lda zpt + cmp #1<<\1 + trap_ne ;wrong bits set or cleared + endm + + ldx #$ba ;protect x & y + ldy #$d0 + rmbt 0 + rmbt 1 + rmbt 2 + rmbt 3 + rmbt 4 + rmbt 5 + rmbt 6 + rmbt 7 + smbt 0 + smbt 1 + smbt 2 + smbt 3 + smbt 4 + smbt 5 + smbt 6 + smbt 7 + cpx #$ba + trap_ne ;x altered during test + cpy #$d0 + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + endif + +; testing CMP - (zp) + ldx #$de ;protect x & y + ldy #$ad + set_a $80,0 + cmp (ind1+8) + tst_a $80,fc + set_a $7f,0 + cmp (ind1+8) + tst_a $7f,fzc + set_a $7e,0 + cmp (ind1+8) + tst_a $7e,fn + set_a $80,$ff + cmp (ind1+8) + tst_a $80,~fnz + set_a $7f,$ff + cmp (ind1+8) + tst_a $7f,~fn + set_a $7e,$ff + cmp (ind1+8) + tst_a $7e,~fzc + cpx #$de + trap_ne ;x altered during test + cpy #$ad + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; testing logical instructions - AND EOR ORA (zp) + ldx #$42 ;protect x & y + + ldy #0 ;AND + lda indAN ;set indirect address + sta zpt + lda indAN+1 + sta zpt+1 +tand1 + set_ay absANa,0 + and (zpt) + tst_ay absrlo,absflo,0 + inc zpt + iny + cpy #4 + bne tand1 + dey + dec zpt +tand2 + set_ay absANa,$ff + and (zpt) + tst_ay absrlo,absflo,$ff-fnz + dec zpt + dey + bpl tand2 + + ldy #0 ;EOR + lda indEO ;set indirect address + sta zpt + lda indEO+1 + sta zpt+1 +teor1 + set_ay absEOa,0 + eor (zpt) + tst_ay absrlo,absflo,0 + inc zpt + iny + cpy #4 + bne teor1 + dey + dec zpt +teor2 + set_ay absEOa,$ff + eor (zpt) + tst_ay absrlo,absflo,$ff-fnz + dec zpt + dey + bpl teor2 + + ldy #0 ;ORA + lda indOR ;set indirect address + sta zpt + lda indOR+1 + sta zpt+1 +tora1 + set_ay absORa,0 + ora (zpt) + tst_ay absrlo,absflo,0 + inc zpt + iny + cpy #4 + bne tora1 + dey + dec zpt +tora2 + set_ay absORa,$ff + ora (zpt) + tst_ay absrlo,absflo,$ff-fnz + dec zpt + dey + bpl tora2 + + cpx #$42 + trap_ne ;x altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + + if I_flag = 3 + cli + endif + +; full binary add/subtract test - (zp) only +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags + cld + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #0 ;start with adding zeroes & no carry + sta adfc ;carry in - for diag + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + sta adrh ;expected result bit 8 (carry out) + lda #$ff ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp + lda #2 ;expected Z-flag + sta adrf +tadd clc ;test with carry clear + jsr chkadd + inc adfc ;now with carry + inc adrl ;result +1 + php ;save N & Z from low result + php + pla ;accu holds expected flags + and #$82 ;mask N & Z + plp + bne tadd1 + inc adrh ;result bit 8 - carry +tadd1 ora adrh ;merge C to expected flags + sta adrf ;save expected flags except overflow + sec ;test with carry set + jsr chkadd + dec adfc ;same for operand +1 but no carry + inc ad1 + bne tadd ;iterate op1 + lda #0 ;preset result to op2 when op1 = 0 + sta adrh + inc ada2 + inc ad2 + php ;save NZ as operand 2 becomes the new result + pla + and #$82 ;mask N00000Z0 + sta adrf ;no need to check carry as we are adding to 0 + dec sb2 ;complement subtract operand 2 + dec sba2 + lda ad2 + sta adrl + bne tadd ;iterate op2 + + cpx #ad2 + trap_ne ;x altered during test + cpy #$ff + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + next_test + +; decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, the V flag is ignored +; although V is declared as beeing valid on the 65C02 it has absolutely +; no use in BCD math. No sign = no overflow! +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag + sed + ldx #ad2 ;for indexed test + ldy #$ff ;max range + lda #$99 ;start with adding 99 to 99 with carry + sta ad1 ;operand 1 - accumulator + sta ad2 ;operand 2 - memory or immediate + sta ada2 ;non zp + sta adrl ;expected result bits 0-7 + lda #1 ;set carry in & out + sta adfc ;carry in - for diag + sta adrh ;expected result bit 8 (carry out) + lda #$81 ;set N & C (99 + 99 + C = 99 + C) + sta adrf + lda #0 ;complemented operand 2 for subtract + sta sb2 + sta sba2 ;non zp +tdad sec ;test with carry set + jsr chkdad + dec adfc ;now with carry clear + lda adrl ;decimal adjust result + bne tdad1 ;skip clear carry & preset result 99 (9A-1) + dec adrh + lda #$99 + sta adrl + bne tdad3 +tdad1 and #$f ;lower nibble mask + bne tdad2 ;no decimal adjust needed + dec adrl ;decimal adjust (?0-6) + dec adrl + dec adrl + dec adrl + dec adrl + dec adrl +tdad2 dec adrl ;result -1 +tdad3 php ;save valid flags + pla + and #$82 ;N-----Z- + ora adrh ;N-----ZC + sta adrf + clc ;test with carry clear + jsr chkdad + inc adfc ;same for operand -1 but with carry + lda ad1 ;decimal adjust operand 1 + beq tdad5 ;iterate operand 2 + and #$f ;lower nibble mask + bne tdad4 ;skip decimal adjust + dec ad1 ;decimal adjust (?0-6) + dec ad1 + dec ad1 + dec ad1 + dec ad1 + dec ad1 +tdad4 dec ad1 ;operand 1 -1 + jmp tdad ;iterate op1 + +tdad5 lda #$99 ;precharge op1 max + sta ad1 + lda ad2 ;decimal adjust operand 2 + beq tdad7 ;end of iteration + and #$f ;lower nibble mask + bne tdad6 ;skip decimal adjust + dec ad2 ;decimal adjust (?0-6) + dec ad2 + dec ad2 + dec ad2 + dec ad2 + dec ad2 + inc sb2 ;complemented decimal adjust for subtract (?9+6) + inc sb2 + inc sb2 + inc sb2 + inc sb2 + inc sb2 +tdad6 dec ad2 ;operand 2 -1 + inc sb2 ;complemented operand for subtract + lda sb2 + sta sba2 ;copy as non zp operand + lda ad2 + sta ada2 ;copy as non zp operand + sta adrl ;new result since op1+carry=00+carry +op2=op2 + php ;save flags + pla + and #$82 ;N-----Z- + ora #1 ;N-----ZC + sta adrf + inc adrh ;result carry + jmp tdad ;iterate op2 + +tdad7 cpx #ad2 + trap_ne ;x altered during test + cpy #$ff + trap_ne ;y altered during test + tsx + cpx #$ff + trap_ne ;sp push/pop mismatch + cld + + lda test_case + cmp #test_num + trap_ne ;test is out of sequence + +; final RAM integrity test +; verifies that none of the previous tests has altered RAM outside of the +; designated write areas. + check_ram +; *** DEBUG INFO *** +; to debug checksum errors uncomment check_ram in the next_test macro to +; narrow down the responsible opcode. +; may give false errors when monitor, OS or other background activity is +; allowed during previous tests. + + + +; S U C C E S S ************************************************ +; ------------- + success ;if you get here everything went well +; ------------- +; S U C C E S S ************************************************ + +; core subroutine of the decimal add/subtract test +; *** WARNING - tests documented behavior only! *** +; only valid BCD operands are tested, V flag is ignored +; iterates through all valid combinations of operands and carry input +; uses increments/decrements to predict result & carry flag +chkdad +; decimal ADC / SBC zp + php ;save carry for subtract + lda ad1 + adc ad2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC abs + php ;save carry for subtract + lda ad1 + adc ada2 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC # + php ;save carry for subtract + lda ad2 + sta chkdadi ;self modify immediate + lda ad1 +chkdadi = * + 1 ;operand of the immediate ADC + adc #0 ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda sb2 + sta chkdsbi ;self modify immediate + lda ad1 +chkdsbi = * + 1 ;operand of the immediate SBC + sbc #0 ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC zp,x + php ;save carry for subtract + lda ad1 + adc 0,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sb2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC abs,x + php ;save carry for subtract + lda ad1 + adc ada2-ad2,x ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-ad2,x ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC abs,y + php ;save carry for subtract + lda ad1 + adc ada2-$ff,y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc sba2-$ff,y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC (zp,x) + php ;save carry for subtract + lda ad1 + adc (lo adi2-ad2,x) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (lo sbi2-ad2,x) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC (abs),y + php ;save carry for subtract + lda ad1 + adc (adiy2),y ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbiy2),y ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp +; decimal ADC / SBC (zp) + php ;save carry for subtract + lda ad1 + adc (adi2) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbi2) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$83 ;mask N-----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; core subroutine of the full binary add/subtract test +; iterates through all combinations of operands and carry input +; uses increments/decrements to predict result & result flags +chkadd lda adrf ;add V-flag if overflow + and #$83 ;keep N-----ZC / clear V + pha + lda ad1 ;test sign unequal between operands + eor ad2 + bmi ckad1 ;no overflow possible - operands have different sign + lda ad1 ;test sign equal between operands and result + eor adrl + bpl ckad1 ;no overflow occured - operand and result have same sign + pla + ora #$40 ;set V + pha +ckad1 pla + sta adrf ;save expected flags +; binary ADC / SBC (zp) + php ;save carry for subtract + lda ad1 + adc (adi2) ;perform add + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + php ;save carry for next add + lda ad1 + sbc (sbi2) ;perform subtract + php + cmp adrl ;check result + trap_ne ;bad result + pla ;check flags + and #$c3 ;mask NV----ZC + cmp adrf + trap_ne ;bad flags + plp + rts + +; target for the jump indirect test +ji_adr dw test_ji + dw ji_ret + + dey + dey +test_ji + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'I' ;registers loaded? + trap_ne + cpx #'N' + trap_ne + cpy #('D'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (ji_tab+2) + nop + nop + trap ;runover protection + +; target for the jump indirect test +jxi_adr dw trap_ind + dw trap_ind + dw test_jxi ;+4 + dw jxi_ret ;+6 + dw trap_ind + dw trap_ind + + dey + dey +test_jxi + php ;either SP or Y count will fail, if we do not hit + dey + dey + dey + plp + trap_cs ;flags loaded? + trap_vs + trap_mi + trap_eq + cmp #'X' ;registers loaded? + trap_ne + cpx #4 + trap_ne + cpy #('I'-3) + trap_ne + pha ;save a,x + txa + pha + tsx + cpx #$fd ;check SP + trap_ne + pla ;restore x + tax + set_stat $ff + pla ;restore a + inx ;return registers with modifications + inx + eor #$aa ;N=1, V=1, Z=0, C=1 + jmp (jxi_tab,x) + nop + nop + trap ;runover protection + +; JMP (abs,x) with bad x + nop + nop +trap_ind + nop + nop + trap ;near miss indexed indirect jump + +;trap in case of unexpected IRQ, NMI, BRK, RESET +nmi_trap + trap ;check stack for conditions at NMI +res_trap + trap ;unexpected RESET +irq_trap + php ;save decimal flag + tsx ;test break on stack + lda $102,x + and #break + trap_eq ;check stack for conditions at IRQ + if ROM_vectors = 1 + pla ;test decimal mode cleared + and #decmode + trap_ne ;decimal mode not cleared after BRK + plp ;pop saved flags + pla ;return address low + cmp #lo(brk_ret) + trap_ne ;unexpected BRK + pla ;return address high + cmp #hi(brk_ret) + trap_ne ;unexpected BRK + jmp brk_ret + else + trap_ne ;check stack for conditions at BRK + endif + +;copy of data to initialize BSS segment + if load_data_direct != 1 +zp_init +zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +zp7f_ db $7f ;test pattern for compare +;logical zeropage operands +zpOR_ db 0,$1f,$71,$80 ;test pattern for OR +zpAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +zpEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;indirect addressing pointers +ind1_ dw abs1 ;indirect pointer to pattern in absolute memory + dw abs1+1 + dw abs1+2 + dw abs1+3 + dw abs7f +inw1_ dw abs1-$f8 ;indirect pointer for wrap-test pattern +indt_ dw abst ;indirect pointer to store area in absolute memory + dw abst+1 + dw abst+2 + dw abst+3 +inwt_ dw abst-$f8 ;indirect pointer for wrap-test store +indAN_ dw absAN ;indirect pointer to AND pattern in absolute memory + dw absAN+1 + dw absAN+2 + dw absAN+3 +indEO_ dw absEO ;indirect pointer to EOR pattern in absolute memory + dw absEO+1 + dw absEO+2 + dw absEO+3 +indOR_ dw absOR ;indirect pointer to OR pattern in absolute memory + dw absOR+1 + dw absOR+2 + dw absOR+3 +;add/subtract indirect pointers +adi2_ dw ada2 ;indirect pointer to operand 2 in absolute memory +sbi2_ dw sba2 ;indirect pointer to complemented operand 2 (SBC) +adiy2_ dw ada2-$ff ;with offset for indirect indexed +sbiy2_ dw sba2-$ff +zp_end + if (zp_end - zp_init) != (zp_bss_end - zp_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and zeropage data + endif +data_init +abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR +abs7f_ db $7f ;test pattern for compare +;loads +fLDx_ db fn,fn,0,fz ;expected flags for load +;shifts +rASL_ ;expected result ASL & ROL -carry +rROL_ db $86,$04,$82,0 ; " +rROLc_ db $87,$05,$83,1 ;expected result ROL +carry +rLSR_ ;expected result LSR & ROR -carry +rROR_ db $61,$41,$20,0 ; " +rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry +fASL_ ;expected flags for shifts +fROL_ db fnc,fc,fn,fz ;no carry in +fROLc_ db fnc,fc,fn,0 ;carry in +fLSR_ +fROR_ db fc,0,fc,fz ;no carry in +fRORc_ db fnc,fn,fnc,fn ;carry in +;increments (decrements) +rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC +fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC +;logical memory operand +absOR_ db 0,$1f,$71,$80 ;test pattern for OR +absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND +absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR +;logical accu operand +absORa_ db 0,$f1,$1f,0 ;test pattern for OR +absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND +absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR +;logical results +absrlo_ db 0,$ff,$7f,$80 +absflo_ db fz,fn,0,fn +data_end + if (data_end - data_init) != (data_bss_end - data_bss) + ;force assembler error if size is different + ERROR ERROR ERROR ;mismatch between bss and data + endif + +vec_init + dw nmi_trap + dw res_trap + dw irq_trap +vec_bss equ $fffa + endif ;end of RAM init data + +; code at end of image due to the need to add blank space as required + if ($ff & (ji_ret - * - 2)) < ($ff & (jxi_ret - * - 2)) +; JMP (abs) when $xxff and $xx00 are from same page + ds lo(ji_ret - * - 2) + nop + nop +ji_px nop ;low address byte matched with ji_ret + nop + trap ;jmp indirect page cross bug + +; JMP (abs,x) when $xxff and $xx00 are from same page + ds lo(jxi_ret - * - 2) + nop + nop +jxi_px nop ;low address byte matched with jxi_ret + nop + trap ;jmp indexed indirect page cross bug + else +; JMP (abs,x) when $xxff and $xx00 are from same page + ds lo(jxi_ret - * - 2) + nop + nop +jxi_px nop ;low address byte matched with jxi_ret + nop + trap ;jmp indexed indirect page cross bug + +; JMP (abs) when $xxff and $xx00 are from same page + ds lo(ji_ret - * - 2) + nop + nop +ji_px nop ;low address byte matched with ji_ret + nop + trap ;jmp indirect page cross bug + endif + + if (load_data_direct = 1) & (ROM_vectors = 1) + org $fffa ;vectors + dw nmi_trap + dw res_trap + dw irq_trap + endif + + end start + \ No newline at end of file diff --git a/license.txt b/license.txt new file mode 100644 index 0000000..94a9ed0 --- /dev/null +++ b/license.txt @@ -0,0 +1,674 @@ + GNU GENERAL PUBLIC LICENSE + Version 3, 29 June 2007 + + Copyright (C) 2007 Free Software Foundation, Inc. + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The GNU General Public License is a free, copyleft license for +software and other kinds of works. + + The licenses for most software and other practical works are designed +to take away your freedom to share and change the works. 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If not, see . + +Also add information on how to contact you by electronic and paper mail. + + If the program does terminal interaction, make it output a short +notice like this when it starts in an interactive mode: + + Copyright (C) + This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'. + This is free software, and you are welcome to redistribute it + under certain conditions; type `show c' for details. + +The hypothetical commands `show w' and `show c' should show the appropriate +parts of the General Public License. Of course, your program's commands +might be different; for a GUI interface, you would use an "about box". + + You should also get your employer (if you work as a programmer) or school, +if any, to sign a "copyright disclaimer" for the program, if necessary. +For more information on this, and how to apply and follow the GNU GPL, see +. + + The GNU General Public License does not permit incorporating your program +into proprietary programs. If your program is a subroutine library, you +may consider it more useful to permit linking proprietary applications with +the library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. But first, please read +. diff --git a/readme.txt b/readme.txt new file mode 100644 index 0000000..440de2f --- /dev/null +++ b/readme.txt @@ -0,0 +1,27 @@ +This is a set of functional tests for the 6502/65C02 type processors. + +The 6502_functionel_test.a65 is an assembler sourcecode to test all valid +opcodes and addressing modes of the original NMOS 6502 cpu. + +The 65C02_extended_opcodes_test.a65c tests all additional opcodes of the +65C02 processor including undefined opcodes. + +The 6502_interrupt_test.a65 is a simple test to check the interrupt system +of both processors. A feedback register is required to inject IRQ and NMI +requests. + +All source files are included in the zipped file. + +Detailed information about how to configure, assemble and run the tests is +included in each source file. + +The tests have primarily been written to test my own ATMega16 6502 emulator +project. You can find it here: http://2m5.de/6502_Emu/index.htm + +A discussion about the tests can be found here: +http://forum.6502.org/viewtopic.php?f=2&t=2241 + +Good luck debugging your emulator, simulator, vhdl core, discrete +logic implementation or whatever you have! + +