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fixed shifts not testing zero result and flag when last 1-bit is shifted out

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Klaus2m5 2020-01-05 14:10:38 +01:00
parent fe99e56162
commit 7954e2dbb4
3 changed files with 185 additions and 175 deletions
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298
6502_functional_test.a65
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@ -1,7 +1,7 @@
; ;
; 6 5 0 2 F U N C T I O N A L T E S T ; 6 5 0 2 F U N C T I O N A L T E S T
; ;
; Copyright (C) 2012-2015 Klaus Dormann ; Copyright (C) 2012-2020 Klaus Dormann
; ;
; This program is free software: you can redistribute it and/or modify ; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by ; it under the terms of the GNU General Public License as published by
@ -21,10 +21,11 @@
; addressing modes with focus on propper setting of the processor status ; addressing modes with focus on propper setting of the processor status
; register bits. ; register bits.
; ;
; version 04-dec-2017 ; version 05-jan-2020
; contact info at http://2m5.de or email K@2m5.de ; contact info at http://2m5.de or email K@2m5.de
; ;
; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/ ; assembled with AS65 written by Frank A. Kingswood
; The assembler as65_142.zip can be obtained from my GitHub repository
; command line switches: -l -m -s2 -w -h0 ; command line switches: -l -m -s2 -w -h0
; | | | | no page headers in listing ; | | | | no page headers in listing
; | | | wide listing (133 char/col) ; | | | wide listing (133 char/col)
@ -76,7 +77,8 @@
; 04-dec-2017 fixed BRK only tested with interrupts enabled ; 04-dec-2017 fixed BRK only tested with interrupts enabled
; added option to skip the remainder of a failing test ; added option to skip the remainder of a failing test
; in report.i65 ; in report.i65
; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit
; is shifted out
; C O N F I G U R A T I O N ; C O N F I G U R A T I O N
@ -96,17 +98,17 @@ load_data_direct = 1
I_flag = 3 I_flag = 3
;configure memory - try to stay away from memory used by the system ;configure memory - try to stay away from memory used by the system
;zero_page memory start address, $50 (80) consecutive Bytes required ;zero_page memory start address, $52 (82) consecutive Bytes required
; add 2 if I_flag = 2 ; add 2 if I_flag = 2
zero_page = $a zero_page = $a
;data_segment memory start address, $6A (106) consecutive Bytes required ;data_segment memory start address, $7B (123) consecutive Bytes required
data_segment = $200 data_segment = $200
if (data_segment & $ff) != 0 if (data_segment & $ff) != 0
ERROR ERROR ERROR low byte of data_segment MUST be $00 !! ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
endif endif
;code_segment memory start address, 13kB of consecutive space required ;code_segment memory start address, 13.1kB of consecutive space required
; add 2.5 kB if I_flag = 2 ; add 2.5 kB if I_flag = 2
code_segment = $400 code_segment = $400
@ -621,7 +623,7 @@ irq_x ds 1 ;x register
flag_I_on ds 1 ;or mask to load flags flag_I_on ds 1 ;or mask to load flags
flag_I_off ds 1 ;and mask to load flags flag_I_off ds 1 ;and mask to load flags
endif endif
zpt ;5 bytes store/modify test area zpt ;6 bytes store/modify test area
;add/subtract operand generation and result/flag prediction ;add/subtract operand generation and result/flag prediction
adfc ds 1 ;carry flag before op adfc ds 1 ;carry flag before op
ad1 ds 1 ;operand 1 - accumulator ad1 ds 1 ;operand 1 - accumulator
@ -631,6 +633,7 @@ adrh ds 1 ;expected result bit 8 (carry)
adrf ds 1 ;expected flags NV0000ZC (only binary mode) adrf ds 1 ;expected flags NV0000ZC (only binary mode)
sb2 ds 1 ;operand 2 complemented for subtract sb2 ds 1 ;operand 2 complemented for subtract
zp_bss zp_bss
zps db $80,1 ;additional shift pattern to test zero result & flag
zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
zp7f db $7f ;test pattern for compare zp7f db $7f ;test pattern for compare
;logical zeropage operands ;logical zeropage operands
@ -672,10 +675,10 @@ zp_bss_end
test_case ds 1 ;current test number test_case ds 1 ;current test number
ram_chksm ds 2 ;checksum for RAM integrity test ram_chksm ds 2 ;checksum for RAM integrity test
;add/subtract operand copy - abs tests write area ;add/subtract operand copy - abs tests write area
abst ;5 bytes store/modify test area abst ;6 bytes store/modify test area
ada2 ds 1 ;operand 2 ada2 ds 1 ;operand 2
sba2 ds 1 ;operand 2 complemented for subtract sba2 ds 1 ;operand 2 complemented for subtract
ds 3 ;fill remaining bytes ds 4 ;fill remaining bytes
data_bss data_bss
if load_data_direct = 1 if load_data_direct = 1
ex_andi and #0 ;execute immediate opcodes ex_andi and #0 ;execute immediate opcodes
@ -695,23 +698,24 @@ ex_orai ds 3
ex_adci ds 3 ex_adci ds 3
ex_sbci ds 3 ex_sbci ds 3
endif endif
;zps db $80,1 ;additional shift patterns test zero result & flag
abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
abs7f db $7f ;test pattern for compare abs7f db $7f ;test pattern for compare
;loads ;loads
fLDx db fn,fn,0,fz ;expected flags for load fLDx db fn,fn,0,fz ;expected flags for load
;shifts ;shifts
rASL ;expected result ASL & ROL -carry rASL ;expected result ASL & ROL -carry
rROL db $86,$04,$82,0 ; " rROL db 0,2,$86,$04,$82,0
rROLc db $87,$05,$83,1 ;expected result ROL +carry rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry
rLSR ;expected result LSR & ROR -carry rLSR ;expected result LSR & ROR -carry
rROR db $61,$41,$20,0 ; " rROR db $40,0,$61,$41,$20,0
rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
fASL ;expected flags for shifts fASL ;expected flags for shifts
fROL db fnc,fc,fn,fz ;no carry in fROL db fzc,0,fnc,fc,fn,fz ;no carry in
fROLc db fnc,fc,fn,0 ;carry in fROLc db fc,0,fnc,fc,fn,0 ;carry in
fLSR fLSR
fROR db fc,0,fc,fz ;no carry in fROR db 0,fzc,fc,0,fc,fz ;no carry in
fRORc db fnc,fn,fnc,fn ;carry in fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in
;increments (decrements) ;increments (decrements)
rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC
@ -4070,91 +4074,91 @@ tstay6 lda abst,y
; testing shifts - ASL LSR ROL ROR all addressing modes ; testing shifts - ASL LSR ROL ROR all addressing modes
; shifts - accumulator ; shifts - accumulator
ldx #3 ldx #5
tasl tasl
set_ax zp1,0 set_ax zps,0
asl a asl a
tst_ax rASL,fASL,0 tst_ax rASL,fASL,0
dex dex
bpl tasl bpl tasl
ldx #3 ldx #5
tasl1 tasl1
set_ax zp1,$ff set_ax zps,$ff
asl a asl a
tst_ax rASL,fASL,$ff-fnzc tst_ax rASL,fASL,$ff-fnzc
dex dex
bpl tasl1 bpl tasl1
ldx #3 ldx #5
tlsr tlsr
set_ax zp1,0 set_ax zps,0
lsr a lsr a
tst_ax rLSR,fLSR,0 tst_ax rLSR,fLSR,0
dex dex
bpl tlsr bpl tlsr
ldx #3 ldx #5
tlsr1 tlsr1
set_ax zp1,$ff set_ax zps,$ff
lsr a lsr a
tst_ax rLSR,fLSR,$ff-fnzc tst_ax rLSR,fLSR,$ff-fnzc
dex dex
bpl tlsr1 bpl tlsr1
ldx #3 ldx #5
trol trol
set_ax zp1,0 set_ax zps,0
rol a rol a
tst_ax rROL,fROL,0 tst_ax rROL,fROL,0
dex dex
bpl trol bpl trol
ldx #3 ldx #5
trol1 trol1
set_ax zp1,$ff-fc set_ax zps,$ff-fc
rol a rol a
tst_ax rROL,fROL,$ff-fnzc tst_ax rROL,fROL,$ff-fnzc
dex dex
bpl trol1 bpl trol1
ldx #3 ldx #5
trolc trolc
set_ax zp1,fc set_ax zps,fc
rol a rol a
tst_ax rROLc,fROLc,0 tst_ax rROLc,fROLc,0
dex dex
bpl trolc bpl trolc
ldx #3 ldx #5
trolc1 trolc1
set_ax zp1,$ff set_ax zps,$ff
rol a rol a
tst_ax rROLc,fROLc,$ff-fnzc tst_ax rROLc,fROLc,$ff-fnzc
dex dex
bpl trolc1 bpl trolc1
ldx #3 ldx #5
tror tror
set_ax zp1,0 set_ax zps,0
ror a ror a
tst_ax rROR,fROR,0 tst_ax rROR,fROR,0
dex dex
bpl tror bpl tror
ldx #3 ldx #5
tror1 tror1
set_ax zp1,$ff-fc set_ax zps,$ff-fc
ror a ror a
tst_ax rROR,fROR,$ff-fnzc tst_ax rROR,fROR,$ff-fnzc
dex dex
bpl tror1 bpl tror1
ldx #3 ldx #5
trorc trorc
set_ax zp1,fc set_ax zps,fc
ror a ror a
tst_ax rRORc,fRORc,0 tst_ax rRORc,fRORc,0
dex dex
bpl trorc bpl trorc
ldx #3 ldx #5
trorc1 trorc1
set_ax zp1,$ff set_ax zps,$ff
ror a ror a
tst_ax rRORc,fRORc,$ff-fnzc tst_ax rRORc,fRORc,$ff-fnzc
dex dex
@ -4162,91 +4166,91 @@ trorc1
next_test next_test
; shifts - zeropage ; shifts - zeropage
ldx #3 ldx #5
tasl2 tasl2
set_z zp1,0 set_z zps,0
asl zpt asl zpt
tst_z rASL,fASL,0 tst_z rASL,fASL,0
dex dex
bpl tasl2 bpl tasl2
ldx #3 ldx #5
tasl3 tasl3
set_z zp1,$ff set_z zps,$ff
asl zpt asl zpt
tst_z rASL,fASL,$ff-fnzc tst_z rASL,fASL,$ff-fnzc
dex dex
bpl tasl3 bpl tasl3
ldx #3 ldx #5
tlsr2 tlsr2
set_z zp1,0 set_z zps,0
lsr zpt lsr zpt
tst_z rLSR,fLSR,0 tst_z rLSR,fLSR,0
dex dex
bpl tlsr2 bpl tlsr2
ldx #3 ldx #5
tlsr3 tlsr3
set_z zp1,$ff set_z zps,$ff
lsr zpt lsr zpt
tst_z rLSR,fLSR,$ff-fnzc tst_z rLSR,fLSR,$ff-fnzc
dex dex
bpl tlsr3 bpl tlsr3
ldx #3 ldx #5
trol2 trol2
set_z zp1,0 set_z zps,0
rol zpt rol zpt
tst_z rROL,fROL,0 tst_z rROL,fROL,0
dex dex
bpl trol2 bpl trol2
ldx #3 ldx #5
trol3 trol3
set_z zp1,$ff-fc set_z zps,$ff-fc
rol zpt rol zpt
tst_z rROL,fROL,$ff-fnzc tst_z rROL,fROL,$ff-fnzc
dex dex
bpl trol3 bpl trol3
ldx #3 ldx #5
trolc2 trolc2
set_z zp1,fc set_z zps,fc
rol zpt rol zpt
tst_z rROLc,fROLc,0 tst_z rROLc,fROLc,0
dex dex
bpl trolc2 bpl trolc2
ldx #3 ldx #5
trolc3 trolc3
set_z zp1,$ff set_z zps,$ff
rol zpt rol zpt
tst_z rROLc,fROLc,$ff-fnzc tst_z rROLc,fROLc,$ff-fnzc
dex dex
bpl trolc3 bpl trolc3
ldx #3 ldx #5
tror2 tror2
set_z zp1,0 set_z zps,0
ror zpt ror zpt
tst_z rROR,fROR,0 tst_z rROR,fROR,0
dex dex
bpl tror2 bpl tror2
ldx #3 ldx #5
tror3 tror3
set_z zp1,$ff-fc set_z zps,$ff-fc
ror zpt ror zpt
tst_z rROR,fROR,$ff-fnzc tst_z rROR,fROR,$ff-fnzc
dex dex
bpl tror3 bpl tror3
ldx #3 ldx #5
trorc2 trorc2
set_z zp1,fc set_z zps,fc
ror zpt ror zpt
tst_z rRORc,fRORc,0 tst_z rRORc,fRORc,0
dex dex
bpl trorc2 bpl trorc2
ldx #3 ldx #5
trorc3 trorc3
set_z zp1,$ff set_z zps,$ff
ror zpt ror zpt
tst_z rRORc,fRORc,$ff-fnzc tst_z rRORc,fRORc,$ff-fnzc
dex dex
@ -4254,91 +4258,91 @@ trorc3
next_test next_test
; shifts - absolute ; shifts - absolute
ldx #3 ldx #5
tasl4 tasl4
set_abs zp1,0 set_abs zps,0
asl abst asl abst
tst_abs rASL,fASL,0 tst_abs rASL,fASL,0
dex dex
bpl tasl4 bpl tasl4
ldx #3 ldx #5
tasl5 tasl5
set_abs zp1,$ff set_abs zps,$ff
asl abst asl abst
tst_abs rASL,fASL,$ff-fnzc tst_abs rASL,fASL,$ff-fnzc
dex dex
bpl tasl5 bpl tasl5
ldx #3 ldx #5
tlsr4 tlsr4
set_abs zp1,0 set_abs zps,0
lsr abst lsr abst
tst_abs rLSR,fLSR,0 tst_abs rLSR,fLSR,0
dex dex
bpl tlsr4 bpl tlsr4
ldx #3 ldx #5
tlsr5 tlsr5
set_abs zp1,$ff set_abs zps,$ff
lsr abst lsr abst
tst_abs rLSR,fLSR,$ff-fnzc tst_abs rLSR,fLSR,$ff-fnzc
dex dex
bpl tlsr5 bpl tlsr5
ldx #3 ldx #5
trol4 trol4
set_abs zp1,0 set_abs zps,0
rol abst rol abst
tst_abs rROL,fROL,0 tst_abs rROL,fROL,0
dex dex
bpl trol4 bpl trol4
ldx #3 ldx #5
trol5 trol5
set_abs zp1,$ff-fc set_abs zps,$ff-fc
rol abst rol abst
tst_abs rROL,fROL,$ff-fnzc tst_abs rROL,fROL,$ff-fnzc
dex dex
bpl trol5 bpl trol5
ldx #3 ldx #5
trolc4 trolc4
set_abs zp1,fc set_abs zps,fc
rol abst rol abst
tst_abs rROLc,fROLc,0 tst_abs rROLc,fROLc,0
dex dex
bpl trolc4 bpl trolc4
ldx #3 ldx #5
trolc5 trolc5
set_abs zp1,$ff set_abs zps,$ff
rol abst rol abst
tst_abs rROLc,fROLc,$ff-fnzc tst_abs rROLc,fROLc,$ff-fnzc
dex dex
bpl trolc5 bpl trolc5
ldx #3 ldx #5
tror4 tror4
set_abs zp1,0 set_abs zps,0
ror abst ror abst
tst_abs rROR,fROR,0 tst_abs rROR,fROR,0
dex dex
bpl tror4 bpl tror4
ldx #3 ldx #5
tror5 tror5
set_abs zp1,$ff-fc set_abs zps,$ff-fc
ror abst ror abst
tst_abs rROR,fROR,$ff-fnzc tst_abs rROR,fROR,$ff-fnzc
dex dex
bpl tror5 bpl tror5
ldx #3 ldx #5
trorc4 trorc4
set_abs zp1,fc set_abs zps,fc
ror abst ror abst
tst_abs rRORc,fRORc,0 tst_abs rRORc,fRORc,0
dex dex
bpl trorc4 bpl trorc4
ldx #3 ldx #5
trorc5 trorc5
set_abs zp1,$ff set_abs zps,$ff
ror abst ror abst
tst_abs rRORc,fRORc,$ff-fnzc tst_abs rRORc,fRORc,$ff-fnzc
dex dex
@ -4346,91 +4350,91 @@ trorc5
next_test next_test
; shifts - zp indexed ; shifts - zp indexed
ldx #3 ldx #5
tasl6 tasl6
set_zx zp1,0 set_zx zps,0
asl zpt,x asl zpt,x
tst_zx rASL,fASL,0 tst_zx rASL,fASL,0
dex dex
bpl tasl6 bpl tasl6
ldx #3 ldx #5
tasl7 tasl7
set_zx zp1,$ff set_zx zps,$ff
asl zpt,x asl zpt,x
tst_zx rASL,fASL,$ff-fnzc tst_zx rASL,fASL,$ff-fnzc
dex dex
bpl tasl7 bpl tasl7
ldx #3 ldx #5
tlsr6 tlsr6
set_zx zp1,0 set_zx zps,0
lsr zpt,x lsr zpt,x
tst_zx rLSR,fLSR,0 tst_zx rLSR,fLSR,0
dex dex
bpl tlsr6 bpl tlsr6
ldx #3 ldx #5
tlsr7 tlsr7
set_zx zp1,$ff set_zx zps,$ff
lsr zpt,x lsr zpt,x
tst_zx rLSR,fLSR,$ff-fnzc tst_zx rLSR,fLSR,$ff-fnzc
dex dex
bpl tlsr7 bpl tlsr7
ldx #3 ldx #5
trol6 trol6
set_zx zp1,0 set_zx zps,0
rol zpt,x rol zpt,x
tst_zx rROL,fROL,0 tst_zx rROL,fROL,0
dex dex
bpl trol6 bpl trol6
ldx #3 ldx #5
trol7 trol7
set_zx zp1,$ff-fc set_zx zps,$ff-fc
rol zpt,x rol zpt,x
tst_zx rROL,fROL,$ff-fnzc tst_zx rROL,fROL,$ff-fnzc
dex dex
bpl trol7 bpl trol7
ldx #3 ldx #5
trolc6 trolc6
set_zx zp1,fc set_zx zps,fc
rol zpt,x rol zpt,x
tst_zx rROLc,fROLc,0 tst_zx rROLc,fROLc,0
dex dex
bpl trolc6 bpl trolc6
ldx #3 ldx #5
trolc7 trolc7
set_zx zp1,$ff set_zx zps,$ff
rol zpt,x rol zpt,x
tst_zx rROLc,fROLc,$ff-fnzc tst_zx rROLc,fROLc,$ff-fnzc
dex dex
bpl trolc7 bpl trolc7
ldx #3 ldx #5
tror6 tror6
set_zx zp1,0 set_zx zps,0
ror zpt,x ror zpt,x
tst_zx rROR,fROR,0 tst_zx rROR,fROR,0
dex dex
bpl tror6 bpl tror6
ldx #3 ldx #5
tror7 tror7
set_zx zp1,$ff-fc set_zx zps,$ff-fc
ror zpt,x ror zpt,x
tst_zx rROR,fROR,$ff-fnzc tst_zx rROR,fROR,$ff-fnzc
dex dex
bpl tror7 bpl tror7
ldx #3 ldx #5
trorc6 trorc6
set_zx zp1,fc set_zx zps,fc
ror zpt,x ror zpt,x
tst_zx rRORc,fRORc,0 tst_zx rRORc,fRORc,0
dex dex
bpl trorc6 bpl trorc6
ldx #3 ldx #5
trorc7 trorc7
set_zx zp1,$ff set_zx zps,$ff
ror zpt,x ror zpt,x
tst_zx rRORc,fRORc,$ff-fnzc tst_zx rRORc,fRORc,$ff-fnzc
dex dex
@ -4438,91 +4442,91 @@ trorc7
next_test next_test
; shifts - abs indexed ; shifts - abs indexed
ldx #3 ldx #5
tasl8 tasl8
set_absx zp1,0 set_absx zps,0
asl abst,x asl abst,x
tst_absx rASL,fASL,0 tst_absx rASL,fASL,0
dex dex
bpl tasl8 bpl tasl8
ldx #3 ldx #5
tasl9 tasl9
set_absx zp1,$ff set_absx zps,$ff
asl abst,x asl abst,x
tst_absx rASL,fASL,$ff-fnzc tst_absx rASL,fASL,$ff-fnzc
dex dex
bpl tasl9 bpl tasl9
ldx #3 ldx #5
tlsr8 tlsr8
set_absx zp1,0 set_absx zps,0
lsr abst,x lsr abst,x
tst_absx rLSR,fLSR,0 tst_absx rLSR,fLSR,0
dex dex
bpl tlsr8 bpl tlsr8
ldx #3 ldx #5
tlsr9 tlsr9
set_absx zp1,$ff set_absx zps,$ff
lsr abst,x lsr abst,x
tst_absx rLSR,fLSR,$ff-fnzc tst_absx rLSR,fLSR,$ff-fnzc
dex dex
bpl tlsr9 bpl tlsr9
ldx #3 ldx #5
trol8 trol8
set_absx zp1,0 set_absx zps,0
rol abst,x rol abst,x
tst_absx rROL,fROL,0 tst_absx rROL,fROL,0
dex dex
bpl trol8 bpl trol8
ldx #3 ldx #5
trol9 trol9
set_absx zp1,$ff-fc set_absx zps,$ff-fc
rol abst,x rol abst,x
tst_absx rROL,fROL,$ff-fnzc tst_absx rROL,fROL,$ff-fnzc
dex dex
bpl trol9 bpl trol9
ldx #3 ldx #5
trolc8 trolc8
set_absx zp1,fc set_absx zps,fc
rol abst,x rol abst,x
tst_absx rROLc,fROLc,0 tst_absx rROLc,fROLc,0
dex dex
bpl trolc8 bpl trolc8
ldx #3 ldx #5
trolc9 trolc9
set_absx zp1,$ff set_absx zps,$ff
rol abst,x rol abst,x
tst_absx rROLc,fROLc,$ff-fnzc tst_absx rROLc,fROLc,$ff-fnzc
dex dex
bpl trolc9 bpl trolc9
ldx #3 ldx #5
tror8 tror8
set_absx zp1,0 set_absx zps,0
ror abst,x ror abst,x
tst_absx rROR,fROR,0 tst_absx rROR,fROR,0
dex dex
bpl tror8 bpl tror8
ldx #3 ldx #5
tror9 tror9
set_absx zp1,$ff-fc set_absx zps,$ff-fc
ror abst,x ror abst,x
tst_absx rROR,fROR,$ff-fnzc tst_absx rROR,fROR,$ff-fnzc
dex dex
bpl tror9 bpl tror9
ldx #3 ldx #5
trorc8 trorc8
set_absx zp1,fc set_absx zps,fc
ror abst,x ror abst,x
tst_absx rRORc,fRORc,0 tst_absx rRORc,fRORc,0
dex dex
bpl trorc8 bpl trorc8
ldx #3 ldx #5
trorc9 trorc9
set_absx zp1,$ff set_absx zps,$ff
ror abst,x ror abst,x
tst_absx rRORc,fRORc,$ff-fnzc tst_absx rRORc,fRORc,$ff-fnzc
dex dex
@ -5997,6 +6001,7 @@ break2 ;BRK pass 2
;copy of data to initialize BSS segment ;copy of data to initialize BSS segment
if load_data_direct != 1 if load_data_direct != 1
zp_init zp_init
zps_ db $80,1 ;additional shift pattern to test zero result & flag
zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
zp7f_ db $7f ;test pattern for compare zp7f_ db $7f ;test pattern for compare
;logical zeropage operands ;logical zeropage operands
@ -6048,23 +6053,24 @@ ex_adc_ adc #0 ;execute immediate opcodes
rts rts
ex_sbc_ sbc #0 ;execute immediate opcodes ex_sbc_ sbc #0 ;execute immediate opcodes
rts rts
;zps db $80,1 ;additional shift patterns test zero result & flag
abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
abs7f_ db $7f ;test pattern for compare abs7f_ db $7f ;test pattern for compare
;loads ;loads
fLDx_ db fn,fn,0,fz ;expected flags for load fLDx_ db fn,fn,0,fz ;expected flags for load
;shifts ;shifts
rASL_ ;expected result ASL & ROL -carry rASL_ ;expected result ASL & ROL -carry
rROL_ db $86,$04,$82,0 ; " rROL_ db 0,2,$86,$04,$82,0
rROLc_ db $87,$05,$83,1 ;expected result ROL +carry rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry
rLSR_ ;expected result LSR & ROR -carry rLSR_ ;expected result LSR & ROR -carry
rROR_ db $61,$41,$20,0 ; " rROR_ db $40,0,$61,$41,$20,0
rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
fASL_ ;expected flags for shifts fASL_ ;expected flags for shifts
fROL_ db fnc,fc,fn,fz ;no carry in fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in
fROLc_ db fnc,fc,fn,0 ;carry in fROLc_ db fc,0,fnc,fc,fn,0 ;carry in
fLSR_ fLSR_
fROR_ db fc,0,fc,fz ;no carry in fROR_ db 0,fzc,fc,0,fc,fz ;no carry in
fRORc_ db fnc,fn,fnc,fn ;carry in fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in
;increments (decrements) ;increments (decrements)
rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC

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readme.txt
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@ -10,14 +10,18 @@ The 6502_interrupt_test.a65 is a simple test to check the interrupt system
of both processors. A feedback register is required to inject IRQ and NMI of both processors. A feedback register is required to inject IRQ and NMI
requests. requests.
The 6502_decimal_test.a65 is Bruce Clark's code to accurately test decimal mode
of the various 6502 cores (6502, 65c02 & 65816 in 8-bit mode) with added
configuration options (invalid bcd or not, which flags to ignore).
Detailed information about how to configure, assemble and run the tests is Detailed information about how to configure, assemble and run the tests is
included in each source file. included in each source file.
The tests have primarily been written to test my own ATMega16 6502 emulator The assembler used is no longer available on the author's website. as65_142.zip
project. You can find it here: http://2m5.de/6502_Emu/index.htm is now included in this repository.
A discussion about the tests can be found here: And no, I will not switch to another assembler. However, GitHub user amb5l has
http://forum.6502.org/viewtopic.php?f=2&t=2241 a CA65 compatible version in his repository.
Good luck debugging your emulator, simulator, fpga core, discrete Good luck debugging your emulator, simulator, fpga core, discrete
logic implementation or whatever you have! logic implementation or whatever you have!