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fixed shifts not testing zero result and flag when last 1-bit is shifted out

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Klaus2m5 2020-01-05 14:10:38 +01:00
parent fe99e56162
commit 7954e2dbb4
3 changed files with 185 additions and 175 deletions
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348
6502_functional_test.a65
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@ -1,7 +1,7 @@
;
; 6 5 0 2 F U N C T I O N A L T E S T
;
; Copyright (C) 2012-2015 Klaus Dormann
; Copyright (C) 2012-2020 Klaus Dormann
;
; This program is free software: you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
@ -21,10 +21,11 @@
; addressing modes with focus on propper setting of the processor status
; register bits.
;
; version 04-dec-2017
; version 05-jan-2020
; contact info at http://2m5.de or email K@2m5.de
;
; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
; assembled with AS65 written by Frank A. Kingswood
; The assembler as65_142.zip can be obtained from my GitHub repository
; command line switches: -l -m -s2 -w -h0
; | | | | no page headers in listing
; | | | wide listing (133 char/col)
@ -76,7 +77,8 @@
; 04-dec-2017 fixed BRK only tested with interrupts enabled
; added option to skip the remainder of a failing test
; in report.i65
; 05-jan-2020 fixed shifts not testing zero result and flag when last 1-bit
; is shifted out
; C O N F I G U R A T I O N
@ -96,17 +98,17 @@ load_data_direct = 1
I_flag = 3
;configure memory - try to stay away from memory used by the system
;zero_page memory start address, $50 (80) consecutive Bytes required
;zero_page memory start address, $52 (82) consecutive Bytes required
; add 2 if I_flag = 2
zero_page = $a
;data_segment memory start address, $6A (106) consecutive Bytes required
;data_segment memory start address, $7B (123) consecutive Bytes required
data_segment = $200
if (data_segment & $ff) != 0
ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
endif
;code_segment memory start address, 13kB of consecutive space required
;code_segment memory start address, 13.1kB of consecutive space required
; add 2.5 kB if I_flag = 2
code_segment = $400
@ -621,7 +623,7 @@ irq_x ds 1 ;x register
flag_I_on ds 1 ;or mask to load flags
flag_I_off ds 1 ;and mask to load flags
endif
zpt ;5 bytes store/modify test area
zpt ;6 bytes store/modify test area
;add/subtract operand generation and result/flag prediction
adfc ds 1 ;carry flag before op
ad1 ds 1 ;operand 1 - accumulator
@ -631,6 +633,7 @@ adrh ds 1 ;expected result bit 8 (carry)
adrf ds 1 ;expected flags NV0000ZC (only binary mode)
sb2 ds 1 ;operand 2 complemented for subtract
zp_bss
zps db $80,1 ;additional shift pattern to test zero result & flag
zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
zp7f db $7f ;test pattern for compare
;logical zeropage operands
@ -672,10 +675,10 @@ zp_bss_end
test_case ds 1 ;current test number
ram_chksm ds 2 ;checksum for RAM integrity test
;add/subtract operand copy - abs tests write area
abst ;5 bytes store/modify test area
abst ;6 bytes store/modify test area
ada2 ds 1 ;operand 2
sba2 ds 1 ;operand 2 complemented for subtract
ds 3 ;fill remaining bytes
ds 4 ;fill remaining bytes
data_bss
if load_data_direct = 1
ex_andi and #0 ;execute immediate opcodes
@ -695,34 +698,35 @@ ex_orai ds 3
ex_adci ds 3
ex_sbci ds 3
endif
;zps db $80,1 ;additional shift patterns test zero result & flag
abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
abs7f db $7f ;test pattern for compare
;loads
fLDx db fn,fn,0,fz ;expected flags for load
fLDx db fn,fn,0,fz ;expected flags for load
;shifts
rASL ;expected result ASL & ROL -carry
rROL db $86,$04,$82,0 ; "
rROLc db $87,$05,$83,1 ;expected result ROL +carry
rLSR ;expected result LSR & ROR -carry
rROR db $61,$41,$20,0 ; "
rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry
fASL ;expected flags for shifts
fROL db fnc,fc,fn,fz ;no carry in
fROLc db fnc,fc,fn,0 ;carry in
fLSR
fROR db fc,0,fc,fz ;no carry in
fRORc db fnc,fn,fnc,fn ;carry in
rASL ;expected result ASL & ROL -carry
rROL db 0,2,$86,$04,$82,0
rROLc db 1,3,$87,$05,$83,1 ;expected result ROL +carry
rLSR ;expected result LSR & ROR -carry
rROR db $40,0,$61,$41,$20,0
rRORc db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
fASL ;expected flags for shifts
fROL db fzc,0,fnc,fc,fn,fz ;no carry in
fROLc db fc,0,fnc,fc,fn,0 ;carry in
fLSR
fROR db 0,fzc,fc,0,fc,fz ;no carry in
fRORc db fn,fnc,fnc,fn,fnc,fn ;carry in
;increments (decrements)
rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC
rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC
;logical memory operand
absOR db 0,$1f,$71,$80 ;test pattern for OR
absAN db $0f,$ff,$7f,$80 ;test pattern for AND
absEO db $ff,$0f,$8f,$8f ;test pattern for EOR
absOR db 0,$1f,$71,$80 ;test pattern for OR
absAN db $0f,$ff,$7f,$80 ;test pattern for AND
absEO db $ff,$0f,$8f,$8f ;test pattern for EOR
;logical accu operand
absORa db 0,$f1,$1f,0 ;test pattern for OR
absANa db $f0,$ff,$ff,$ff ;test pattern for AND
absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR
absORa db 0,$f1,$1f,0 ;test pattern for OR
absANa db $f0,$ff,$ff,$ff ;test pattern for AND
absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR
;logical results
absrlo db 0,$ff,$7f,$80
absflo db fz,fn,0,fn
@ -4070,91 +4074,91 @@ tstay6 lda abst,y
; testing shifts - ASL LSR ROL ROR all addressing modes
; shifts - accumulator
ldx #3
ldx #5
tasl
set_ax zp1,0
set_ax zps,0
asl a
tst_ax rASL,fASL,0
dex
bpl tasl
ldx #3
ldx #5
tasl1
set_ax zp1,$ff
set_ax zps,$ff
asl a
tst_ax rASL,fASL,$ff-fnzc
dex
bpl tasl1
ldx #3
ldx #5
tlsr
set_ax zp1,0
set_ax zps,0
lsr a
tst_ax rLSR,fLSR,0
dex
bpl tlsr
ldx #3
ldx #5
tlsr1
set_ax zp1,$ff
set_ax zps,$ff
lsr a
tst_ax rLSR,fLSR,$ff-fnzc
dex
bpl tlsr1
ldx #3
ldx #5
trol
set_ax zp1,0
set_ax zps,0
rol a
tst_ax rROL,fROL,0
dex
bpl trol
ldx #3
ldx #5
trol1
set_ax zp1,$ff-fc
set_ax zps,$ff-fc
rol a
tst_ax rROL,fROL,$ff-fnzc
dex
bpl trol1
ldx #3
ldx #5
trolc
set_ax zp1,fc
set_ax zps,fc
rol a
tst_ax rROLc,fROLc,0
dex
bpl trolc
ldx #3
ldx #5
trolc1
set_ax zp1,$ff
set_ax zps,$ff
rol a
tst_ax rROLc,fROLc,$ff-fnzc
dex
bpl trolc1
ldx #3
ldx #5
tror
set_ax zp1,0
set_ax zps,0
ror a
tst_ax rROR,fROR,0
dex
bpl tror
ldx #3
ldx #5
tror1
set_ax zp1,$ff-fc
set_ax zps,$ff-fc
ror a
tst_ax rROR,fROR,$ff-fnzc
dex
bpl tror1
ldx #3
ldx #5
trorc
set_ax zp1,fc
set_ax zps,fc
ror a
tst_ax rRORc,fRORc,0
dex
bpl trorc
ldx #3
ldx #5
trorc1
set_ax zp1,$ff
set_ax zps,$ff
ror a
tst_ax rRORc,fRORc,$ff-fnzc
dex
@ -4162,91 +4166,91 @@ trorc1
next_test
; shifts - zeropage
ldx #3
ldx #5
tasl2
set_z zp1,0
set_z zps,0
asl zpt
tst_z rASL,fASL,0
dex
bpl tasl2
ldx #3
ldx #5
tasl3
set_z zp1,$ff
set_z zps,$ff
asl zpt
tst_z rASL,fASL,$ff-fnzc
dex
bpl tasl3
ldx #3
ldx #5
tlsr2
set_z zp1,0
set_z zps,0
lsr zpt
tst_z rLSR,fLSR,0
dex
bpl tlsr2
ldx #3
ldx #5
tlsr3
set_z zp1,$ff
set_z zps,$ff
lsr zpt
tst_z rLSR,fLSR,$ff-fnzc
dex
bpl tlsr3
ldx #3
ldx #5
trol2
set_z zp1,0
set_z zps,0
rol zpt
tst_z rROL,fROL,0
dex
bpl trol2
ldx #3
ldx #5
trol3
set_z zp1,$ff-fc
set_z zps,$ff-fc
rol zpt
tst_z rROL,fROL,$ff-fnzc
dex
bpl trol3
ldx #3
ldx #5
trolc2
set_z zp1,fc
set_z zps,fc
rol zpt
tst_z rROLc,fROLc,0
dex
bpl trolc2
ldx #3
ldx #5
trolc3
set_z zp1,$ff
set_z zps,$ff
rol zpt
tst_z rROLc,fROLc,$ff-fnzc
dex
bpl trolc3
ldx #3
ldx #5
tror2
set_z zp1,0
set_z zps,0
ror zpt
tst_z rROR,fROR,0
dex
bpl tror2
ldx #3
ldx #5
tror3
set_z zp1,$ff-fc
set_z zps,$ff-fc
ror zpt
tst_z rROR,fROR,$ff-fnzc
dex
bpl tror3
ldx #3
ldx #5
trorc2
set_z zp1,fc
set_z zps,fc
ror zpt
tst_z rRORc,fRORc,0
dex
bpl trorc2
ldx #3
ldx #5
trorc3
set_z zp1,$ff
set_z zps,$ff
ror zpt
tst_z rRORc,fRORc,$ff-fnzc
dex
@ -4254,91 +4258,91 @@ trorc3
next_test
; shifts - absolute
ldx #3
ldx #5
tasl4
set_abs zp1,0
set_abs zps,0
asl abst
tst_abs rASL,fASL,0
dex
bpl tasl4
ldx #3
ldx #5
tasl5
set_abs zp1,$ff
set_abs zps,$ff
asl abst
tst_abs rASL,fASL,$ff-fnzc
dex
bpl tasl5
ldx #3
ldx #5
tlsr4
set_abs zp1,0
set_abs zps,0
lsr abst
tst_abs rLSR,fLSR,0
dex
bpl tlsr4
ldx #3
ldx #5
tlsr5
set_abs zp1,$ff
set_abs zps,$ff
lsr abst
tst_abs rLSR,fLSR,$ff-fnzc
dex
bpl tlsr5
ldx #3
ldx #5
trol4
set_abs zp1,0
set_abs zps,0
rol abst
tst_abs rROL,fROL,0
dex
bpl trol4
ldx #3
ldx #5
trol5
set_abs zp1,$ff-fc
set_abs zps,$ff-fc
rol abst
tst_abs rROL,fROL,$ff-fnzc
dex
bpl trol5
ldx #3
ldx #5
trolc4
set_abs zp1,fc
set_abs zps,fc
rol abst
tst_abs rROLc,fROLc,0
dex
bpl trolc4
ldx #3
ldx #5
trolc5
set_abs zp1,$ff
set_abs zps,$ff
rol abst
tst_abs rROLc,fROLc,$ff-fnzc
dex
bpl trolc5
ldx #3
ldx #5
tror4
set_abs zp1,0
set_abs zps,0
ror abst
tst_abs rROR,fROR,0
dex
bpl tror4
ldx #3
ldx #5
tror5
set_abs zp1,$ff-fc
set_abs zps,$ff-fc
ror abst
tst_abs rROR,fROR,$ff-fnzc
dex
bpl tror5
ldx #3
ldx #5
trorc4
set_abs zp1,fc
set_abs zps,fc
ror abst
tst_abs rRORc,fRORc,0
dex
bpl trorc4
ldx #3
ldx #5
trorc5
set_abs zp1,$ff
set_abs zps,$ff
ror abst
tst_abs rRORc,fRORc,$ff-fnzc
dex
@ -4346,91 +4350,91 @@ trorc5
next_test
; shifts - zp indexed
ldx #3
ldx #5
tasl6
set_zx zp1,0
set_zx zps,0
asl zpt,x
tst_zx rASL,fASL,0
dex
bpl tasl6
ldx #3
ldx #5
tasl7
set_zx zp1,$ff
set_zx zps,$ff
asl zpt,x
tst_zx rASL,fASL,$ff-fnzc
dex
bpl tasl7
ldx #3
ldx #5
tlsr6
set_zx zp1,0
set_zx zps,0
lsr zpt,x
tst_zx rLSR,fLSR,0
dex
bpl tlsr6
ldx #3
ldx #5
tlsr7
set_zx zp1,$ff
set_zx zps,$ff
lsr zpt,x
tst_zx rLSR,fLSR,$ff-fnzc
dex
bpl tlsr7
ldx #3
ldx #5
trol6
set_zx zp1,0
set_zx zps,0
rol zpt,x
tst_zx rROL,fROL,0
dex
bpl trol6
ldx #3
ldx #5
trol7
set_zx zp1,$ff-fc
set_zx zps,$ff-fc
rol zpt,x
tst_zx rROL,fROL,$ff-fnzc
dex
bpl trol7
ldx #3
ldx #5
trolc6
set_zx zp1,fc
set_zx zps,fc
rol zpt,x
tst_zx rROLc,fROLc,0
dex
bpl trolc6
ldx #3
ldx #5
trolc7
set_zx zp1,$ff
set_zx zps,$ff
rol zpt,x
tst_zx rROLc,fROLc,$ff-fnzc
dex
bpl trolc7
ldx #3
ldx #5
tror6
set_zx zp1,0
set_zx zps,0
ror zpt,x
tst_zx rROR,fROR,0
dex
bpl tror6
ldx #3
ldx #5
tror7
set_zx zp1,$ff-fc
set_zx zps,$ff-fc
ror zpt,x
tst_zx rROR,fROR,$ff-fnzc
dex
bpl tror7
ldx #3
ldx #5
trorc6
set_zx zp1,fc
set_zx zps,fc
ror zpt,x
tst_zx rRORc,fRORc,0
dex
bpl trorc6
ldx #3
ldx #5
trorc7
set_zx zp1,$ff
set_zx zps,$ff
ror zpt,x
tst_zx rRORc,fRORc,$ff-fnzc
dex
@ -4438,91 +4442,91 @@ trorc7
next_test
; shifts - abs indexed
ldx #3
ldx #5
tasl8
set_absx zp1,0
set_absx zps,0
asl abst,x
tst_absx rASL,fASL,0
dex
bpl tasl8
ldx #3
ldx #5
tasl9
set_absx zp1,$ff
set_absx zps,$ff
asl abst,x
tst_absx rASL,fASL,$ff-fnzc
dex
bpl tasl9
ldx #3
ldx #5
tlsr8
set_absx zp1,0
set_absx zps,0
lsr abst,x
tst_absx rLSR,fLSR,0
dex
bpl tlsr8
ldx #3
ldx #5
tlsr9
set_absx zp1,$ff
set_absx zps,$ff
lsr abst,x
tst_absx rLSR,fLSR,$ff-fnzc
dex
bpl tlsr9
ldx #3
ldx #5
trol8
set_absx zp1,0
set_absx zps,0
rol abst,x
tst_absx rROL,fROL,0
dex
bpl trol8
ldx #3
ldx #5
trol9
set_absx zp1,$ff-fc
set_absx zps,$ff-fc
rol abst,x
tst_absx rROL,fROL,$ff-fnzc
dex
bpl trol9
ldx #3
ldx #5
trolc8
set_absx zp1,fc
set_absx zps,fc
rol abst,x
tst_absx rROLc,fROLc,0
dex
bpl trolc8
ldx #3
ldx #5
trolc9
set_absx zp1,$ff
set_absx zps,$ff
rol abst,x
tst_absx rROLc,fROLc,$ff-fnzc
dex
bpl trolc9
ldx #3
ldx #5
tror8
set_absx zp1,0
set_absx zps,0
ror abst,x
tst_absx rROR,fROR,0
dex
bpl tror8
ldx #3
ldx #5
tror9
set_absx zp1,$ff-fc
set_absx zps,$ff-fc
ror abst,x
tst_absx rROR,fROR,$ff-fnzc
dex
bpl tror9
ldx #3
ldx #5
trorc8
set_absx zp1,fc
set_absx zps,fc
ror abst,x
tst_absx rRORc,fRORc,0
dex
bpl trorc8
ldx #3
ldx #5
trorc9
set_absx zp1,$ff
set_absx zps,$ff
ror abst,x
tst_absx rRORc,fRORc,$ff-fnzc
dex
@ -5997,6 +6001,7 @@ break2 ;BRK pass 2
;copy of data to initialize BSS segment
if load_data_direct != 1
zp_init
zps_ db $80,1 ;additional shift pattern to test zero result & flag
zp1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
zp7f_ db $7f ;test pattern for compare
;logical zeropage operands
@ -6048,34 +6053,35 @@ ex_adc_ adc #0 ;execute immediate opcodes
rts
ex_sbc_ sbc #0 ;execute immediate opcodes
rts
;zps db $80,1 ;additional shift patterns test zero result & flag
abs1_ db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
abs7f_ db $7f ;test pattern for compare
;loads
fLDx_ db fn,fn,0,fz ;expected flags for load
fLDx_ db fn,fn,0,fz ;expected flags for load
;shifts
rASL_ ;expected result ASL & ROL -carry
rROL_ db $86,$04,$82,0 ; "
rROLc_ db $87,$05,$83,1 ;expected result ROL +carry
rLSR_ ;expected result LSR & ROR -carry
rROR_ db $61,$41,$20,0 ; "
rRORc_ db $e1,$c1,$a0,$80 ;expected result ROR +carry
fASL_ ;expected flags for shifts
fROL_ db fnc,fc,fn,fz ;no carry in
fROLc_ db fnc,fc,fn,0 ;carry in
rASL_ ;expected result ASL & ROL -carry
rROL_ db 0,2,$86,$04,$82,0
rROLc_ db 1,3,$87,$05,$83,1 ;expected result ROL +carry
rLSR_ ;expected result LSR & ROR -carry
rROR_ db $40,0,$61,$41,$20,0
rRORc_ db $c0,$80,$e1,$c1,$a0,$80 ;expected result ROR +carry
fASL_ ;expected flags for shifts
fROL_ db fzc,0,fnc,fc,fn,fz ;no carry in
fROLc_ db fc,0,fnc,fc,fn,0 ;carry in
fLSR_
fROR_ db fc,0,fc,fz ;no carry in
fRORc_ db fnc,fn,fnc,fn ;carry in
fROR_ db 0,fzc,fc,0,fc,fz ;no carry in
fRORc_ db fn,fnc,fnc,fn,fnc,fn ;carry in
;increments (decrements)
rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC
rINC_ db $7f,$80,$ff,0,1 ;expected result for INC/DEC
fINC_ db 0,fn,fn,fz,0 ;expected flags for INC/DEC
;logical memory operand
absOR_ db 0,$1f,$71,$80 ;test pattern for OR
absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND
absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR
absOR_ db 0,$1f,$71,$80 ;test pattern for OR
absAN_ db $0f,$ff,$7f,$80 ;test pattern for AND
absEO_ db $ff,$0f,$8f,$8f ;test pattern for EOR
;logical accu operand
absORa_ db 0,$f1,$1f,0 ;test pattern for OR
absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND
absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR
absORa_ db 0,$f1,$1f,0 ;test pattern for OR
absANa_ db $f0,$ff,$ff,$ff ;test pattern for AND
absEOa_ db $ff,$f0,$f0,$0f ;test pattern for EOR
;logical results
absrlo_ db 0,$ff,$7f,$80
absflo_ db fz,fn,0,fn

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as65_142.zip Normal file
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12
readme.txt
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@ -10,14 +10,18 @@ The 6502_interrupt_test.a65 is a simple test to check the interrupt system
of both processors. A feedback register is required to inject IRQ and NMI
requests.
The 6502_decimal_test.a65 is Bruce Clark's code to accurately test decimal mode
of the various 6502 cores (6502, 65c02 & 65816 in 8-bit mode) with added
configuration options (invalid bcd or not, which flags to ignore).
Detailed information about how to configure, assemble and run the tests is
included in each source file.
The tests have primarily been written to test my own ATMega16 6502 emulator
project. You can find it here: http://2m5.de/6502_Emu/index.htm
The assembler used is no longer available on the author's website. as65_142.zip
is now included in this repository.
A discussion about the tests can be found here:
http://forum.6502.org/viewtopic.php?f=2&t=2241
And no, I will not switch to another assembler. However, GitHub user amb5l has
a CA65 compatible version in his repository.
Good luck debugging your emulator, simulator, fpga core, discrete
logic implementation or whatever you have!