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5801 lines
136 KiB
Plaintext
5801 lines
136 KiB
Plaintext
;
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; 6 5 0 2 F U N C T I O N A L T E S T
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;
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; Copyright (C) 2012-2013 Klaus Dormann
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;
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; This program is free software: you can redistribute it and/or modify
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; it under the terms of the GNU General Public License as published by
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; the Free Software Foundation, either version 3 of the License, or
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; (at your option) any later version.
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;
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; This program is distributed in the hope that it will be useful,
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; but WITHOUT ANY WARRANTY; without even the implied warranty of
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; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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; GNU General Public License for more details.
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;
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; You should have received a copy of the GNU General Public License
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; along with this program. If not, see <http://www.gnu.org/licenses/>.
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; This program is designed to test all opcodes of a 6502 emulator using all
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; addressing modes with focus on propper setting of the processor status
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; register bits.
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;
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; version 16-aug-2013
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; contact info at http://2m5.de or email K@2m5.de
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;
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; assembled with AS65 from http://www.kingswood-consulting.co.uk/assemblers/
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; command line switches: -l -m -s2 -w -h0
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; | | | | no page headers in listing
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; | | | wide listing (133 char/col)
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; | | write intel hex file instead of binary
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; | expand macros in listing
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; generate pass2 listing
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;
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; No IO - should be run from a monitor with access to registers.
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; To run load intel hex image with a load command, than alter PC to 400 hex
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; (code_segment) and enter a go command.
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; Loop on program counter determines error or successful completion of test.
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; Check listing for relevant traps (jump/branch *).
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; Please note that in early tests some instructions will have to be used before
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; they are actually tested!
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;
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; RESET, NMI or IRQ should not occur and will be trapped if vectors are enabled.
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; Tests documented behavior of the original NMOS 6502 only! No unofficial
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; opcodes. Additional opcodes of newer versions of the CPU (65C02, 65816) will
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; not be tested. Decimal ops will only be tested with valid BCD operands and
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; N V Z flags will be ignored.
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;
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; Debugging hints:
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; Most of the code is written sequentially. if you hit a trap, check the
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; immediately preceeding code for the instruction to be tested. Results are
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; tested first, flags are checked second by pushing them onto the stack and
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; pulling them to the accumulator after the result was checked. The "real"
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; flags are no longer valid for the tested instruction at this time!
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; If the tested instruction was indexed, the relevant index (X or Y) must
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; also be checked. Opposed to the flags, X and Y registers are still valid.
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;
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; versions:
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; 28-jul-2012 1st version distributed for testing
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; 29-jul-2012 fixed references to location 0, now #0
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; added license - GPLv3
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; 30-jul-2012 added configuration options
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; 01-aug-2012 added trap macro to allow user to change error handling
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; 01-dec-2012 fixed trap in branch field must be a branch
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; 02-mar-2013 fixed PLA flags not tested
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; 19-jul-2013 allowed ROM vectors to be loaded when load_data_direct = 0
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; added test sequence check to detect if tests jump their fence
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; 23-jul-2013 added RAM integrity check option
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; 16-aug-2013 added error report to standard output option
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; C O N F I G U R A T I O N
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;ROM_vectors writable (0=no, 1=yes)
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;if ROM vectors can not be used interrupts will not be trapped
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;as a consequence BRK can not be tested but will be emulated to test RTI
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ROM_vectors = 1
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;load_data_direct (0=move from code segment, 1=load directly)
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;loading directly is preferred but may not be supported by your platform
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;0 produces only consecutive object code, 1 is not suitable for a binary image
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load_data_direct = 1
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;I_flag behavior (0=force enabled, 1=force disabled, 2=prohibit change, 3=allow
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;change) 2 requires extra code and is not recommended. SEI & CLI can only be
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;tested if you allow changing the interrupt status (I_flag = 3)
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I_flag = 3
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;configure memory - try to stay away from memory used by the system
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;zero_page memory start address, $50 (80) consecutive Bytes required
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; add 2 if I_flag = 2
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zero_page = $a
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;data_segment memory start address, $5B (91) consecutive Bytes required
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data_segment = $200
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if (data_segment & $ff) != 0
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ERROR ERROR ERROR low byte of data_segment MUST be $00 !!
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endif
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;code_segment memory start address, 13kB of consecutive space required
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; add 2.5 kB if I_flag = 2
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;parts of the code are self modifying and must reside in RAM
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code_segment = $400
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;report errors through I/O channel (0=use standard self trap loops, 1=include
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;report.i65 as I/O channel, add 3.5 kB)
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report = 0
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;RAM integrity test option. Checks for undesired RAM writes.
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;set lowest non RAM or RAM mirror address page (-1=disable, 0=64k, $40=16k)
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;leave disabled if a monitor, OS or background interrupt is allowed to alter RAM
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ram_top = -1
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noopt ;do not take shortcuts
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;macros for error & success traps to allow user modification
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;example:
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;trap macro
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; jsr my_error_handler
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; endm
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;trap_eq macro
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; bne skip\?
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; trap ;failed equal (zero)
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;skip\?
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; endm
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;
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; my_error_handler should pop the calling address from the stack and report it.
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; putting larger portions of code (more than 3 bytes) inside the trap macro
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; may lead to branch range problems for some tests.
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if report = 0
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trap macro
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jmp * ;failed anyway
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endm
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trap_eq macro
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beq * ;failed equal (zero)
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endm
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trap_ne macro
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bne * ;failed not equal (non zero)
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endm
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trap_cs macro
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bcs * ;failed carry set
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endm
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trap_cc macro
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bcc * ;failed carry clear
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endm
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trap_mi macro
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bmi * ;failed minus (bit 7 set)
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endm
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trap_pl macro
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bpl * ;failed plus (bit 7 clear)
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endm
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trap_vs macro
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bvs * ;failed overflow set
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endm
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trap_vc macro
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bvc * ;failed overflow clear
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jmp * ;test passed, no errors
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endm
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endif
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if report = 1
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trap macro
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jsr report_error
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endm
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trap_eq macro
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bne skip\?
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trap ;failed equal (zero)
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skip\?
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endm
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trap_ne macro
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beq skip\?
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trap ;failed not equal (non zero)
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skip\?
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endm
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trap_cs macro
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bcc skip\?
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trap ;failed carry set
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skip\?
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endm
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trap_cc macro
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bcs skip\?
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trap ;failed carry clear
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skip\?
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endm
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trap_mi macro
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bpl skip\?
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trap ;failed minus (bit 7 set)
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skip\?
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endm
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trap_pl macro
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bmi skip\?
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trap ;failed plus (bit 7 clear)
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skip\?
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endm
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trap_vs macro
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bvc skip\?
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trap ;failed overflow set
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skip\?
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endm
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trap_vc macro
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bvs skip\?
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trap ;failed overflow clear
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skip\?
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endm
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; please observe that during the test the stack gets invalidated
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; therefore a RTS inside the success macro is not possible
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success macro
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jsr report_success
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endm
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endif
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carry equ %00000001 ;flag bits in status
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zero equ %00000010
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intdis equ %00000100
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decmode equ %00001000
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break equ %00010000
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reserv equ %00100000
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overfl equ %01000000
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minus equ %10000000
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fc equ carry
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fz equ zero
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fzc equ carry+zero
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fv equ overfl
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fvz equ overfl+zero
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fn equ minus
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fnc equ minus+carry
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fnz equ minus+zero
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fnzc equ minus+zero+carry
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fnv equ minus+overfl
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fao equ break+reserv ;bits always on after PHP, BRK
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fai equ fao+intdis ;+ forced interrupt disable
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m8 equ $ff ;8 bit mask
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m8i equ $ff&~intdis ;8 bit mask - interrupt disable
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;macros to allow masking of status bits.
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;masking of interrupt enable/disable on load and compare
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;masking of always on bits after PHP or BRK (unused & break) on compare
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if I_flag = 0
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load_flag macro
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lda #\1&m8i ;force enable interrupts (mask I)
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endm
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cmp_flag macro
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cmp #(\1|fao)&m8i ;I_flag is always enabled + always on bits
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endm
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eor_flag macro
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eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits
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endm
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endif
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if I_flag = 1
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load_flag macro
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lda #\1|intdis ;force disable interrupts
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endm
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cmp_flag macro
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cmp #(\1|fai)&m8 ;I_flag is always disabled + always on bits
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endm
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eor_flag macro
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eor #(\1|fai) ;invert expected flags + always on bits + I
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endm
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endif
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if I_flag = 2
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load_flag macro
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lda #\1
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ora flag_I_on ;restore I-flag
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and flag_I_off
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endm
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cmp_flag macro
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eor flag_I_on ;I_flag is never changed
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cmp #(\1|fao)&m8i ;expected flags + always on bits, mask I
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endm
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eor_flag macro
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eor flag_I_on ;I_flag is never changed
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eor #(\1&m8i|fao) ;mask I, invert expected flags + always on bits
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endm
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endif
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if I_flag = 3
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load_flag macro
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lda #\1 ;allow test to change I-flag (no mask)
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endm
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cmp_flag macro
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cmp #(\1|fao)&m8 ;expected flags + always on bits
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endm
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eor_flag macro
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eor #\1|fao ;invert expected flags + always on bits
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endm
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endif
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;macros to set (register|memory|zeropage) & status
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set_stat macro ;setting flags in the processor status register
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load_flag \1
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pha ;use stack to load status
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plp
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endm
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set_a macro ;precharging accu & status
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load_flag \2
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pha ;use stack to load status
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lda #\1 ;precharge accu
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plp
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endm
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set_x macro ;precharging index & status
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load_flag \2
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pha ;use stack to load status
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ldx #\1 ;precharge index x
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plp
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endm
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set_y macro ;precharging index & status
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load_flag \2
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pha ;use stack to load status
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ldy #\1 ;precharge index y
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plp
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endm
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set_ax macro ;precharging indexed accu & immediate status
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load_flag \2
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pha ;use stack to load status
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lda \1,x ;precharge accu
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plp
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endm
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set_ay macro ;precharging indexed accu & immediate status
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load_flag \2
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pha ;use stack to load status
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lda \1,y ;precharge accu
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plp
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endm
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set_z macro ;precharging indexed zp & immediate status
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load_flag \2
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pha ;use stack to load status
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lda \1,x ;load to zeropage
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sta zpt
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plp
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endm
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set_zx macro ;precharging zp,x & immediate status
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load_flag \2
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pha ;use stack to load status
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lda \1,x ;load to indexed zeropage
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sta zpt,x
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plp
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endm
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set_abs macro ;precharging indexed memory & immediate status
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load_flag \2
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pha ;use stack to load status
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lda \1,x ;load to memory
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sta abst
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plp
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endm
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set_absx macro ;precharging abs,x & immediate status
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load_flag \2
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pha ;use stack to load status
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lda \1,x ;load to indexed memory
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sta abst,x
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plp
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endm
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;macros to test (register|memory|zeropage) & status & (mask)
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tst_stat macro ;testing flags in the processor status register
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php ;save status
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php ;use stack to retrieve status
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pla
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cmp_flag \1
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trap_ne
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plp ;restore status
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endm
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tst_a macro ;testing result in accu & flags
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php ;save flags
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php
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cmp #\1 ;test result
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trap_ne
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pla ;load status
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cmp_flag \2
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trap_ne
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plp ;restore status
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endm
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tst_x macro ;testing result in x index & flags
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php ;save flags
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php
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cpx #\1 ;test result
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trap_ne
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pla ;load status
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cmp_flag \2
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trap_ne
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plp ;restore status
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endm
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tst_y macro ;testing result in y index & flags
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php ;save flags
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php
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cpy #\1 ;test result
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trap_ne
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pla ;load status
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cmp_flag \2
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trap_ne
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plp ;restore status
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endm
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tst_ax macro ;indexed testing result in accu & flags
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php ;save flags
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cmp \1,x ;test result
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trap_ne
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pla ;load status
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eor_flag \3
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cmp \2,x ;test flags
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trap_ne ;
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endm
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tst_ay macro ;indexed testing result in accu & flags
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php ;save flags
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cmp \1,y ;test result
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trap_ne ;
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pla ;load status
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eor_flag \3
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cmp \2,y ;test flags
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trap_ne
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endm
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tst_z macro ;indexed testing result in zp & flags
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php ;save flags
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lda zpt
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cmp \1,x ;test result
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trap_ne
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pla ;load status
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eor_flag \3
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cmp \2,x ;test flags
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trap_ne
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endm
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tst_zx macro ;testing result in zp,x & flags
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php ;save flags
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lda zpt,x
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cmp \1,x ;test result
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trap_ne
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pla ;load status
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eor_flag \3
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cmp \2,x ;test flags
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trap_ne
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endm
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tst_abs macro ;indexed testing result in memory & flags
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php ;save flags
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lda abst
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cmp \1,x ;test result
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trap_ne
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pla ;load status
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eor_flag \3
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cmp \2,x ;test flags
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trap_ne
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endm
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tst_absx macro ;testing result in abs,x & flags
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php ;save flags
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lda abst,x
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cmp \1,x ;test result
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trap_ne
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pla ;load status
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eor_flag \3
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cmp \2,x ;test flags
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trap_ne
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endm
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; RAM integrity test
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; verifies that none of the previous tests has altered RAM outside of the
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; designated write areas.
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; uses zpt word as indirect pointer, zpt+2 word as checksum
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if ram_top > -1
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check_ram macro
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cld
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lda #0
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sta zpt ;set low byte of indirect pointer
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sta zpt+3 ;checksum high byte
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sta range_adr ;reset self modifying code
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sta tandi1
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sta tandi2
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sta teori1
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sta teori2
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sta torai1
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sta torai2
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sta chkdadi
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sta chkdsbi
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sta chkadi
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sta chksbi
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clc
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ldx #zp_bss-zero_page ;zeropage - write test area
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ccs3\? adc zero_page,x
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bcc ccs2\?
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inc zpt+3 ;carry to high byte
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clc
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ccs2\? inx
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bne ccs3\?
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ldx #hi(data_segment) ;set high byte of indirect pointer
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stx zpt+1
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ldy #lo(data_bss) ;data after write test area
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ccs5\? adc (zpt),y
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bcc ccs4\?
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inc zpt+3 ;carry to high byte
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clc
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ccs4\? iny
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bne ccs5\?
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inx ;advance RAM high address
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stx zpt+1
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cpx #ram_top
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bne ccs5\?
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sta zpt+2 ;checksum low is
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cmp ram_chksm ;checksum low expected
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trap_ne ;checksum mismatch
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lda zpt+3 ;checksum high is
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cmp ram_chksm+1 ;checksum high expected
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trap_ne ;checksum mismatch
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endm
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else
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check_ram macro
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;RAM check disabled - RAM size not set
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endm
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endif
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next_test macro ;make sure, tests don't jump the fence
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lda test_case ;previous test
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cmp #test_num
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trap_ne ;test is out of sequence
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test_num = test_num + 1
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lda #test_num ;*** next tests' number
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sta test_case
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;check_ram ;uncomment to find altered RAM after each test
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endm
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if load_data_direct = 1
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data
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else
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bss ;uninitialized segment, copy of data at end of code!
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endif
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org zero_page
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;break test interrupt save
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irq_a ds 1 ;a register
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irq_x ds 1 ;x register
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if I_flag = 2
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;masking for I bit in status
|
|
flag_I_on ds 1 ;or mask to load flags
|
|
flag_I_off ds 1 ;and mask to load flags
|
|
endif
|
|
zpt ;5 bytes store/modify test area
|
|
;add/subtract operand generation and result/flag prediction
|
|
adfc ds 1 ;carry flag before op
|
|
ad1 ds 1 ;operand 1 - accumulator
|
|
ad2 ds 1 ;operand 2 - memory / immediate
|
|
adrl ds 1 ;expected result bits 0-7
|
|
adrh ds 1 ;expected result bit 8 (carry)
|
|
adrf ds 1 ;expected flags NV0000ZC (only binary mode)
|
|
sb2 ds 1 ;operand 2 complemented for subtract
|
|
zp_bss
|
|
zp1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
|
|
zp7f db $7f ;test pattern for compare
|
|
;logical zeropage operands
|
|
zpOR db 0,$1f,$71,$80 ;test pattern for OR
|
|
zpAN db $0f,$ff,$7f,$80 ;test pattern for AND
|
|
zpEO db $ff,$0f,$8f,$8f ;test pattern for EOR
|
|
;indirect addressing pointers
|
|
ind1 dw abs1 ;indirect pointer to pattern in absolute memory
|
|
dw abs1+1
|
|
dw abs1+2
|
|
dw abs1+3
|
|
dw abs7f
|
|
inw1 dw abs1-$f8 ;indirect pointer for wrap-test pattern
|
|
indt dw abst ;indirect pointer to store area in absolute memory
|
|
dw abst+1
|
|
dw abst+2
|
|
dw abst+3
|
|
inwt dw abst-$f8 ;indirect pointer for wrap-test store
|
|
indAN dw absAN ;indirect pointer to AND pattern in absolute memory
|
|
dw absAN+1
|
|
dw absAN+2
|
|
dw absAN+3
|
|
indEO dw absEO ;indirect pointer to EOR pattern in absolute memory
|
|
dw absEO+1
|
|
dw absEO+2
|
|
dw absEO+3
|
|
indOR dw absOR ;indirect pointer to OR pattern in absolute memory
|
|
dw absOR+1
|
|
dw absOR+2
|
|
dw absOR+3
|
|
;add/subtract indirect pointers
|
|
adi2 dw ada2 ;indirect pointer to operand 2 in absolute memory
|
|
sbi2 dw sba2 ;indirect pointer to complemented operand 2 (SBC)
|
|
adiy2 dw ada2-$ff ;with offset for indirect indexed
|
|
sbiy2 dw sba2-$ff
|
|
zp_bss_end
|
|
|
|
org data_segment
|
|
test_case ds 1 ;current test number
|
|
ram_chksm ds 2 ;checksum for RAM integrity test
|
|
;add/subtract operand copy - abs tests write area
|
|
abst ;5 bytes store/modify test area
|
|
ada2 ds 1 ;operand 2
|
|
sba2 ds 1 ;operand 2 complemented for subtract
|
|
ds 3 ;fill remaining bytes
|
|
data_bss
|
|
abs1 db $c3,$82,$41,0 ;test patterns for LDx BIT ROL ROR ASL LSR
|
|
abs7f db $7f ;test pattern for compare
|
|
;loads
|
|
fLDx db fn,fn,0,fz ;expected flags for load
|
|
;shifts
|
|
rASL ;expected result ASL & ROL -carry
|
|
rROL db $86,$04,$82,0 ; "
|
|
rROLc db $87,$05,$83,1 ;expected result ROL +carry
|
|
rLSR ;expected result LSR & ROR -carry
|
|
rROR db $61,$41,$20,0 ; "
|
|
rRORc db $e1,$c1,$a0,$80 ;expected result ROR +carry
|
|
fASL ;expected flags for shifts
|
|
fROL db fnc,fc,fn,fz ;no carry in
|
|
fROLc db fnc,fc,fn,0 ;carry in
|
|
fLSR
|
|
fROR db fc,0,fc,fz ;no carry in
|
|
fRORc db fnc,fn,fnc,fn ;carry in
|
|
;increments (decrements)
|
|
rINC db $7f,$80,$ff,0,1 ;expected result for INC/DEC
|
|
fINC db 0,fn,fn,fz,0 ;expected flags for INC/DEC
|
|
;logical memory operand
|
|
absOR db 0,$1f,$71,$80 ;test pattern for OR
|
|
absAN db $0f,$ff,$7f,$80 ;test pattern for AND
|
|
absEO db $ff,$0f,$8f,$8f ;test pattern for EOR
|
|
;logical accu operand
|
|
absORa db 0,$f1,$1f,0 ;test pattern for OR
|
|
absANa db $f0,$ff,$ff,$ff ;test pattern for AND
|
|
absEOa db $ff,$f0,$f0,$0f ;test pattern for EOR
|
|
;logical results
|
|
absrlo db 0,$ff,$7f,$80
|
|
absflo db fz,fn,0,fn
|
|
data_bss_end
|
|
|
|
|
|
code
|
|
org code_segment
|
|
start cld
|
|
ldx #$ff
|
|
txs
|
|
lda #0 ;*** test 0 = initialize
|
|
sta test_case
|
|
test_num = 0
|
|
|
|
;stop interrupts before initializing BSS
|
|
if I_flag = 1
|
|
sei
|
|
endif
|
|
|
|
;initialize I/O for report channel
|
|
if report = 1
|
|
jsr report_init
|
|
endif
|
|
|
|
;initialize BSS segment
|
|
if load_data_direct != 1
|
|
ldx #zp_end-zp_init-1
|
|
ld_zp lda zp_init,x
|
|
sta zp_bss,x
|
|
dex
|
|
bpl ld_zp
|
|
ldx #data_end-data_init-1
|
|
ld_data lda data_init,x
|
|
sta data_bss,x
|
|
dex
|
|
bpl ld_data
|
|
if ROM_vectors = 1
|
|
ldx #5
|
|
ld_vect lda vec_init,x
|
|
sta vec_bss,x
|
|
dex
|
|
bpl ld_vect
|
|
endif
|
|
endif
|
|
|
|
;retain status of interrupt flag
|
|
if I_flag = 2
|
|
php
|
|
pla
|
|
and #4 ;isolate flag
|
|
sta flag_I_on ;or mask
|
|
eor #lo(~4) ;reverse
|
|
sta flag_I_off ;and mask
|
|
endif
|
|
|
|
;generate checksum for RAM integrity test
|
|
if ram_top > -1
|
|
lda #0
|
|
sta zpt ;set low byte of indirect pointer
|
|
sta ram_chksm+1 ;checksum high byte
|
|
sta range_adr ;reset self modifying code
|
|
sta tandi1
|
|
sta tandi2
|
|
sta teori1
|
|
sta teori2
|
|
sta torai1
|
|
sta torai2
|
|
sta chkdadi
|
|
sta chkdsbi
|
|
sta chkadi
|
|
sta chksbi
|
|
clc
|
|
ldx #zp_bss-zero_page ;zeropage - write test area
|
|
gcs3 adc zero_page,x
|
|
bcc gcs2
|
|
inc ram_chksm+1 ;carry to high byte
|
|
clc
|
|
gcs2 inx
|
|
bne gcs3
|
|
ldx #hi(data_segment) ;set high byte of indirect pointer
|
|
stx zpt+1
|
|
ldy #lo(data_bss) ;data after write test area
|
|
gcs5 adc (zpt),y
|
|
bcc gcs4
|
|
inc ram_chksm+1 ;carry to high byte
|
|
clc
|
|
gcs4 iny
|
|
bne gcs5
|
|
inx ;advance RAM high address
|
|
stx zpt+1
|
|
cpx #ram_top
|
|
bne gcs5
|
|
sta ram_chksm ;checksum complete
|
|
endif
|
|
next_test
|
|
|
|
;testing relative addressing with BEQ
|
|
ldy #$fe ;testing maximum range, not -1/-2 (invalid/self adr)
|
|
range_loop
|
|
dey ;next relative address
|
|
tya
|
|
tax ;precharge count to end of loop
|
|
bpl range_fw ;calculate relative address
|
|
clc ;avoid branch self or to relative address of branch
|
|
adc #2
|
|
range_fw
|
|
eor #$7f ;complement except sign
|
|
sta range_adr ;load into test target
|
|
lda #0 ;should set zero flag in status register
|
|
jmp range_op
|
|
|
|
;relative address target field with branch under test in the middle
|
|
dex ;-128 - max backward
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-120
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-110
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-100
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-90
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-80
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-70
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-60
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-50
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-40
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-30
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-20
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-10
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;-3
|
|
range_op ;test target with zero flag=0, z=1 if previous dex
|
|
range_adr = *+1 ;modifiable relative address
|
|
beq *+64 ;if called without modification
|
|
dex ;+0
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+10
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+20
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+30
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+40
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+50
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+60
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+70
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+80
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+90
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+100
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+110
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex ;+120
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
dex
|
|
beq range_ok ;+127 - max forward
|
|
trap ; bad range
|
|
range_ok
|
|
cpy #0
|
|
beq range_end
|
|
jmp range_loop
|
|
range_end ;range test successful
|
|
next_test
|
|
|
|
;partial test BNE & CMP, CPX, CPY immediate
|
|
cpy #1 ;testing BNE true
|
|
bne test_bne
|
|
trap
|
|
test_bne
|
|
lda #0
|
|
cmp #0 ;test compare immediate
|
|
trap_ne
|
|
trap_cc
|
|
trap_mi
|
|
cmp #1
|
|
trap_eq
|
|
trap_cs
|
|
trap_pl
|
|
tax
|
|
cpx #0 ;test compare x immediate
|
|
trap_ne
|
|
trap_cc
|
|
trap_mi
|
|
cpx #1
|
|
trap_eq
|
|
trap_cs
|
|
trap_pl
|
|
tay
|
|
cpy #0 ;test compare y immediate
|
|
trap_ne
|
|
trap_cc
|
|
trap_mi
|
|
cpy #1
|
|
trap_eq
|
|
trap_cs
|
|
trap_pl
|
|
next_test
|
|
;testing stack operations PHA PHP PLA PLP
|
|
|
|
ldx #$ff ;initialize stack
|
|
txs
|
|
lda #$55
|
|
pha
|
|
lda #$aa
|
|
pha
|
|
cmp $1fe ;on stack ?
|
|
trap_ne
|
|
tsx
|
|
txa ;overwrite accu
|
|
cmp #$fd ;sp decremented?
|
|
trap_ne
|
|
pla
|
|
cmp #$aa ;successful retreived from stack?
|
|
trap_ne
|
|
pla
|
|
cmp #$55
|
|
trap_ne
|
|
cmp $1ff ;remains on stack?
|
|
trap_ne
|
|
tsx
|
|
cpx #$ff ;sp incremented?
|
|
trap_ne
|
|
next_test
|
|
|
|
;testing branch decisions BPL BMI BVC BVS BCC BCS BNE BEQ
|
|
set_stat $ff ;all on
|
|
bpl nbr1 ;branches should not be taken
|
|
bvc nbr2
|
|
bcc nbr3
|
|
bne nbr4
|
|
bmi br1 ;branches should be taken
|
|
trap
|
|
br1 bvs br2
|
|
trap
|
|
br2 bcs br3
|
|
trap
|
|
br3 beq br4
|
|
trap
|
|
nbr1
|
|
trap ;previous bpl taken
|
|
nbr2
|
|
trap ;previous bvc taken
|
|
nbr3
|
|
trap ;previous bcc taken
|
|
nbr4
|
|
trap ;previous bne taken
|
|
br4 php
|
|
tsx
|
|
cpx #$fe ;sp after php?
|
|
trap_ne
|
|
pla
|
|
cmp_flag $ff ;returned all flags on?
|
|
trap_ne
|
|
tsx
|
|
cpx #$ff ;sp after php?
|
|
trap_ne
|
|
set_stat 0 ;all off
|
|
bmi nbr11 ;branches should not be taken
|
|
bvs nbr12
|
|
bcs nbr13
|
|
beq nbr14
|
|
bpl br11 ;branches should be taken
|
|
trap
|
|
br11 bvc br12
|
|
trap
|
|
br12 bcc br13
|
|
trap
|
|
br13 bne br14
|
|
trap
|
|
nbr11
|
|
trap ;previous bmi taken
|
|
nbr12
|
|
trap ;previous bvs taken
|
|
nbr13
|
|
trap ;previous bcs taken
|
|
nbr14
|
|
trap ;previous beq taken
|
|
br14 php
|
|
pla
|
|
cmp_flag 0 ;flags off except break (pushed by sw) + reserved?
|
|
trap_ne
|
|
;crosscheck flags
|
|
set_stat zero
|
|
bne brzs1
|
|
beq brzs2
|
|
brzs1
|
|
trap ;branch zero/non zero
|
|
brzs2 bcs brzs3
|
|
bcc brzs4
|
|
brzs3
|
|
trap ;branch carry/no carry
|
|
brzs4 bmi brzs5
|
|
bpl brzs6
|
|
brzs5
|
|
trap ;branch minus/plus
|
|
brzs6 bvs brzs7
|
|
bvc brzs8
|
|
brzs7
|
|
trap ;branch overflow/no overflow
|
|
brzs8
|
|
set_stat carry
|
|
beq brcs1
|
|
bne brcs2
|
|
brcs1
|
|
trap ;branch zero/non zero
|
|
brcs2 bcc brcs3
|
|
bcs brcs4
|
|
brcs3
|
|
trap ;branch carry/no carry
|
|
brcs4 bmi brcs5
|
|
bpl brcs6
|
|
brcs5
|
|
trap ;branch minus/plus
|
|
brcs6 bvs brcs7
|
|
bvc brcs8
|
|
brcs7
|
|
trap ;branch overflow/no overflow
|
|
|
|
brcs8
|
|
set_stat minus
|
|
beq brmi1
|
|
bne brmi2
|
|
brmi1
|
|
trap ;branch zero/non zero
|
|
brmi2 bcs brmi3
|
|
bcc brmi4
|
|
brmi3
|
|
trap ;branch carry/no carry
|
|
brmi4 bpl brmi5
|
|
bmi brmi6
|
|
brmi5
|
|
trap ;branch minus/plus
|
|
brmi6 bvs brmi7
|
|
bvc brmi8
|
|
brmi7
|
|
trap ;branch overflow/no overflow
|
|
brmi8
|
|
set_stat overfl
|
|
beq brvs1
|
|
bne brvs2
|
|
brvs1
|
|
trap ;branch zero/non zero
|
|
brvs2 bcs brvs3
|
|
bcc brvs4
|
|
brvs3
|
|
trap ;branch carry/no carry
|
|
brvs4 bmi brvs5
|
|
bpl brvs6
|
|
brvs5
|
|
trap ;branch minus/plus
|
|
brvs6 bvc brvs7
|
|
bvs brvs8
|
|
brvs7
|
|
trap ;branch overflow/no overflow
|
|
brvs8
|
|
set_stat $ff-zero
|
|
beq brzc1
|
|
bne brzc2
|
|
brzc1
|
|
trap ;branch zero/non zero
|
|
brzc2 bcc brzc3
|
|
bcs brzc4
|
|
brzc3
|
|
trap ;branch carry/no carry
|
|
brzc4 bpl brzc5
|
|
bmi brzc6
|
|
brzc5
|
|
trap ;branch minus/plus
|
|
brzc6 bvc brzc7
|
|
bvs brzc8
|
|
brzc7
|
|
trap ;branch overflow/no overflow
|
|
brzc8
|
|
set_stat $ff-carry
|
|
bne brcc1
|
|
beq brcc2
|
|
brcc1
|
|
trap ;branch zero/non zero
|
|
brcc2 bcs brcc3
|
|
bcc brcc4
|
|
brcc3
|
|
trap ;branch carry/no carry
|
|
brcc4 bpl brcc5
|
|
bmi brcc6
|
|
brcc5
|
|
trap ;branch minus/plus
|
|
brcc6 bvc brcc7
|
|
bvs brcc8
|
|
brcc7
|
|
trap ;branch overflow/no overflow
|
|
brcc8
|
|
set_stat $ff-minus
|
|
bne brpl1
|
|
beq brpl2
|
|
brpl1
|
|
trap ;branch zero/non zero
|
|
brpl2 bcc brpl3
|
|
bcs brpl4
|
|
brpl3
|
|
trap ;branch carry/no carry
|
|
brpl4 bmi brpl5
|
|
bpl brpl6
|
|
brpl5
|
|
trap ;branch minus/plus
|
|
brpl6 bvc brpl7
|
|
bvs brpl8
|
|
brpl7
|
|
trap ;branch overflow/no overflow
|
|
brpl8
|
|
set_stat $ff-overfl
|
|
bne brvc1
|
|
beq brvc2
|
|
brvc1
|
|
trap ;branch zero/non zero
|
|
brvc2 bcc brvc3
|
|
bcs brvc4
|
|
brvc3
|
|
trap ;branch carry/no carry
|
|
brvc4 bpl brvc5
|
|
bmi brvc6
|
|
brvc5
|
|
trap ;branch minus/plus
|
|
brvc6 bvs brvc7
|
|
bvc brvc8
|
|
brvc7
|
|
trap ;branch overflow/no overflow
|
|
brvc8
|
|
next_test
|
|
|
|
; test PHA does not alter flags or accumulator but PLA does
|
|
ldx #$55 ;x & y protected
|
|
ldy #$aa
|
|
set_a 1,$ff ;push
|
|
pha
|
|
tst_a 1,$ff
|
|
set_a 0,0
|
|
pha
|
|
tst_a 0,0
|
|
set_a $ff,$ff
|
|
pha
|
|
tst_a $ff,$ff
|
|
set_a 1,0
|
|
pha
|
|
tst_a 1,0
|
|
set_a 0,$ff
|
|
pha
|
|
tst_a 0,$ff
|
|
set_a $ff,0
|
|
pha
|
|
tst_a $ff,0
|
|
set_a 0,$ff ;pull
|
|
pla
|
|
tst_a $ff,$ff-zero
|
|
set_a $ff,0
|
|
pla
|
|
tst_a 0,zero
|
|
set_a $fe,$ff
|
|
pla
|
|
tst_a 1,$ff-zero-minus
|
|
set_a 0,0
|
|
pla
|
|
tst_a $ff,minus
|
|
set_a $ff,$ff
|
|
pla
|
|
tst_a 0,$ff-minus
|
|
set_a $fe,0
|
|
pla
|
|
tst_a 1,0
|
|
cpx #$55 ;x & y unchanged?
|
|
trap_ne
|
|
cpy #$aa
|
|
trap_ne
|
|
next_test
|
|
|
|
; partial pretest EOR #
|
|
set_a $3c,0
|
|
eor #$c3
|
|
tst_a $ff,fn
|
|
set_a $c3,0
|
|
eor #$c3
|
|
tst_a 0,fz
|
|
next_test
|
|
|
|
; PC modifying instructions except branches (NOP, JMP, JSR, RTS, BRK, RTI)
|
|
; testing NOP
|
|
ldx #$24
|
|
ldy #$42
|
|
set_a $18,0
|
|
nop
|
|
tst_a $18,0
|
|
cpx #$24
|
|
trap_ne
|
|
cpy #$42
|
|
trap_ne
|
|
ldx #$db
|
|
ldy #$bd
|
|
set_a $e7,$ff
|
|
nop
|
|
tst_a $e7,$ff
|
|
cpx #$db
|
|
trap_ne
|
|
cpy #$bd
|
|
trap_ne
|
|
next_test
|
|
|
|
; jump absolute
|
|
set_stat $0
|
|
lda #'F'
|
|
ldx #'A'
|
|
ldy #'R' ;N=0, V=0, Z=0, C=0
|
|
jmp test_far
|
|
nop
|
|
nop
|
|
trap_ne ;runover protection
|
|
inx
|
|
inx
|
|
far_ret
|
|
trap_eq ;returned flags OK?
|
|
trap_pl
|
|
trap_cc
|
|
trap_vc
|
|
cmp #('F'^$aa) ;returned registers OK?
|
|
trap_ne
|
|
cpx #('A'+1)
|
|
trap_ne
|
|
cpy #('R'-3)
|
|
trap_ne
|
|
dex
|
|
iny
|
|
iny
|
|
iny
|
|
eor #$aa ;N=0, V=1, Z=0, C=1
|
|
jmp test_near
|
|
nop
|
|
nop
|
|
trap_ne ;runover protection
|
|
inx
|
|
inx
|
|
test_near
|
|
trap_eq ;passed flags OK?
|
|
trap_mi
|
|
trap_cc
|
|
trap_vc
|
|
cmp #'F' ;passed registers OK?
|
|
trap_ne
|
|
cpx #'A'
|
|
trap_ne
|
|
cpy #'R'
|
|
trap_ne
|
|
next_test
|
|
|
|
; jump indirect
|
|
set_stat 0
|
|
lda #'I'
|
|
ldx #'N'
|
|
ldy #'D' ;N=0, V=0, Z=0, C=0
|
|
jmp (ptr_tst_ind)
|
|
nop
|
|
trap_ne ;runover protection
|
|
dey
|
|
dey
|
|
ind_ret
|
|
php ;either SP or Y count will fail, if we do not hit
|
|
dey
|
|
dey
|
|
dey
|
|
plp
|
|
trap_eq ;returned flags OK?
|
|
trap_pl
|
|
trap_cc
|
|
trap_vc
|
|
cmp #('I'^$aa) ;returned registers OK?
|
|
trap_ne
|
|
cpx #('N'+1)
|
|
trap_ne
|
|
cpy #('D'-6)
|
|
trap_ne
|
|
tsx ;SP check
|
|
cpx #$ff
|
|
trap_ne
|
|
next_test
|
|
|
|
; jump subroutine & return from subroutine
|
|
set_stat 0
|
|
lda #'J'
|
|
ldx #'S'
|
|
ldy #'R' ;N=0, V=0, Z=0, C=0
|
|
jsr test_jsr
|
|
jsr_ret = *-1 ;last address of jsr = return address
|
|
php ;either SP or Y count will fail, if we do not hit
|
|
dey
|
|
dey
|
|
dey
|
|
plp
|
|
trap_eq ;returned flags OK?
|
|
trap_pl
|
|
trap_cc
|
|
trap_vc
|
|
cmp #('J'^$aa) ;returned registers OK?
|
|
trap_ne
|
|
cpx #('S'+1)
|
|
trap_ne
|
|
cpy #('R'-6)
|
|
trap_ne
|
|
tsx ;sp?
|
|
cpx #$ff
|
|
trap_ne
|
|
next_test
|
|
|
|
; break & return from interrupt
|
|
if ROM_vectors = 1
|
|
set_stat 0
|
|
lda #'B'
|
|
ldx #'R'
|
|
ldy #'K' ;N=0, V=0, Z=0, C=0
|
|
brk
|
|
else
|
|
lda #hi brk_ret ;emulated break
|
|
pha
|
|
lda #lo brk_ret
|
|
pha
|
|
lda #fao ;set break & unused on stack
|
|
pha
|
|
set_stat intdis
|
|
lda #'B'
|
|
ldx #'R'
|
|
ldy #'K' ;N=0, V=0, Z=0, C=0
|
|
jmp irq_trap
|
|
endif
|
|
dey ;should not be executed
|
|
brk_ret ;address of break return
|
|
php ;either SP or Y count will fail, if we do not hit
|
|
dey
|
|
dey
|
|
dey
|
|
cmp #('B'^$aa) ;returned registers OK?
|
|
trap_ne
|
|
cpx #('R'+1)
|
|
trap_ne
|
|
cpy #('K'-6)
|
|
trap_ne
|
|
pla ;returned flags OK (unchanged)?
|
|
cmp_flag 0
|
|
trap_ne
|
|
tsx ;sp?
|
|
cpx #$ff
|
|
trap_ne
|
|
next_test
|
|
|
|
; test set and clear flags CLC CLI CLD CLV SEC SEI SED
|
|
set_stat $ff
|
|
clc
|
|
tst_stat $ff-carry
|
|
sec
|
|
tst_stat $ff
|
|
if I_flag = 3
|
|
cli
|
|
tst_stat $ff-intdis
|
|
sei
|
|
tst_stat $ff
|
|
endif
|
|
cld
|
|
tst_stat $ff-decmode
|
|
sed
|
|
tst_stat $ff
|
|
clv
|
|
tst_stat $ff-overfl
|
|
set_stat 0
|
|
tst_stat 0
|
|
sec
|
|
tst_stat carry
|
|
clc
|
|
tst_stat 0
|
|
if I_flag = 3
|
|
sei
|
|
tst_stat intdis
|
|
cli
|
|
tst_stat 0
|
|
endif
|
|
sed
|
|
tst_stat decmode
|
|
cld
|
|
tst_stat 0
|
|
set_stat overfl
|
|
tst_stat overfl
|
|
clv
|
|
tst_stat 0
|
|
next_test
|
|
; testing index register increment/decrement and transfer
|
|
; INX INY DEX DEY TAX TXA TAY TYA
|
|
ldx #$fe
|
|
set_stat $ff
|
|
inx ;ff
|
|
tst_x $ff,$ff-zero
|
|
inx ;00
|
|
tst_x 0,$ff-minus
|
|
inx ;01
|
|
tst_x 1,$ff-minus-zero
|
|
dex ;00
|
|
tst_x 0,$ff-minus
|
|
dex ;ff
|
|
tst_x $ff,$ff-zero
|
|
dex ;fe
|
|
set_stat 0
|
|
inx ;ff
|
|
tst_x $ff,minus
|
|
inx ;00
|
|
tst_x 0,zero
|
|
inx ;01
|
|
tst_x 1,0
|
|
dex ;00
|
|
tst_x 0,zero
|
|
dex ;ff
|
|
tst_x $ff,minus
|
|
|
|
ldy #$fe
|
|
set_stat $ff
|
|
iny ;ff
|
|
tst_y $ff,$ff-zero
|
|
iny ;00
|
|
tst_y 0,$ff-minus
|
|
iny ;01
|
|
tst_y 1,$ff-minus-zero
|
|
dey ;00
|
|
tst_y 0,$ff-minus
|
|
dey ;ff
|
|
tst_y $ff,$ff-zero
|
|
dey ;fe
|
|
set_stat 0
|
|
iny ;ff
|
|
tst_y $ff,0+minus
|
|
iny ;00
|
|
tst_y 0,zero
|
|
iny ;01
|
|
tst_y 1,0
|
|
dey ;00
|
|
tst_y 0,zero
|
|
dey ;ff
|
|
tst_y $ff,minus
|
|
|
|
ldx #$ff
|
|
set_stat $ff
|
|
txa
|
|
tst_a $ff,$ff-zero
|
|
php
|
|
inx ;00
|
|
plp
|
|
txa
|
|
tst_a 0,$ff-minus
|
|
php
|
|
inx ;01
|
|
plp
|
|
txa
|
|
tst_a 1,$ff-minus-zero
|
|
set_stat 0
|
|
txa
|
|
tst_a 1,0
|
|
php
|
|
dex ;00
|
|
plp
|
|
txa
|
|
tst_a 0,zero
|
|
php
|
|
dex ;ff
|
|
plp
|
|
txa
|
|
tst_a $ff,minus
|
|
|
|
ldy #$ff
|
|
set_stat $ff
|
|
tya
|
|
tst_a $ff,$ff-zero
|
|
php
|
|
iny ;00
|
|
plp
|
|
tya
|
|
tst_a 0,$ff-minus
|
|
php
|
|
iny ;01
|
|
plp
|
|
tya
|
|
tst_a 1,$ff-minus-zero
|
|
set_stat 0
|
|
tya
|
|
tst_a 1,0
|
|
php
|
|
dey ;00
|
|
plp
|
|
tya
|
|
tst_a 0,zero
|
|
php
|
|
dey ;ff
|
|
plp
|
|
tya
|
|
tst_a $ff,minus
|
|
|
|
load_flag $ff
|
|
pha
|
|
ldx #$ff ;ff
|
|
txa
|
|
plp
|
|
tay
|
|
tst_y $ff,$ff-zero
|
|
php
|
|
inx ;00
|
|
txa
|
|
plp
|
|
tay
|
|
tst_y 0,$ff-minus
|
|
php
|
|
inx ;01
|
|
txa
|
|
plp
|
|
tay
|
|
tst_y 1,$ff-minus-zero
|
|
load_flag 0
|
|
pha
|
|
lda #0
|
|
txa
|
|
plp
|
|
tay
|
|
tst_y 1,0
|
|
php
|
|
dex ;00
|
|
txa
|
|
plp
|
|
tay
|
|
tst_y 0,zero
|
|
php
|
|
dex ;ff
|
|
txa
|
|
plp
|
|
tay
|
|
tst_y $ff,minus
|
|
|
|
|
|
load_flag $ff
|
|
pha
|
|
ldy #$ff ;ff
|
|
tya
|
|
plp
|
|
tax
|
|
tst_x $ff,$ff-zero
|
|
php
|
|
iny ;00
|
|
tya
|
|
plp
|
|
tax
|
|
tst_x 0,$ff-minus
|
|
php
|
|
iny ;01
|
|
tya
|
|
plp
|
|
tax
|
|
tst_x 1,$ff-minus-zero
|
|
load_flag 0
|
|
pha
|
|
lda #0 ;preset status
|
|
tya
|
|
plp
|
|
tax
|
|
tst_x 1,0
|
|
php
|
|
dey ;00
|
|
tya
|
|
plp
|
|
tax
|
|
tst_x 0,zero
|
|
php
|
|
dey ;ff
|
|
tya
|
|
plp
|
|
tax
|
|
tst_x $ff,minus
|
|
next_test
|
|
|
|
;TSX sets NZ - TXS does not
|
|
ldx #1 ;01
|
|
set_stat $ff
|
|
txs
|
|
php
|
|
lda $101
|
|
cmp_flag $ff
|
|
trap_ne
|
|
set_stat 0
|
|
txs
|
|
php
|
|
lda $101
|
|
cmp_flag 0
|
|
trap_ne
|
|
dex ;00
|
|
set_stat $ff
|
|
txs
|
|
php
|
|
lda $100
|
|
cmp_flag $ff
|
|
trap_ne
|
|
set_stat 0
|
|
txs
|
|
php
|
|
lda $100
|
|
cmp_flag 0
|
|
trap_ne
|
|
dex ;ff
|
|
set_stat $ff
|
|
txs
|
|
php
|
|
lda $1ff
|
|
cmp_flag $ff
|
|
trap_ne
|
|
set_stat 0
|
|
txs
|
|
php
|
|
lda $1ff
|
|
cmp_flag 0
|
|
|
|
ldx #1
|
|
txs ;sp=01
|
|
set_stat $ff
|
|
tsx ;clears Z, N
|
|
php ;sp=00
|
|
cpx #1
|
|
trap_ne
|
|
lda $101
|
|
cmp_flag $ff-minus-zero
|
|
trap_ne
|
|
set_stat $ff
|
|
tsx ;clears N, sets Z
|
|
php ;sp=ff
|
|
cpx #0
|
|
trap_ne
|
|
lda $100
|
|
cmp_flag $ff-minus
|
|
trap_ne
|
|
set_stat $ff
|
|
tsx ;clears N, sets Z
|
|
php ;sp=fe
|
|
cpx #$ff
|
|
trap_ne
|
|
lda $1ff
|
|
cmp_flag $ff-zero
|
|
trap_ne
|
|
|
|
ldx #1
|
|
txs ;sp=01
|
|
set_stat 0
|
|
tsx ;clears Z, N
|
|
php ;sp=00
|
|
cpx #1
|
|
trap_ne
|
|
lda $101
|
|
cmp_flag 0
|
|
trap_ne
|
|
set_stat 0
|
|
tsx ;clears N, sets Z
|
|
php ;sp=ff
|
|
cpx #0
|
|
trap_ne
|
|
lda $100
|
|
cmp_flag zero
|
|
trap_ne
|
|
set_stat 0
|
|
tsx ;clears N, sets Z
|
|
php ;sp=fe
|
|
cpx #$ff
|
|
trap_ne
|
|
lda $1ff
|
|
cmp_flag minus
|
|
trap_ne
|
|
pla ;sp=ff
|
|
next_test
|
|
|
|
; testing index register load & store LDY LDX STY STX all addressing modes
|
|
; LDX / STX - zp,y / abs,y
|
|
ldy #3
|
|
tldx
|
|
set_stat 0
|
|
ldx zp1,y
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
plp
|
|
sta abst,y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tldx
|
|
|
|
ldy #3
|
|
tldx1
|
|
set_stat $ff
|
|
ldx zp1,y
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
plp
|
|
sta abst,y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tldx1
|
|
|
|
ldy #3
|
|
tldx2
|
|
set_stat 0
|
|
ldx abs1,y
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt,y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tldx2
|
|
|
|
ldy #3
|
|
tldx3
|
|
set_stat $ff
|
|
ldx abs1,y
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt,y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tldx3
|
|
|
|
ldy #3 ;testing store result
|
|
ldx #0
|
|
tstx lda zpt,y
|
|
eor #$c3
|
|
cmp zp1,y
|
|
trap_ne ;store to zp data
|
|
stx zpt,y ;clear
|
|
lda abst,y
|
|
eor #$c3
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstx
|
|
next_test
|
|
|
|
; indexed wraparound test (only zp should wrap)
|
|
ldy #3+$fa
|
|
tldx4 ldx zp1-$fa&$ff,y ;wrap on indexed zp
|
|
txa
|
|
sta abst-$fa,y ;no STX abs,y!
|
|
dey
|
|
cpy #$fa
|
|
bcs tldx4
|
|
ldy #3+$fa
|
|
tldx5 ldx abs1-$fa,y ;no wrap on indexed abs
|
|
stx zpt-$fa&$ff,y
|
|
dey
|
|
cpy #$fa
|
|
bcs tldx5
|
|
ldy #3 ;testing wraparound result
|
|
ldx #0
|
|
tstx1 lda zpt,y
|
|
cmp zp1,y
|
|
trap_ne ;store to zp data
|
|
stx zpt,y ;clear
|
|
lda abst,y
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstx1
|
|
next_test
|
|
|
|
; LDY / STY - zp,x / abs,x
|
|
ldx #3
|
|
tldy
|
|
set_stat 0
|
|
ldy zp1,x
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
plp
|
|
sta abst,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldy
|
|
|
|
ldx #3
|
|
tldy1
|
|
set_stat $ff
|
|
ldy zp1,x
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
plp
|
|
sta abst,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldy1
|
|
|
|
ldx #3
|
|
tldy2
|
|
set_stat 0
|
|
ldy abs1,x
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldy2
|
|
|
|
ldx #3
|
|
tldy3
|
|
set_stat $ff
|
|
ldy abs1,x
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldy3
|
|
|
|
ldx #3 ;testing store result
|
|
ldy #0
|
|
tsty lda zpt,x
|
|
eor #$c3
|
|
cmp zp1,x
|
|
trap_ne ;store to zp,x data
|
|
sty zpt,x ;clear
|
|
lda abst,x
|
|
eor #$c3
|
|
cmp abs1,x
|
|
trap_ne ;store to abs,x data
|
|
txa
|
|
sta abst,x ;clear
|
|
dex
|
|
bpl tsty
|
|
next_test
|
|
|
|
; indexed wraparound test (only zp should wrap)
|
|
ldx #3+$fa
|
|
tldy4 ldy zp1-$fa&$ff,x ;wrap on indexed zp
|
|
tya
|
|
sta abst-$fa,x ;no STX abs,x!
|
|
dex
|
|
cpx #$fa
|
|
bcs tldy4
|
|
ldx #3+$fa
|
|
tldy5 ldy abs1-$fa,x ;no wrap on indexed abs
|
|
sty zpt-$fa&$ff,x
|
|
dex
|
|
cpx #$fa
|
|
bcs tldy5
|
|
ldx #3 ;testing wraparound result
|
|
ldy #0
|
|
tsty1 lda zpt,x
|
|
cmp zp1,x
|
|
trap_ne ;store to zp,x data
|
|
sty zpt,x ;clear
|
|
lda abst,x
|
|
cmp abs1,x
|
|
trap_ne ;store to abs,x data
|
|
txa
|
|
sta abst,x ;clear
|
|
dex
|
|
bpl tsty1
|
|
next_test
|
|
|
|
; LDX / STX - zp / abs / #
|
|
set_stat 0
|
|
ldx zp1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #$c3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx zp1+1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #$82 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx zp1+2
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #$41 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx zp1+3
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #0 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
ldx zp1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #$c3 ;test result
|
|
trap_ne ;
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx zp1+1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #$82 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx zp1+2
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #$41 ;test result
|
|
trap_ne ;
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx zp1+3
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx abst+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx #0 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat 0
|
|
ldx abs1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx abs1+1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx abs1+2
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx abs1+3
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
ldx abs1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx zp1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx abs1+1
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx zp1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx abs1+2
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx zp1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx abs1+3
|
|
php ;test stores do not alter flags
|
|
txa
|
|
eor #$c3
|
|
tax
|
|
plp
|
|
stx zpt+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tax
|
|
cpx zp1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat 0
|
|
ldx #$c3
|
|
php
|
|
cpx abs1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx #$82
|
|
php
|
|
cpx abs1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx #$41
|
|
php
|
|
cpx abs1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldx #0
|
|
php
|
|
cpx abs1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
ldx #$c3
|
|
php
|
|
cpx abs1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx #$82
|
|
php
|
|
cpx abs1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx #$41
|
|
php
|
|
cpx abs1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldx #0
|
|
php
|
|
cpx abs1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
ldx #0
|
|
lda zpt
|
|
eor #$c3
|
|
cmp zp1
|
|
trap_ne ;store to zp data
|
|
stx zpt ;clear
|
|
lda abst
|
|
eor #$c3
|
|
cmp abs1
|
|
trap_ne ;store to abs data
|
|
stx abst ;clear
|
|
lda zpt+1
|
|
eor #$c3
|
|
cmp zp1+1
|
|
trap_ne ;store to zp data
|
|
stx zpt+1 ;clear
|
|
lda abst+1
|
|
eor #$c3
|
|
cmp abs1+1
|
|
trap_ne ;store to abs data
|
|
stx abst+1 ;clear
|
|
lda zpt+2
|
|
eor #$c3
|
|
cmp zp1+2
|
|
trap_ne ;store to zp data
|
|
stx zpt+2 ;clear
|
|
lda abst+2
|
|
eor #$c3
|
|
cmp abs1+2
|
|
trap_ne ;store to abs data
|
|
stx abst+2 ;clear
|
|
lda zpt+3
|
|
eor #$c3
|
|
cmp zp1+3
|
|
trap_ne ;store to zp data
|
|
stx zpt+3 ;clear
|
|
lda abst+3
|
|
eor #$c3
|
|
cmp abs1+3
|
|
trap_ne ;store to abs data
|
|
stx abst+3 ;clear
|
|
next_test
|
|
|
|
; LDY / STY - zp / abs / #
|
|
set_stat 0
|
|
ldy zp1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #$c3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy zp1+1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #$82 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy zp1+2
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #$41 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy zp1+3
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #0 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
ldy zp1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #$c3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy zp1+1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #$82 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy zp1+2
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #$41 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy zp1+3
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty abst+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy #0 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat 0
|
|
ldy abs1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy zp1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy abs1+1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy zp1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy abs1+2
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy zp1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy abs1+3
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cpy zp1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
ldy abs1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cmp zp1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy abs1+1
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cmp zp1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy abs1+2
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cmp zp1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy abs1+3
|
|
php ;test stores do not alter flags
|
|
tya
|
|
eor #$c3
|
|
tay
|
|
plp
|
|
sty zpt+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
tay
|
|
cmp zp1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
|
|
set_stat 0
|
|
ldy #$c3
|
|
php
|
|
cpy abs1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy #$82
|
|
php
|
|
cpy abs1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy #$41
|
|
php
|
|
cpy abs1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
ldy #0
|
|
php
|
|
cpy abs1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
ldy #$c3
|
|
php
|
|
cpy abs1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy #$82
|
|
php
|
|
cpy abs1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy #$41
|
|
php
|
|
cpy abs1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
ldy #0
|
|
php
|
|
cpy abs1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
ldy #0
|
|
lda zpt
|
|
eor #$c3
|
|
cmp zp1
|
|
trap_ne ;store to zp data
|
|
sty zpt ;clear
|
|
lda abst
|
|
eor #$c3
|
|
cmp abs1
|
|
trap_ne ;store to abs data
|
|
sty abst ;clear
|
|
lda zpt+1
|
|
eor #$c3
|
|
cmp zp1+1
|
|
trap_ne ;store to zp+1 data
|
|
sty zpt+1 ;clear
|
|
lda abst+1
|
|
eor #$c3
|
|
cmp abs1+1
|
|
trap_ne ;store to abs+1 data
|
|
sty abst+1 ;clear
|
|
lda zpt+2
|
|
eor #$c3
|
|
cmp zp1+2
|
|
trap_ne ;store to zp+2 data
|
|
sty zpt+2 ;clear
|
|
lda abst+2
|
|
eor #$c3
|
|
cmp abs1+2
|
|
trap_ne ;store to abs+2 data
|
|
sty abst+2 ;clear
|
|
lda zpt+3
|
|
eor #$c3
|
|
cmp zp1+3
|
|
trap_ne ;store to zp+3 data
|
|
sty zpt+3 ;clear
|
|
lda abst+3
|
|
eor #$c3
|
|
cmp abs1+3
|
|
trap_ne ;store to abs+3 data
|
|
sty abst+3 ;clear
|
|
next_test
|
|
|
|
; testing load / store accumulator LDA / STA all addressing modes
|
|
; LDA / STA - zp,x / abs,x
|
|
ldx #3
|
|
tldax
|
|
set_stat 0
|
|
lda zp1,x
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldax
|
|
|
|
ldx #3
|
|
tldax1
|
|
set_stat $ff
|
|
lda zp1,x
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldax1
|
|
|
|
ldx #3
|
|
tldax2
|
|
set_stat 0
|
|
lda abs1,x
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldax2
|
|
|
|
ldx #3
|
|
tldax3
|
|
set_stat $ff
|
|
lda abs1,x
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt,x
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1,x ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,x ;test flags
|
|
trap_ne
|
|
dex
|
|
bpl tldax3
|
|
|
|
ldx #3 ;testing store result
|
|
ldy #0
|
|
tstax lda zpt,x
|
|
eor #$c3
|
|
cmp zp1,x
|
|
trap_ne ;store to zp,x data
|
|
sty zpt,x ;clear
|
|
lda abst,x
|
|
eor #$c3
|
|
cmp abs1,x
|
|
trap_ne ;store to abs,x data
|
|
txa
|
|
sta abst,x ;clear
|
|
dex
|
|
bpl tstax
|
|
next_test
|
|
|
|
; LDA / STA - (zp),y / abs,y / (zp,x)
|
|
ldy #3
|
|
tlday
|
|
set_stat 0
|
|
lda (ind1),y
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst,y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tlday
|
|
|
|
ldy #3
|
|
tlday1
|
|
set_stat $ff
|
|
lda (ind1),y
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst,y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tlday1
|
|
|
|
ldy #3 ;testing store result
|
|
ldx #0
|
|
tstay lda abst,y
|
|
eor #$c3
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstay
|
|
|
|
ldy #3
|
|
tlday2
|
|
set_stat 0
|
|
lda abs1,y
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta (indt),y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp (ind1),y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tlday2
|
|
|
|
ldy #3
|
|
tlday3
|
|
set_stat $ff
|
|
lda abs1,y
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta (indt),y
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp (ind1),y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dey
|
|
bpl tlday3
|
|
|
|
ldy #3 ;testing store result
|
|
ldx #0
|
|
tstay1 lda abst,y
|
|
eor #$c3
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstay1
|
|
|
|
ldx #6
|
|
ldy #3
|
|
tldax4
|
|
set_stat 0
|
|
lda (ind1,x)
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta (indt,x)
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dex
|
|
dex
|
|
dey
|
|
bpl tldax4
|
|
|
|
ldx #6
|
|
ldy #3
|
|
tldax5
|
|
set_stat $ff
|
|
lda (ind1,x)
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta (indt,x)
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp abs1,y ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx,y ;test flags
|
|
trap_ne
|
|
dex
|
|
dex
|
|
dey
|
|
bpl tldax5
|
|
|
|
ldy #3 ;testing store result
|
|
ldx #0
|
|
tstay2 lda abst,y
|
|
eor #$c3
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstay2
|
|
next_test
|
|
|
|
; indexed wraparound test (only zp should wrap)
|
|
ldx #3+$fa
|
|
tldax6 lda zp1-$fa&$ff,x ;wrap on indexed zp
|
|
sta abst-$fa,x ;no STX abs,x!
|
|
dex
|
|
cpx #$fa
|
|
bcs tldax6
|
|
ldx #3+$fa
|
|
tldax7 lda abs1-$fa,x ;no wrap on indexed abs
|
|
sta zpt-$fa&$ff,x
|
|
dex
|
|
cpx #$fa
|
|
bcs tldax7
|
|
|
|
ldx #3 ;testing wraparound result
|
|
ldy #0
|
|
tstax1 lda zpt,x
|
|
cmp zp1,x
|
|
trap_ne ;store to zp,x data
|
|
sty zpt,x ;clear
|
|
lda abst,x
|
|
cmp abs1,x
|
|
trap_ne ;store to abs,x data
|
|
txa
|
|
sta abst,x ;clear
|
|
dex
|
|
bpl tstax1
|
|
|
|
ldy #3+$f8
|
|
ldx #6+$f8
|
|
tlday4 lda (ind1-$f8&$ff,x) ;wrap on indexed zp indirect
|
|
sta abst-$f8,y
|
|
dex
|
|
dex
|
|
dey
|
|
cpy #$f8
|
|
bcs tlday4
|
|
ldy #3 ;testing wraparound result
|
|
ldx #0
|
|
tstay4 lda abst,y
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstay4
|
|
|
|
ldy #3+$f8
|
|
tlday5 lda abs1-$f8,y ;no wrap on indexed abs
|
|
sta (inwt),y
|
|
dey
|
|
cpy #$f8
|
|
bcs tlday5
|
|
ldy #3 ;testing wraparound result
|
|
ldx #0
|
|
tstay5 lda abst,y
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstay5
|
|
|
|
ldy #3+$f8
|
|
ldx #6+$f8
|
|
tlday6 lda (inw1),y ;no wrap on zp indirect indexed
|
|
sta (indt-$f8&$ff,x)
|
|
dex
|
|
dex
|
|
dey
|
|
cpy #$f8
|
|
bcs tlday6
|
|
ldy #3 ;testing wraparound result
|
|
ldx #0
|
|
tstay6 lda abst,y
|
|
cmp abs1,y
|
|
trap_ne ;store to abs data
|
|
txa
|
|
sta abst,y ;clear
|
|
dey
|
|
bpl tstay6
|
|
next_test
|
|
|
|
; LDA / STA - zp / abs / #
|
|
set_stat 0
|
|
lda zp1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #$c3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda zp1+1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #$82 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda zp1+2
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #$41 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda zp1+3
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #0 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda zp1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #$c3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda zp1+1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #$82 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda zp1+2
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #$41 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda zp1+3
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta abst+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp #0 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda abs1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda abs1+1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda abs1+2
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda abs1+3
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda abs1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda abs1+1
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt+1
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda abs1+2
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt+2
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda abs1+3
|
|
php ;test stores do not alter flags
|
|
eor #$c3
|
|
plp
|
|
sta zpt+3
|
|
php ;flags after load/store sequence
|
|
eor #$c3
|
|
cmp zp1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda #$c3
|
|
php
|
|
cmp abs1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda #$82
|
|
php
|
|
cmp abs1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda #$41
|
|
php
|
|
cmp abs1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat 0
|
|
lda #0
|
|
php
|
|
cmp abs1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag 0
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
set_stat $ff
|
|
lda #$c3
|
|
php
|
|
cmp abs1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda #$82
|
|
php
|
|
cmp abs1+1 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+1 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda #$41
|
|
php
|
|
cmp abs1+2 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+2 ;test flags
|
|
trap_ne
|
|
set_stat $ff
|
|
lda #0
|
|
php
|
|
cmp abs1+3 ;test result
|
|
trap_ne
|
|
pla ;load status
|
|
eor_flag lo~fnz ;mask bits not altered
|
|
cmp fLDx+3 ;test flags
|
|
trap_ne
|
|
|
|
ldx #0
|
|
lda zpt
|
|
eor #$c3
|
|
cmp zp1
|
|
trap_ne ;store to zp data
|
|
stx zpt ;clear
|
|
lda abst
|
|
eor #$c3
|
|
cmp abs1
|
|
trap_ne ;store to abs data
|
|
stx abst ;clear
|
|
lda zpt+1
|
|
eor #$c3
|
|
cmp zp1+1
|
|
trap_ne ;store to zp data
|
|
stx zpt+1 ;clear
|
|
lda abst+1
|
|
eor #$c3
|
|
cmp abs1+1
|
|
trap_ne ;store to abs data
|
|
stx abst+1 ;clear
|
|
lda zpt+2
|
|
eor #$c3
|
|
cmp zp1+2
|
|
trap_ne ;store to zp data
|
|
stx zpt+2 ;clear
|
|
lda abst+2
|
|
eor #$c3
|
|
cmp abs1+2
|
|
trap_ne ;store to abs data
|
|
stx abst+2 ;clear
|
|
lda zpt+3
|
|
eor #$c3
|
|
cmp zp1+3
|
|
trap_ne ;store to zp data
|
|
stx zpt+3 ;clear
|
|
lda abst+3
|
|
eor #$c3
|
|
cmp abs1+3
|
|
trap_ne ;store to abs data
|
|
stx abst+3 ;clear
|
|
next_test
|
|
|
|
; testing bit test & compares BIT CPX CPY CMP all addressing modes
|
|
; BIT - zp / abs
|
|
set_a $ff,0
|
|
bit zp1+3 ;00 - should set Z / clear NV
|
|
tst_a $ff,fz
|
|
set_a 1,0
|
|
bit zp1+2 ;41 - should set V (M6) / clear NZ
|
|
tst_a 1,fv
|
|
set_a 1,0
|
|
bit zp1+1 ;82 - should set N (M7) & Z / clear V
|
|
tst_a 1,fnz
|
|
set_a 1,0
|
|
bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z
|
|
tst_a 1,fnv
|
|
|
|
set_a $ff,$ff
|
|
bit zp1+3 ;00 - should set Z / clear NV
|
|
tst_a $ff,~fnv
|
|
set_a 1,$ff
|
|
bit zp1+2 ;41 - should set V (M6) / clear NZ
|
|
tst_a 1,~fnz
|
|
set_a 1,$ff
|
|
bit zp1+1 ;82 - should set N (M7) & Z / clear V
|
|
tst_a 1,~fv
|
|
set_a 1,$ff
|
|
bit zp1 ;c3 - should set N (M7) & V (M6) / clear Z
|
|
tst_a 1,~fz
|
|
|
|
set_a $ff,0
|
|
bit abs1+3 ;00 - should set Z / clear NV
|
|
tst_a $ff,fz
|
|
set_a 1,0
|
|
bit abs1+2 ;41 - should set V (M6) / clear NZ
|
|
tst_a 1,fv
|
|
set_a 1,0
|
|
bit abs1+1 ;82 - should set N (M7) & Z / clear V
|
|
tst_a 1,fnz
|
|
set_a 1,0
|
|
bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z
|
|
tst_a 1,fnv
|
|
|
|
set_a $ff,$ff
|
|
bit abs1+3 ;00 - should set Z / clear NV
|
|
tst_a $ff,~fnv
|
|
set_a 1,$ff
|
|
bit abs1+2 ;41 - should set V (M6) / clear NZ
|
|
tst_a 1,~fnz
|
|
set_a 1,$ff
|
|
bit abs1+1 ;82 - should set N (M7) & Z / clear V
|
|
tst_a 1,~fv
|
|
set_a 1,$ff
|
|
bit abs1 ;c3 - should set N (M7) & V (M6) / clear Z
|
|
tst_a 1,~fz
|
|
next_test
|
|
|
|
; CPX - zp / abs / #
|
|
set_x $80,0
|
|
cpx zp7f
|
|
tst_stat fc
|
|
dex
|
|
cpx zp7f
|
|
tst_stat fzc
|
|
dex
|
|
cpx zp7f
|
|
tst_x $7e,fn
|
|
set_x $80,$ff
|
|
cpx zp7f
|
|
tst_stat ~fnz
|
|
dex
|
|
cpx zp7f
|
|
tst_stat ~fn
|
|
dex
|
|
cpx zp7f
|
|
tst_x $7e,~fzc
|
|
|
|
set_x $80,0
|
|
cpx abs7f
|
|
tst_stat fc
|
|
dex
|
|
cpx abs7f
|
|
tst_stat fzc
|
|
dex
|
|
cpx abs7f
|
|
tst_x $7e,fn
|
|
set_x $80,$ff
|
|
cpx abs7f
|
|
tst_stat ~fnz
|
|
dex
|
|
cpx abs7f
|
|
tst_stat ~fn
|
|
dex
|
|
cpx abs7f
|
|
tst_x $7e,~fzc
|
|
|
|
set_x $80,0
|
|
cpx #$7f
|
|
tst_stat fc
|
|
dex
|
|
cpx #$7f
|
|
tst_stat fzc
|
|
dex
|
|
cpx #$7f
|
|
tst_x $7e,fn
|
|
set_x $80,$ff
|
|
cpx #$7f
|
|
tst_stat ~fnz
|
|
dex
|
|
cpx #$7f
|
|
tst_stat ~fn
|
|
dex
|
|
cpx #$7f
|
|
tst_x $7e,~fzc
|
|
next_test
|
|
|
|
; CPY - zp / abs / #
|
|
set_y $80,0
|
|
cpy zp7f
|
|
tst_stat fc
|
|
dey
|
|
cpy zp7f
|
|
tst_stat fzc
|
|
dey
|
|
cpy zp7f
|
|
tst_y $7e,fn
|
|
set_y $80,$ff
|
|
cpy zp7f
|
|
tst_stat ~fnz
|
|
dey
|
|
cpy zp7f
|
|
tst_stat ~fn
|
|
dey
|
|
cpy zp7f
|
|
tst_y $7e,~fzc
|
|
|
|
set_y $80,0
|
|
cpy abs7f
|
|
tst_stat fc
|
|
dey
|
|
cpy abs7f
|
|
tst_stat fzc
|
|
dey
|
|
cpy abs7f
|
|
tst_y $7e,fn
|
|
set_y $80,$ff
|
|
cpy abs7f
|
|
tst_stat ~fnz
|
|
dey
|
|
cpy abs7f
|
|
tst_stat ~fn
|
|
dey
|
|
cpy abs7f
|
|
tst_y $7e,~fzc
|
|
|
|
set_y $80,0
|
|
cpy #$7f
|
|
tst_stat fc
|
|
dey
|
|
cpy #$7f
|
|
tst_stat fzc
|
|
dey
|
|
cpy #$7f
|
|
tst_y $7e,fn
|
|
set_y $80,$ff
|
|
cpy #$7f
|
|
tst_stat ~fnz
|
|
dey
|
|
cpy #$7f
|
|
tst_stat ~fn
|
|
dey
|
|
cpy #$7f
|
|
tst_y $7e,~fzc
|
|
next_test
|
|
|
|
; CMP - zp / abs / #
|
|
set_a $80,0
|
|
cmp zp7f
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp zp7f
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp zp7f
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp zp7f
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp zp7f
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp zp7f
|
|
tst_a $7e,~fzc
|
|
|
|
set_a $80,0
|
|
cmp abs7f
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp abs7f
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp abs7f
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp abs7f
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp abs7f
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp abs7f
|
|
tst_a $7e,~fzc
|
|
|
|
set_a $80,0
|
|
cmp #$7f
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp #$7f
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp #$7f
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp #$7f
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp #$7f
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp #$7f
|
|
tst_a $7e,~fzc
|
|
|
|
ldx #4 ;with indexing by X
|
|
set_a $80,0
|
|
cmp zp1,x
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp zp1,x
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp zp1,x
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp zp1,x
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp zp1,x
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp zp1,x
|
|
tst_a $7e,~fzc
|
|
|
|
set_a $80,0
|
|
cmp abs1,x
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp abs1,x
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp abs1,x
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp abs1,x
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp abs1,x
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp abs1,x
|
|
tst_a $7e,~fzc
|
|
|
|
ldy #4 ;with indexing by Y
|
|
ldx #8 ;with indexed indirect
|
|
set_a $80,0
|
|
cmp abs1,y
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp abs1,y
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp abs1,y
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp abs1,y
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp abs1,y
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp abs1,y
|
|
tst_a $7e,~fzc
|
|
|
|
set_a $80,0
|
|
cmp (ind1,x)
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp (ind1,x)
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp (ind1,x)
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp (ind1,x)
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp (ind1,x)
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp (ind1,x)
|
|
tst_a $7e,~fzc
|
|
|
|
set_a $80,0
|
|
cmp (ind1),y
|
|
tst_a $80,fc
|
|
set_a $7f,0
|
|
cmp (ind1),y
|
|
tst_a $7f,fzc
|
|
set_a $7e,0
|
|
cmp (ind1),y
|
|
tst_a $7e,fn
|
|
set_a $80,$ff
|
|
cmp (ind1),y
|
|
tst_a $80,~fnz
|
|
set_a $7f,$ff
|
|
cmp (ind1),y
|
|
tst_a $7f,~fn
|
|
set_a $7e,$ff
|
|
cmp (ind1),y
|
|
tst_a $7e,~fzc
|
|
next_test
|
|
|
|
; testing shifts - ASL LSR ROL ROR all addressing modes
|
|
; shifts - accumulator
|
|
ldx #3
|
|
tasl
|
|
set_ax zp1,0
|
|
asl a
|
|
tst_ax rASL,fASL,0
|
|
dex
|
|
bpl tasl
|
|
ldx #3
|
|
tasl1
|
|
set_ax zp1,$ff
|
|
asl a
|
|
tst_ax rASL,fASL,$ff-fnzc
|
|
dex
|
|
bpl tasl1
|
|
|
|
ldx #3
|
|
tlsr
|
|
set_ax zp1,0
|
|
lsr a
|
|
tst_ax rLSR,fLSR,0
|
|
dex
|
|
bpl tlsr
|
|
ldx #3
|
|
tlsr1
|
|
set_ax zp1,$ff
|
|
lsr a
|
|
tst_ax rLSR,fLSR,$ff-fnzc
|
|
dex
|
|
bpl tlsr1
|
|
|
|
ldx #3
|
|
trol
|
|
set_ax zp1,0
|
|
rol a
|
|
tst_ax rROL,fROL,0
|
|
dex
|
|
bpl trol
|
|
ldx #3
|
|
trol1
|
|
set_ax zp1,$ff-fc
|
|
rol a
|
|
tst_ax rROL,fROL,$ff-fnzc
|
|
dex
|
|
bpl trol1
|
|
|
|
ldx #3
|
|
trolc
|
|
set_ax zp1,fc
|
|
rol a
|
|
tst_ax rROLc,fROLc,0
|
|
dex
|
|
bpl trolc
|
|
ldx #3
|
|
trolc1
|
|
set_ax zp1,$ff
|
|
rol a
|
|
tst_ax rROLc,fROLc,$ff-fnzc
|
|
dex
|
|
bpl trolc1
|
|
|
|
ldx #3
|
|
tror
|
|
set_ax zp1,0
|
|
ror a
|
|
tst_ax rROR,fROR,0
|
|
dex
|
|
bpl tror
|
|
ldx #3
|
|
tror1
|
|
set_ax zp1,$ff-fc
|
|
ror a
|
|
tst_ax rROR,fROR,$ff-fnzc
|
|
dex
|
|
bpl tror1
|
|
|
|
ldx #3
|
|
trorc
|
|
set_ax zp1,fc
|
|
ror a
|
|
tst_ax rRORc,fRORc,0
|
|
dex
|
|
bpl trorc
|
|
ldx #3
|
|
trorc1
|
|
set_ax zp1,$ff
|
|
ror a
|
|
tst_ax rRORc,fRORc,$ff-fnzc
|
|
dex
|
|
bpl trorc1
|
|
next_test
|
|
|
|
; shifts - zeropage
|
|
ldx #3
|
|
tasl2
|
|
set_z zp1,0
|
|
asl zpt
|
|
tst_z rASL,fASL,0
|
|
dex
|
|
bpl tasl2
|
|
ldx #3
|
|
tasl3
|
|
set_z zp1,$ff
|
|
asl zpt
|
|
tst_z rASL,fASL,$ff-fnzc
|
|
dex
|
|
bpl tasl3
|
|
|
|
ldx #3
|
|
tlsr2
|
|
set_z zp1,0
|
|
lsr zpt
|
|
tst_z rLSR,fLSR,0
|
|
dex
|
|
bpl tlsr2
|
|
ldx #3
|
|
tlsr3
|
|
set_z zp1,$ff
|
|
lsr zpt
|
|
tst_z rLSR,fLSR,$ff-fnzc
|
|
dex
|
|
bpl tlsr3
|
|
|
|
ldx #3
|
|
trol2
|
|
set_z zp1,0
|
|
rol zpt
|
|
tst_z rROL,fROL,0
|
|
dex
|
|
bpl trol2
|
|
ldx #3
|
|
trol3
|
|
set_z zp1,$ff-fc
|
|
rol zpt
|
|
tst_z rROL,fROL,$ff-fnzc
|
|
dex
|
|
bpl trol3
|
|
|
|
ldx #3
|
|
trolc2
|
|
set_z zp1,fc
|
|
rol zpt
|
|
tst_z rROLc,fROLc,0
|
|
dex
|
|
bpl trolc2
|
|
ldx #3
|
|
trolc3
|
|
set_z zp1,$ff
|
|
rol zpt
|
|
tst_z rROLc,fROLc,$ff-fnzc
|
|
dex
|
|
bpl trolc3
|
|
|
|
ldx #3
|
|
tror2
|
|
set_z zp1,0
|
|
ror zpt
|
|
tst_z rROR,fROR,0
|
|
dex
|
|
bpl tror2
|
|
ldx #3
|
|
tror3
|
|
set_z zp1,$ff-fc
|
|
ror zpt
|
|
tst_z rROR,fROR,$ff-fnzc
|
|
dex
|
|
bpl tror3
|
|
|
|
ldx #3
|
|
trorc2
|
|
set_z zp1,fc
|
|
ror zpt
|
|
tst_z rRORc,fRORc,0
|
|
dex
|
|
bpl trorc2
|
|
ldx #3
|
|
trorc3
|
|
set_z zp1,$ff
|
|
ror zpt
|
|
tst_z rRORc,fRORc,$ff-fnzc
|
|
dex
|
|
bpl trorc3
|
|
next_test
|
|
|
|
; shifts - absolute
|
|
ldx #3
|
|
tasl4
|
|
set_abs zp1,0
|
|
asl abst
|
|
tst_abs rASL,fASL,0
|
|
dex
|
|
bpl tasl4
|
|
ldx #3
|
|
tasl5
|
|
set_abs zp1,$ff
|
|
asl abst
|
|
tst_abs rASL,fASL,$ff-fnzc
|
|
dex
|
|
bpl tasl5
|
|
|
|
ldx #3
|
|
tlsr4
|
|
set_abs zp1,0
|
|
lsr abst
|
|
tst_abs rLSR,fLSR,0
|
|
dex
|
|
bpl tlsr4
|
|
ldx #3
|
|
tlsr5
|
|
set_abs zp1,$ff
|
|
lsr abst
|
|
tst_abs rLSR,fLSR,$ff-fnzc
|
|
dex
|
|
bpl tlsr5
|
|
|
|
ldx #3
|
|
trol4
|
|
set_abs zp1,0
|
|
rol abst
|
|
tst_abs rROL,fROL,0
|
|
dex
|
|
bpl trol4
|
|
ldx #3
|
|
trol5
|
|
set_abs zp1,$ff-fc
|
|
rol abst
|
|
tst_abs rROL,fROL,$ff-fnzc
|
|
dex
|
|
bpl trol5
|
|
|
|
ldx #3
|
|
trolc4
|
|
set_abs zp1,fc
|
|
rol abst
|
|
tst_abs rROLc,fROLc,0
|
|
dex
|
|
bpl trolc4
|
|
ldx #3
|
|
trolc5
|
|
set_abs zp1,$ff
|
|
rol abst
|
|
tst_abs rROLc,fROLc,$ff-fnzc
|
|
dex
|
|
bpl trolc5
|
|
|
|
ldx #3
|
|
tror4
|
|
set_abs zp1,0
|
|
ror abst
|
|
tst_abs rROR,fROR,0
|
|
dex
|
|
bpl tror4
|
|
ldx #3
|
|
tror5
|
|