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54768c6dc0
decimal mode tests can be disabled for the ADC & SBC instructions or also including the decimal mode bit of the processor status register.
356 lines
9.0 KiB
Plaintext
356 lines
9.0 KiB
Plaintext
; Verify decimal mode behavior
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; Written by Bruce Clark. This code is public domain.
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; see http://www.6502.org/tutorials/decimal_mode.html
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;
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; Returns:
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; ERROR = 0 if the test passed
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; ERROR = 1 if the test failed
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; modify the code at the DONE label for desired program end
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;
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; This routine requires 17 bytes of RAM -- 1 byte each for:
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; AR, CF, DA, DNVZC, ERROR, HA, HNVZC, N1, N1H, N1L, N2, N2L, NF, VF, and ZF
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; and 2 bytes for N2H
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;
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; Variables:
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; N1 and N2 are the two numbers to be added or subtracted
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; N1H, N1L, N2H, and N2L are the upper 4 bits and lower 4 bits of N1 and N2
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; DA and DNVZC are the actual accumulator and flag results in decimal mode
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; HA and HNVZC are the accumulator and flag results when N1 and N2 are
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; added or subtracted using binary arithmetic
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; AR, NF, VF, ZF, and CF are the predicted decimal mode accumulator and
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; flag results, calculated using binary arithmetic
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;
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; This program takes approximately 1 minute at 1 MHz (a few seconds more on
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; a 65C02 than a 6502 or 65816)
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;
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; Configuration:
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cputype = 0 ; 0 = 6502, 1 = 65C02, 2 = 65C816
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vld_bcd = 0 ; 0 = allow invalid bcd, 1 = valid bcd only
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chk_a = 1 ; check accumulator
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chk_n = 0 ; check sign (negative) flag
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chk_v = 0 ; check overflow flag
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chk_z = 0 ; check zero flag
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chk_c = 1 ; check carry flag
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end_of_test macro
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db $db ;execute 65C02 stop instruction
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endm
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bss
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org 0
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; operands - register Y = carry in
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N1 ds 1
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N2 ds 1
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; binary result
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HA ds 1
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HNVZC ds 1
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;04
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; decimal result
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DA ds 1
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DNVZC ds 1
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; predicted results
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AR ds 1
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NF ds 1
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;08
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VF ds 1
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ZF ds 1
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CF ds 1
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ERROR ds 1
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;0C
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; workspace
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N1L ds 1
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N1H ds 1
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N2L ds 1
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N2H ds 2
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code
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org $200
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TEST ldy #1 ; initialize Y (used to loop through carry flag values)
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sty ERROR ; store 1 in ERROR until the test passes
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lda #0 ; initialize N1 and N2
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sta N1
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sta N2
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LOOP1 lda N2 ; N2L = N2 & $0F
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and #$0F ; [1] see text
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if vld_bcd = 1
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cmp #$0a
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bcs NEXT2
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endif
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sta N2L
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lda N2 ; N2H = N2 & $F0
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and #$F0 ; [2] see text
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if vld_bcd = 1
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cmp #$a0
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bcs NEXT2
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endif
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sta N2H
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ora #$0F ; N2H+1 = (N2 & $F0) + $0F
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sta N2H+1
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LOOP2 lda N1 ; N1L = N1 & $0F
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and #$0F ; [3] see text
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if vld_bcd = 1
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cmp #$0a
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bcs NEXT1
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endif
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sta N1L
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lda N1 ; N1H = N1 & $F0
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and #$F0 ; [4] see text
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if vld_bcd = 1
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cmp #$a0
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bcs NEXT1
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endif
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sta N1H
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jsr ADD
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jsr A6502
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jsr COMPARE
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bne DONE
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jsr SUB
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jsr S6502
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jsr COMPARE
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bne DONE
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NEXT1 inc N1 ; [5] see text
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bne LOOP2 ; loop through all 256 values of N1
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NEXT2 inc N2 ; [6] see text
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bne LOOP1 ; loop through all 256 values of N2
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dey
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bpl LOOP1 ; loop through both values of the carry flag
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lda #0 ; test passed, so store 0 in ERROR
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sta ERROR
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DONE
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end_of_test
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; Calculate the actual decimal mode accumulator and flags, the accumulator
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; and flag results when N1 is added to N2 using binary arithmetic, the
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; predicted accumulator result, the predicted carry flag, and the predicted
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; V flag
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;
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ADD sed ; decimal mode
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cpy #1 ; set carry if Y = 1, clear carry if Y = 0
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lda N1
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adc N2
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sta DA ; actual accumulator result in decimal mode
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php
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pla
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sta DNVZC ; actual flags result in decimal mode
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cld ; binary mode
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cpy #1 ; set carry if Y = 1, clear carry if Y = 0
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lda N1
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adc N2
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sta HA ; accumulator result of N1+N2 using binary arithmetic
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php
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pla
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sta HNVZC ; flags result of N1+N2 using binary arithmetic
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cpy #1
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lda N1L
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adc N2L
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cmp #$0A
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ldx #0
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bcc A1
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inx
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adc #5 ; add 6 (carry is set)
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and #$0F
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sec
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A1 ora N1H
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;
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; if N1L + N2L < $0A, then add N2 & $F0
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; if N1L + N2L >= $0A, then add (N2 & $F0) + $0F + 1 (carry is set)
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;
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adc N2H,x
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php
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bcs A2
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cmp #$A0
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bcc A3
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A2 adc #$5F ; add $60 (carry is set)
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sec
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A3 sta AR ; predicted accumulator result
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php
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pla
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sta CF ; predicted carry result
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pla
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;
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; note that all 8 bits of the P register are stored in VF
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;
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sta VF ; predicted V flags
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rts
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; Calculate the actual decimal mode accumulator and flags, and the
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; accumulator and flag results when N2 is subtracted from N1 using binary
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; arithmetic
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;
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SUB sed ; decimal mode
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cpy #1 ; set carry if Y = 1, clear carry if Y = 0
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lda N1
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sbc N2
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sta DA ; actual accumulator result in decimal mode
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php
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pla
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sta DNVZC ; actual flags result in decimal mode
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cld ; binary mode
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cpy #1 ; set carry if Y = 1, clear carry if Y = 0
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lda N1
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sbc N2
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sta HA ; accumulator result of N1-N2 using binary arithmetic
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php
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pla
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sta HNVZC ; flags result of N1-N2 using binary arithmetic
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rts
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if cputype != 1
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; Calculate the predicted SBC accumulator result for the 6502 and 65816
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;
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SUB1 cpy #1 ; set carry if Y = 1, clear carry if Y = 0
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lda N1L
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sbc N2L
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ldx #0
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bcs S11
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inx
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sbc #5 ; subtract 6 (carry is clear)
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and #$0F
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clc
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S11 ora N1H
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;
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; if N1L - N2L >= 0, then subtract N2 & $F0
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; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
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;
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sbc N2H,x
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bcs S12
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sbc #$5F ; subtract $60 (carry is clear)
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S12 sta AR
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rts
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endif
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if cputype = 1
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; Calculate the predicted SBC accumulator result for the 6502 and 65C02
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;
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SUB2 cpy #1 ; set carry if Y = 1, clear carry if Y = 0
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lda N1L
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sbc N2L
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ldx #0
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bcs S21
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inx
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and #$0F
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clc
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S21 ora N1H
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;
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; if N1L - N2L >= 0, then subtract N2 & $F0
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; if N1L - N2L < 0, then subtract (N2 & $F0) + $0F + 1 (carry is clear)
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;
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sbc N2H,x
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bcs S22
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sbc #$5F ; subtract $60 (carry is clear)
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S22 cpx #0
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beq S23
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sbc #6
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S23 sta AR ; predicted accumulator result
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rts
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endif
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; Compare accumulator actual results to predicted results
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;
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; Return:
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; Z flag = 1 (BEQ branch) if same
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; Z flag = 0 (BNE branch) if different
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;
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COMPARE
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if chk_a = 1
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lda DA
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cmp AR
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bne C1
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endif
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if chk_n = 1
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lda DNVZC ; [7] see text
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eor NF
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and #$80 ; mask off N flag
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bne C1
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endif
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if chk_v = 1
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lda DNVZC ; [8] see text
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eor VF
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and #$40 ; mask off V flag
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bne C1 ; [9] see text
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endif
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if chk_z = 1
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lda DNVZC
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eor ZF ; mask off Z flag
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and #2
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bne C1 ; [10] see text
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endif
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if chk_c = 1
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lda DNVZC
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eor CF
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and #1 ; mask off C flag
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endif
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C1 rts
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; These routines store the predicted values for ADC and SBC for the 6502,
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; 65C02, and 65816 in AR, CF, NF, VF, and ZF
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if cputype = 0
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A6502 lda VF ; 6502
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;
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; since all 8 bits of the P register were stored in VF, bit 7 of VF contains
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; the N flag for NF
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;
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sta NF
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lda HNVZC
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sta ZF
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rts
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S6502 jsr SUB1
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lda HNVZC
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sta NF
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sta VF
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sta ZF
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sta CF
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rts
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endif
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if cputype = 1
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A6502 lda AR ; 65C02
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php
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pla
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sta NF
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sta ZF
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rts
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S6502 jsr SUB2
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lda AR
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php
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pla
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sta NF
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sta ZF
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lda HNVZC
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sta VF
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sta CF
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rts
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endif
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if cputype = 2
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A6502 lda AR ; 65C816
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php
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pla
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sta NF
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sta ZF
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rts
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S6502 jsr SUB1
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lda AR
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php
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pla
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sta NF
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sta ZF
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lda HNVZC
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sta VF
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sta CF
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rts
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endif
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end TEST
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