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6502bench/SourceGen/SGTestData/Expected/20240-large-overlay_cc65.cfg

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Fix 64tass output for non-loadable files 64tass wants to place its output into a 64KB region of memory, starting at the address "*" is set to, and continuing without wrapping around the end of the bank. Some files aren't meant to be handled that way, so we need to generate the output differently. If the file's output fits nicely, it's considered "loadable", and is generated in the usual way. If it doesn't, it's treated as "streamable", and the initial "* = addr" directive is omitted (leaving "*" at zero), and we go straight to ".logical" directives. 65816 code with an initial address outside bank 0 is treated as "streamable" whether or not the contents fit nicely in the designated 64K area. This caused a minor change to a few of the 65816 tests. A new test, 20240-large-overlay, exercises "streamable" by creating a file with eight overlapping 8KB segments that load at $8000. While the file as a whole fits in 64KB, it wouldn't if loaded at the desired start address. Also, updated the regression test harness to report assembler failure independently of overall test failure. This makes it easier to confirm that (say) ACME v0.96.4 still works with the code we generate, even though it doesn't match the expected output (which was generated for v0.97). (problem was raised in issue #98)
2021-08-02 00:09:52 +00:00
# 6502bench SourceGen generated linker script for 20240-large-overlay
MEMORY {
MAIN: file=%O, start=%S, size=65536;
# MEM000: file=%O, start=$8000, size=8192;
# MEM001: file=%O, start=$8000, size=8192;
# MEM002: file=%O, start=$8000, size=8192;
# MEM003: file=%O, start=$8000, size=8192;
# MEM004: file=%O, start=$8000, size=8192;
# MEM005: file=%O, start=$8000, size=8192;
# MEM006: file=%O, start=$8000, size=8192;
# MEM007: file=%O, start=$8000, size=8192;
}
SEGMENTS {
CODE: load=MAIN, type=rw;
# SEG000: load=MEM000, type=rw;
# SEG001: load=MEM001, type=rw;
# SEG002: load=MEM002, type=rw;
# SEG003: load=MEM003, type=rw;
# SEG004: load=MEM004, type=rw;
# SEG005: load=MEM005, type=rw;
# SEG006: load=MEM006, type=rw;
# SEG007: load=MEM007, type=rw;
}
FEATURES {}
SYMBOLS {}
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